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cmpa_prog_in_progress.rscustomer_defined.rsdcfg_cc_socu_dflt.rsdcfg_cc_socu_pin.rsenable_fa_mode.rsheader.rsimage_key_revoke.rsns_fw_version.rsprince_region0_iv_body0.rsprince_region0_iv_body1.rsprince_region0_iv_body10.rsprince_region0_iv_body11.rsprince_region0_iv_body2.rsprince_region0_iv_body3.rsprince_region0_iv_body4.rsprince_region0_iv_body5.rsprince_region0_iv_body6.rsprince_region0_iv_body7.rsprince_region0_iv_body8.rsprince_region0_iv_body9.rsprince_region0_iv_code0.rsprince_region0_iv_code1.rsprince_region0_iv_code10.rsprince_region0_iv_code11.rsprince_region0_iv_code12.rsprince_region0_iv_code13.rsprince_region0_iv_code2.rsprince_region0_iv_code3.rsprince_region0_iv_code4.rsprince_region0_iv_code5.rsprince_region0_iv_code6.rsprince_region0_iv_code7.rsprince_region0_iv_code8.rsprince_region0_iv_code9.rsprince_region0_iv_header0.rsprince_region0_iv_header1.rsprince_region1_iv_body0.rsprince_region1_iv_body1.rsprince_region1_iv_body10.rsprince_region1_iv_body11.rsprince_region1_iv_body2.rsprince_region1_iv_body3.rsprince_region1_iv_body4.rsprince_region1_iv_body5.rsprince_region1_iv_body6.rsprince_region1_iv_body7.rsprince_region1_iv_body8.rsprince_region1_iv_body9.rsprince_region1_iv_code0.rsprince_region1_iv_code1.rsprince_region1_iv_code10.rsprince_region1_iv_code11.rsprince_region1_iv_code12.rsprince_region1_iv_code13.rsprince_region1_iv_code2.rsprince_region1_iv_code3.rsprince_region1_iv_code4.rsprince_region1_iv_code5.rsprince_region1_iv_code6.rsprince_region1_iv_code7.rsprince_region1_iv_code8.rsprince_region1_iv_code9.rsprince_region1_iv_header0.rsprince_region1_iv_header1.rsprince_region2_iv_body0.rsprince_region2_iv_body1.rsprince_region2_iv_body10.rsprince_region2_iv_body11.rsprince_region2_iv_body2.rsprince_region2_iv_body3.rsprince_region2_iv_body4.rsprince_region2_iv_body5.rsprince_region2_iv_body6.rsprince_region2_iv_body7.rsprince_region2_iv_body8.rsprince_region2_iv_body9.rsprince_region2_iv_code0.rsprince_region2_iv_code1.rsprince_region2_iv_code10.rsprince_region2_iv_code11.rsprince_region2_iv_code12.rsprince_region2_iv_code13.rsprince_region2_iv_code2.rsprince_region2_iv_code3.rsprince_region2_iv_code4.rsprince_region2_iv_code5.rsprince_region2_iv_code6.rsprince_region2_iv_code7.rsprince_region2_iv_code8.rsprince_region2_iv_code9.rsprince_region2_iv_header0.rsprince_region2_iv_header1.rsrotkh_revoke.rss_fw_version.rssha256_digest.rsvendor_usage.rsversion.rs
flash_cmpa
flash_key_store
activation_code.rsheader.rsprince_region0_body0.rsprince_region0_body1.rsprince_region0_body10.rsprince_region0_body11.rsprince_region0_body2.rsprince_region0_body3.rsprince_region0_body4.rsprince_region0_body5.rsprince_region0_body6.rsprince_region0_body7.rsprince_region0_body8.rsprince_region0_body9.rsprince_region0_header0.rsprince_region0_header1.rsprince_region0_key_code0.rsprince_region0_key_code1.rsprince_region0_key_code10.rsprince_region0_key_code11.rsprince_region0_key_code12.rsprince_region0_key_code13.rsprince_region0_key_code2.rsprince_region0_key_code3.rsprince_region0_key_code4.rsprince_region0_key_code5.rsprince_region0_key_code6.rsprince_region0_key_code7.rsprince_region0_key_code8.rsprince_region0_key_code9.rsprince_region1_body0.rsprince_region1_body1.rsprince_region1_body10.rsprince_region1_body11.rsprince_region1_body2.rsprince_region1_body3.rsprince_region1_body4.rsprince_region1_body5.rsprince_region1_body6.rsprince_region1_body7.rsprince_region1_body8.rsprince_region1_body9.rsprince_region1_header0.rsprince_region1_header1.rsprince_region1_key_code0.rsprince_region1_key_code1.rsprince_region1_key_code10.rsprince_region1_key_code11.rsprince_region1_key_code12.rsprince_region1_key_code13.rsprince_region1_key_code2.rsprince_region1_key_code3.rsprince_region1_key_code4.rsprince_region1_key_code5.rsprince_region1_key_code6.rsprince_region1_key_code7.rsprince_region1_key_code8.rsprince_region1_key_code9.rsprince_region2_body0.rsprince_region2_body1.rsprince_region2_body10.rsprince_region2_body11.rsprince_region2_body2.rsprince_region2_body3.rsprince_region2_body4.rsprince_region2_body5.rsprince_region2_body6.rsprince_region2_body7.rsprince_region2_body8.rsprince_region2_body9.rsprince_region2_header0.rsprince_region2_header1.rsprince_region2_key_code0.rsprince_region2_key_code1.rsprince_region2_key_code10.rsprince_region2_key_code11.rsprince_region2_key_code12.rsprince_region2_key_code13.rsprince_region2_key_code2.rsprince_region2_key_code3.rsprince_region2_key_code4.rsprince_region2_key_code5.rsprince_region2_key_code6.rsprince_region2_key_code7.rsprince_region2_key_code8.rsprince_region2_key_code9.rspuf_discharge_time_in_ms.rssbkey_body0.rssbkey_body1.rssbkey_body10.rssbkey_body11.rssbkey_body2.rssbkey_body3.rssbkey_body4.rssbkey_body5.rssbkey_body6.rssbkey_body7.rssbkey_body8.rssbkey_body9.rssbkey_header0.rssbkey_header1.rssbkey_key_code0.rssbkey_key_code1.rssbkey_key_code10.rssbkey_key_code11.rssbkey_key_code12.rssbkey_key_code13.rssbkey_key_code2.rssbkey_key_code3.rssbkey_key_code4.rssbkey_key_code5.rssbkey_key_code6.rssbkey_key_code7.rssbkey_key_code8.rssbkey_key_code9.rsuds_body0.rsuds_body1.rsuds_body10.rsuds_body11.rsuds_body2.rsuds_body3.rsuds_body4.rsuds_body5.rsuds_body6.rsuds_body7.rsuds_body8.rsuds_body9.rsuds_header0.rsuds_header1.rsuds_key_code0.rsuds_key_code1.rsuds_key_code10.rsuds_key_code11.rsuds_key_code12.rsuds_key_code13.rsuds_key_code2.rsuds_key_code3.rsuds_key_code4.rsuds_key_code5.rsuds_key_code6.rsuds_key_code7.rsuds_key_code8.rsuds_key_code9.rsuser_kek_body0.rsuser_kek_body1.rsuser_kek_body10.rsuser_kek_body11.rsuser_kek_body2.rsuser_kek_body3.rsuser_kek_body4.rsuser_kek_body5.rsuser_kek_body6.rsuser_kek_body7.rsuser_kek_body8.rsuser_kek_body9.rsuser_kek_header0.rsuser_kek_header1.rsuser_kek_key_code0.rsuser_kek_key_code1.rsuser_kek_key_code10.rsuser_kek_key_code11.rsuser_kek_key_code12.rsuser_kek_key_code13.rsuser_kek_key_code2.rsuser_kek_key_code3.rsuser_kek_key_code4.rsuser_kek_key_code5.rsuser_kek_key_code6.rsuser_kek_key_code7.rsuser_kek_key_code8.rsuser_kek_key_code9.rs
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adcclkdiv.rsadcclksel.rsahbclkctrl0.rsahbclkctrl1.rsahbclkctrl2.rsahbclkctrlclr.rsahbclkctrlset.rsahbclkdiv.rsahbmatprio.rsautoclkgateoverride.rsclkoutdiv.rsclkoutsel.rsclock_ctrl.rsclockgenupdatelockout.rscomp_int_ctrl.rscomp_int_status.rscpboot.rscpstat.rscpu0nstckcal.rscpu0stckcal.rscpu1stckcal.rscpucfg.rscpuctrl.rsctimerclksel0.rsctimerclksel1.rsctimerclksel2.rsctimerclksel3.rsctimerclksel4.rsctimerclkselx0.rsctimerclkselx1.rsctimerclkselx2.rsctimerclkselx3.rsctimerclkselx4.rsdebug_auth_beacon.rsdebug_features.rsdebug_features_dp.rsdebug_lock_en.rsdevice_id0.rsdieid.rsfcclksel0.rsfcclksel1.rsfcclksel2.rsfcclksel3.rsfcclksel4.rsfcclksel5.rsfcclksel6.rsfcclksel7.rsfcclkselx0.rsfcclkselx1.rsfcclkselx2.rsfcclkselx3.rsfcclkselx4.rsfcclkselx5.rsfcclkselx6.rsfcclkselx7.rsflexfrg0ctrl.rsflexfrg1ctrl.rsflexfrg2ctrl.rsflexfrg3ctrl.rsflexfrg4ctrl.rsflexfrg5ctrl.rsflexfrg6ctrl.rsflexfrg7ctrl.rsflexfrgxctrl0.rsflexfrgxctrl1.rsflexfrgxctrl2.rsflexfrgxctrl3.rsflexfrgxctrl4.rsflexfrgxctrl5.rsflexfrgxctrl6.rsflexfrgxctrl7.rsfmccr.rsfmcflush.rsfrohfdiv.rsgpiopsync.rshslspiclksel.rskey_block.rsmainclksela.rsmainclkselb.rsmclkclksel.rsmclkdiv.rsmclkio.rsmemoryremap.rsnmisrc.rspll0clkdiv.rspll0clksel.rspll0ctrl.rspll0ndec.rspll0pdec.rspll0sscg0.rspll0sscg1.rspll0stat.rspll1clksel.rspll1ctrl.rspll1mdec.rspll1ndec.rspll1pdec.rspll1stat.rspresetctrl0.rspresetctrl1.rspresetctrl2.rspresetctrlclr.rspresetctrlset.rssctclkdiv.rssctclksel.rssdioclkctrl.rssdioclkdiv.rssdioclksel.rsswr_reset.rssystickclkdiv0.rssystickclkdiv1.rssystickclksel0.rssystickclksel1.rssystickclkselx0.rssystickclkselx1.rstraceclkdiv.rstraceclksel.rsusb0clkdiv.rsusb0clksel.rsusb0needclkctrl.rsusb0needclkstat.rsusb1needclkctrl.rsusb1needclkstat.rswdtclkdiv.rs
sysctl
usart0
usb1
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utick0
wwdt
nb
r0
stable_deref_trait
typenum
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void
volatile_register
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#[doc = "Reader of register FCCLKSEL3"]
pub type R = crate::R<u32, super::FCCLKSEL3>;
#[doc = "Writer for register FCCLKSEL3"]
pub type W = crate::W<u32, super::FCCLKSEL3>;
#[doc = "Register FCCLKSEL3 `reset()`'s with value 0x07"]
impl crate::ResetValue for super::FCCLKSEL3 {
    type Type = u32;
    #[inline(always)]
    fn reset_value() -> Self::Type {
        0x07
    }
}
#[doc = "Flexcomm Interface 3 clock source select for Fractional Rate Divider.\n\nValue on reset: 7"]
#[derive(Clone, Copy, Debug, PartialEq)]
#[repr(u8)]
pub enum SEL_A {
    #[doc = "0: Main clock."]
    ENUM_0X0 = 0,
    #[doc = "1: system PLL divided clock."]
    ENUM_0X1 = 1,
    #[doc = "2: FRO 12 MHz clock."]
    ENUM_0X2 = 2,
    #[doc = "3: FRO 96 MHz clock."]
    ENUM_0X3 = 3,
    #[doc = "4: FRO 1MHz clock."]
    ENUM_0X4 = 4,
    #[doc = "5: MCLK clock."]
    ENUM_0X5 = 5,
    #[doc = "6: Oscillator 32 kHz clock."]
    ENUM_0X6 = 6,
    #[doc = "7: No clock."]
    ENUM_0X7 = 7,
}
impl From<SEL_A> for u8 {
    #[inline(always)]
    fn from(variant: SEL_A) -> Self {
        variant as _
    }
}
#[doc = "Reader of field `SEL`"]
pub type SEL_R = crate::R<u8, SEL_A>;
impl SEL_R {
    #[doc = r"Get enumerated values variant"]
    #[inline(always)]
    pub fn variant(&self) -> SEL_A {
        match self.bits {
            0 => SEL_A::ENUM_0X0,
            1 => SEL_A::ENUM_0X1,
            2 => SEL_A::ENUM_0X2,
            3 => SEL_A::ENUM_0X3,
            4 => SEL_A::ENUM_0X4,
            5 => SEL_A::ENUM_0X5,
            6 => SEL_A::ENUM_0X6,
            7 => SEL_A::ENUM_0X7,
            _ => unreachable!(),
        }
    }
    #[doc = "Checks if the value of the field is `ENUM_0X0`"]
    #[inline(always)]
    pub fn is_enum_0x0(&self) -> bool {
        *self == SEL_A::ENUM_0X0
    }
    #[doc = "Checks if the value of the field is `ENUM_0X1`"]
    #[inline(always)]
    pub fn is_enum_0x1(&self) -> bool {
        *self == SEL_A::ENUM_0X1
    }
    #[doc = "Checks if the value of the field is `ENUM_0X2`"]
    #[inline(always)]
    pub fn is_enum_0x2(&self) -> bool {
        *self == SEL_A::ENUM_0X2
    }
    #[doc = "Checks if the value of the field is `ENUM_0X3`"]
    #[inline(always)]
    pub fn is_enum_0x3(&self) -> bool {
        *self == SEL_A::ENUM_0X3
    }
    #[doc = "Checks if the value of the field is `ENUM_0X4`"]
    #[inline(always)]
    pub fn is_enum_0x4(&self) -> bool {
        *self == SEL_A::ENUM_0X4
    }
    #[doc = "Checks if the value of the field is `ENUM_0X5`"]
    #[inline(always)]
    pub fn is_enum_0x5(&self) -> bool {
        *self == SEL_A::ENUM_0X5
    }
    #[doc = "Checks if the value of the field is `ENUM_0X6`"]
    #[inline(always)]
    pub fn is_enum_0x6(&self) -> bool {
        *self == SEL_A::ENUM_0X6
    }
    #[doc = "Checks if the value of the field is `ENUM_0X7`"]
    #[inline(always)]
    pub fn is_enum_0x7(&self) -> bool {
        *self == SEL_A::ENUM_0X7
    }
}
#[doc = "Write proxy for field `SEL`"]
pub struct SEL_W<'a> {
    w: &'a mut W,
}
impl<'a> SEL_W<'a> {
    #[doc = r"Writes `variant` to the field"]
    #[inline(always)]
    pub fn variant(self, variant: SEL_A) -> &'a mut W {
        {
            self.bits(variant.into())
        }
    }
    #[doc = "Main clock."]
    #[inline(always)]
    pub fn enum_0x0(self) -> &'a mut W {
        self.variant(SEL_A::ENUM_0X0)
    }
    #[doc = "system PLL divided clock."]
    #[inline(always)]
    pub fn enum_0x1(self) -> &'a mut W {
        self.variant(SEL_A::ENUM_0X1)
    }
    #[doc = "FRO 12 MHz clock."]
    #[inline(always)]
    pub fn enum_0x2(self) -> &'a mut W {
        self.variant(SEL_A::ENUM_0X2)
    }
    #[doc = "FRO 96 MHz clock."]
    #[inline(always)]
    pub fn enum_0x3(self) -> &'a mut W {
        self.variant(SEL_A::ENUM_0X3)
    }
    #[doc = "FRO 1MHz clock."]
    #[inline(always)]
    pub fn enum_0x4(self) -> &'a mut W {
        self.variant(SEL_A::ENUM_0X4)
    }
    #[doc = "MCLK clock."]
    #[inline(always)]
    pub fn enum_0x5(self) -> &'a mut W {
        self.variant(SEL_A::ENUM_0X5)
    }
    #[doc = "Oscillator 32 kHz clock."]
    #[inline(always)]
    pub fn enum_0x6(self) -> &'a mut W {
        self.variant(SEL_A::ENUM_0X6)
    }
    #[doc = "No clock."]
    #[inline(always)]
    pub fn enum_0x7(self) -> &'a mut W {
        self.variant(SEL_A::ENUM_0X7)
    }
    #[doc = r"Writes raw bits to the field"]
    #[inline(always)]
    pub fn bits(self, value: u8) -> &'a mut W {
        self.w.bits = (self.w.bits & !0x07) | ((value as u32) & 0x07);
        self.w
    }
}
impl R {
    #[doc = "Bits 0:2 - Flexcomm Interface 3 clock source select for Fractional Rate Divider."]
    #[inline(always)]
    pub fn sel(&self) -> SEL_R {
        SEL_R::new((self.bits & 0x07) as u8)
    }
}
impl W {
    #[doc = "Bits 0:2 - Flexcomm Interface 3 clock source select for Fractional Rate Divider."]
    #[inline(always)]
    pub fn sel(&mut self) -> SEL_W {
        SEL_W { w: self }
    }
}