Files
aligned
as_slice
bare_metal
bitfield
block_buffer
block_cipher
cortex_m
cortex_m_rt
cortex_m_semihosting
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generic_array
lpc55_hal
lpc55_pac
adc0
ahb_secure_ctrl
anactrl
casper
crc_engine
ctimer0
dbgmailbox
dma0
flash
flash_cfpa0
cmpa_prog_in_progress.rscustomer_defined.rsdcfg_cc_socu_dflt.rsdcfg_cc_socu_pin.rsenable_fa_mode.rsheader.rsimage_key_revoke.rsns_fw_version.rsprince_region0_iv_body0.rsprince_region0_iv_body1.rsprince_region0_iv_body10.rsprince_region0_iv_body11.rsprince_region0_iv_body2.rsprince_region0_iv_body3.rsprince_region0_iv_body4.rsprince_region0_iv_body5.rsprince_region0_iv_body6.rsprince_region0_iv_body7.rsprince_region0_iv_body8.rsprince_region0_iv_body9.rsprince_region0_iv_code0.rsprince_region0_iv_code1.rsprince_region0_iv_code10.rsprince_region0_iv_code11.rsprince_region0_iv_code12.rsprince_region0_iv_code13.rsprince_region0_iv_code2.rsprince_region0_iv_code3.rsprince_region0_iv_code4.rsprince_region0_iv_code5.rsprince_region0_iv_code6.rsprince_region0_iv_code7.rsprince_region0_iv_code8.rsprince_region0_iv_code9.rsprince_region0_iv_header0.rsprince_region0_iv_header1.rsprince_region1_iv_body0.rsprince_region1_iv_body1.rsprince_region1_iv_body10.rsprince_region1_iv_body11.rsprince_region1_iv_body2.rsprince_region1_iv_body3.rsprince_region1_iv_body4.rsprince_region1_iv_body5.rsprince_region1_iv_body6.rsprince_region1_iv_body7.rsprince_region1_iv_body8.rsprince_region1_iv_body9.rsprince_region1_iv_code0.rsprince_region1_iv_code1.rsprince_region1_iv_code10.rsprince_region1_iv_code11.rsprince_region1_iv_code12.rsprince_region1_iv_code13.rsprince_region1_iv_code2.rsprince_region1_iv_code3.rsprince_region1_iv_code4.rsprince_region1_iv_code5.rsprince_region1_iv_code6.rsprince_region1_iv_code7.rsprince_region1_iv_code8.rsprince_region1_iv_code9.rsprince_region1_iv_header0.rsprince_region1_iv_header1.rsprince_region2_iv_body0.rsprince_region2_iv_body1.rsprince_region2_iv_body10.rsprince_region2_iv_body11.rsprince_region2_iv_body2.rsprince_region2_iv_body3.rsprince_region2_iv_body4.rsprince_region2_iv_body5.rsprince_region2_iv_body6.rsprince_region2_iv_body7.rsprince_region2_iv_body8.rsprince_region2_iv_body9.rsprince_region2_iv_code0.rsprince_region2_iv_code1.rsprince_region2_iv_code10.rsprince_region2_iv_code11.rsprince_region2_iv_code12.rsprince_region2_iv_code13.rsprince_region2_iv_code2.rsprince_region2_iv_code3.rsprince_region2_iv_code4.rsprince_region2_iv_code5.rsprince_region2_iv_code6.rsprince_region2_iv_code7.rsprince_region2_iv_code8.rsprince_region2_iv_code9.rsprince_region2_iv_header0.rsprince_region2_iv_header1.rsrotkh_revoke.rss_fw_version.rssha256_digest.rsvendor_usage.rsversion.rs
flash_cmpa
flash_key_store
activation_code.rsheader.rsprince_region0_body0.rsprince_region0_body1.rsprince_region0_body10.rsprince_region0_body11.rsprince_region0_body2.rsprince_region0_body3.rsprince_region0_body4.rsprince_region0_body5.rsprince_region0_body6.rsprince_region0_body7.rsprince_region0_body8.rsprince_region0_body9.rsprince_region0_header0.rsprince_region0_header1.rsprince_region0_key_code0.rsprince_region0_key_code1.rsprince_region0_key_code10.rsprince_region0_key_code11.rsprince_region0_key_code12.rsprince_region0_key_code13.rsprince_region0_key_code2.rsprince_region0_key_code3.rsprince_region0_key_code4.rsprince_region0_key_code5.rsprince_region0_key_code6.rsprince_region0_key_code7.rsprince_region0_key_code8.rsprince_region0_key_code9.rsprince_region1_body0.rsprince_region1_body1.rsprince_region1_body10.rsprince_region1_body11.rsprince_region1_body2.rsprince_region1_body3.rsprince_region1_body4.rsprince_region1_body5.rsprince_region1_body6.rsprince_region1_body7.rsprince_region1_body8.rsprince_region1_body9.rsprince_region1_header0.rsprince_region1_header1.rsprince_region1_key_code0.rsprince_region1_key_code1.rsprince_region1_key_code10.rsprince_region1_key_code11.rsprince_region1_key_code12.rsprince_region1_key_code13.rsprince_region1_key_code2.rsprince_region1_key_code3.rsprince_region1_key_code4.rsprince_region1_key_code5.rsprince_region1_key_code6.rsprince_region1_key_code7.rsprince_region1_key_code8.rsprince_region1_key_code9.rsprince_region2_body0.rsprince_region2_body1.rsprince_region2_body10.rsprince_region2_body11.rsprince_region2_body2.rsprince_region2_body3.rsprince_region2_body4.rsprince_region2_body5.rsprince_region2_body6.rsprince_region2_body7.rsprince_region2_body8.rsprince_region2_body9.rsprince_region2_header0.rsprince_region2_header1.rsprince_region2_key_code0.rsprince_region2_key_code1.rsprince_region2_key_code10.rsprince_region2_key_code11.rsprince_region2_key_code12.rsprince_region2_key_code13.rsprince_region2_key_code2.rsprince_region2_key_code3.rsprince_region2_key_code4.rsprince_region2_key_code5.rsprince_region2_key_code6.rsprince_region2_key_code7.rsprince_region2_key_code8.rsprince_region2_key_code9.rspuf_discharge_time_in_ms.rssbkey_body0.rssbkey_body1.rssbkey_body10.rssbkey_body11.rssbkey_body2.rssbkey_body3.rssbkey_body4.rssbkey_body5.rssbkey_body6.rssbkey_body7.rssbkey_body8.rssbkey_body9.rssbkey_header0.rssbkey_header1.rssbkey_key_code0.rssbkey_key_code1.rssbkey_key_code10.rssbkey_key_code11.rssbkey_key_code12.rssbkey_key_code13.rssbkey_key_code2.rssbkey_key_code3.rssbkey_key_code4.rssbkey_key_code5.rssbkey_key_code6.rssbkey_key_code7.rssbkey_key_code8.rssbkey_key_code9.rsuds_body0.rsuds_body1.rsuds_body10.rsuds_body11.rsuds_body2.rsuds_body3.rsuds_body4.rsuds_body5.rsuds_body6.rsuds_body7.rsuds_body8.rsuds_body9.rsuds_header0.rsuds_header1.rsuds_key_code0.rsuds_key_code1.rsuds_key_code10.rsuds_key_code11.rsuds_key_code12.rsuds_key_code13.rsuds_key_code2.rsuds_key_code3.rsuds_key_code4.rsuds_key_code5.rsuds_key_code6.rsuds_key_code7.rsuds_key_code8.rsuds_key_code9.rsuser_kek_body0.rsuser_kek_body1.rsuser_kek_body10.rsuser_kek_body11.rsuser_kek_body2.rsuser_kek_body3.rsuser_kek_body4.rsuser_kek_body5.rsuser_kek_body6.rsuser_kek_body7.rsuser_kek_body8.rsuser_kek_body9.rsuser_kek_header0.rsuser_kek_header1.rsuser_kek_key_code0.rsuser_kek_key_code1.rsuser_kek_key_code10.rsuser_kek_key_code11.rsuser_kek_key_code12.rsuser_kek_key_code13.rsuser_kek_key_code2.rsuser_kek_key_code3.rsuser_kek_key_code4.rsuser_kek_key_code5.rsuser_kek_key_code6.rsuser_kek_key_code7.rsuser_kek_key_code8.rsuser_kek_key_code9.rs
flexcomm0
gint0
gpio
hashcrypt
i2c0
i2s0
inputmux
iocon
mailbox
mrt0
ostimer
pint
plu
pmc
powerquad
prince
puf
rng
rtc
sau
scn_scb
sct0
sdif
secgpio
spi0
syscon
adcclkdiv.rsadcclksel.rsahbclkctrl0.rsahbclkctrl1.rsahbclkctrl2.rsahbclkctrlclr.rsahbclkctrlset.rsahbclkdiv.rsahbmatprio.rsautoclkgateoverride.rsclkoutdiv.rsclkoutsel.rsclock_ctrl.rsclockgenupdatelockout.rscomp_int_ctrl.rscomp_int_status.rscpboot.rscpstat.rscpu0nstckcal.rscpu0stckcal.rscpu1stckcal.rscpucfg.rscpuctrl.rsctimerclksel0.rsctimerclksel1.rsctimerclksel2.rsctimerclksel3.rsctimerclksel4.rsctimerclkselx0.rsctimerclkselx1.rsctimerclkselx2.rsctimerclkselx3.rsctimerclkselx4.rsdebug_auth_beacon.rsdebug_features.rsdebug_features_dp.rsdebug_lock_en.rsdevice_id0.rsdieid.rsfcclksel0.rsfcclksel1.rsfcclksel2.rsfcclksel3.rsfcclksel4.rsfcclksel5.rsfcclksel6.rsfcclksel7.rsfcclkselx0.rsfcclkselx1.rsfcclkselx2.rsfcclkselx3.rsfcclkselx4.rsfcclkselx5.rsfcclkselx6.rsfcclkselx7.rsflexfrg0ctrl.rsflexfrg1ctrl.rsflexfrg2ctrl.rsflexfrg3ctrl.rsflexfrg4ctrl.rsflexfrg5ctrl.rsflexfrg6ctrl.rsflexfrg7ctrl.rsflexfrgxctrl0.rsflexfrgxctrl1.rsflexfrgxctrl2.rsflexfrgxctrl3.rsflexfrgxctrl4.rsflexfrgxctrl5.rsflexfrgxctrl6.rsflexfrgxctrl7.rsfmccr.rsfmcflush.rsfrohfdiv.rsgpiopsync.rshslspiclksel.rskey_block.rsmainclksela.rsmainclkselb.rsmclkclksel.rsmclkdiv.rsmclkio.rsmemoryremap.rsnmisrc.rspll0clkdiv.rspll0clksel.rspll0ctrl.rspll0ndec.rspll0pdec.rspll0sscg0.rspll0sscg1.rspll0stat.rspll1clksel.rspll1ctrl.rspll1mdec.rspll1ndec.rspll1pdec.rspll1stat.rspresetctrl0.rspresetctrl1.rspresetctrl2.rspresetctrlclr.rspresetctrlset.rssctclkdiv.rssctclksel.rssdioclkctrl.rssdioclkdiv.rssdioclksel.rsswr_reset.rssystickclkdiv0.rssystickclkdiv1.rssystickclksel0.rssystickclksel1.rssystickclkselx0.rssystickclkselx1.rstraceclkdiv.rstraceclksel.rsusb0clkdiv.rsusb0clksel.rsusb0needclkctrl.rsusb0needclkstat.rsusb1needclkctrl.rsusb1needclkstat.rswdtclkdiv.rs
sysctl
usart0
usb1
usbfsh
usbhsh
usbphy
utick0
wwdt
nb
r0
stable_deref_trait
typenum
usb_device
usbd_serial
vcell
void
volatile_register
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#[doc = r"Register block"]
#[repr(C)]
pub struct RegisterBlock {
    #[doc = "0x00 - Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending."]
    pub ir: IR,
    #[doc = "0x04 - Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR."]
    pub tcr: TCR,
    #[doc = "0x08 - Timer Counter"]
    pub tc: TC,
    #[doc = "0x0c - Prescale Register"]
    pub pr: PR,
    #[doc = "0x10 - Prescale Counter"]
    pub pc: PC,
    #[doc = "0x14 - Match Control Register"]
    pub mcr: MCR,
    #[doc = "0x18 - Match Register . MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC."]
    pub mr: [MR; 4],
    #[doc = "0x28 - Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place."]
    pub ccr: CCR,
    #[doc = "0x2c - Capture Register . CR is loaded with the value of TC when there is an event on the CAPn. input."]
    pub cr: [CR; 4],
    #[doc = "0x3c - External Match Register. The EMR controls the match function and the external match pins."]
    pub emr: EMR,
    _reserved10: [u8; 48usize],
    #[doc = "0x70 - Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting."]
    pub ctcr: CTCR,
    #[doc = "0x74 - PWM Control Register. This register enables PWM mode for the external match pins."]
    pub pwmc: PWMC,
    #[doc = "0x78 - Match Shadow Register"]
    pub msr: [MSR; 4],
}
#[doc = "Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending.\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ir](ir) module"]
pub type IR = crate::Reg<u32, _IR>;
#[allow(missing_docs)]
#[doc(hidden)]
pub struct _IR;
#[doc = "`read()` method returns [ir::R](ir::R) reader structure"]
impl crate::Readable for IR {}
#[doc = "`write(|w| ..)` method takes [ir::W](ir::W) writer structure"]
impl crate::Writable for IR {}
#[doc = "Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending."]
pub mod ir;
#[doc = "Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR.\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [tcr](tcr) module"]
pub type TCR = crate::Reg<u32, _TCR>;
#[allow(missing_docs)]
#[doc(hidden)]
pub struct _TCR;
#[doc = "`read()` method returns [tcr::R](tcr::R) reader structure"]
impl crate::Readable for TCR {}
#[doc = "`write(|w| ..)` method takes [tcr::W](tcr::W) writer structure"]
impl crate::Writable for TCR {}
#[doc = "Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR."]
pub mod tcr;
#[doc = "Timer Counter\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [tc](tc) module"]
pub type TC = crate::Reg<u32, _TC>;
#[allow(missing_docs)]
#[doc(hidden)]
pub struct _TC;
#[doc = "`read()` method returns [tc::R](tc::R) reader structure"]
impl crate::Readable for TC {}
#[doc = "`write(|w| ..)` method takes [tc::W](tc::W) writer structure"]
impl crate::Writable for TC {}
#[doc = "Timer Counter"]
pub mod tc;
#[doc = "Prescale Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pr](pr) module"]
pub type PR = crate::Reg<u32, _PR>;
#[allow(missing_docs)]
#[doc(hidden)]
pub struct _PR;
#[doc = "`read()` method returns [pr::R](pr::R) reader structure"]
impl crate::Readable for PR {}
#[doc = "`write(|w| ..)` method takes [pr::W](pr::W) writer structure"]
impl crate::Writable for PR {}
#[doc = "Prescale Register"]
pub mod pr;
#[doc = "Prescale Counter\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pc](pc) module"]
pub type PC = crate::Reg<u32, _PC>;
#[allow(missing_docs)]
#[doc(hidden)]
pub struct _PC;
#[doc = "`read()` method returns [pc::R](pc::R) reader structure"]
impl crate::Readable for PC {}
#[doc = "`write(|w| ..)` method takes [pc::W](pc::W) writer structure"]
impl crate::Writable for PC {}
#[doc = "Prescale Counter"]
pub mod pc;
#[doc = "Match Control Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [mcr](mcr) module"]
pub type MCR = crate::Reg<u32, _MCR>;
#[allow(missing_docs)]
#[doc(hidden)]
pub struct _MCR;
#[doc = "`read()` method returns [mcr::R](mcr::R) reader structure"]
impl crate::Readable for MCR {}
#[doc = "`write(|w| ..)` method takes [mcr::W](mcr::W) writer structure"]
impl crate::Writable for MCR {}
#[doc = "Match Control Register"]
pub mod mcr;
#[doc = "Match Register . MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC.\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [mr](mr) module"]
pub type MR = crate::Reg<u32, _MR>;
#[allow(missing_docs)]
#[doc(hidden)]
pub struct _MR;
#[doc = "`read()` method returns [mr::R](mr::R) reader structure"]
impl crate::Readable for MR {}
#[doc = "`write(|w| ..)` method takes [mr::W](mr::W) writer structure"]
impl crate::Writable for MR {}
#[doc = "Match Register . MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC."]
pub mod mr;
#[doc = "Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place.\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ccr](ccr) module"]
pub type CCR = crate::Reg<u32, _CCR>;
#[allow(missing_docs)]
#[doc(hidden)]
pub struct _CCR;
#[doc = "`read()` method returns [ccr::R](ccr::R) reader structure"]
impl crate::Readable for CCR {}
#[doc = "`write(|w| ..)` method takes [ccr::W](ccr::W) writer structure"]
impl crate::Writable for CCR {}
#[doc = "Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place."]
pub mod ccr;
#[doc = "Capture Register . CR is loaded with the value of TC when there is an event on the CAPn. input.\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cr](cr) module"]
pub type CR = crate::Reg<u32, _CR>;
#[allow(missing_docs)]
#[doc(hidden)]
pub struct _CR;
#[doc = "`read()` method returns [cr::R](cr::R) reader structure"]
impl crate::Readable for CR {}
#[doc = "Capture Register . CR is loaded with the value of TC when there is an event on the CAPn. input."]
pub mod cr;
#[doc = "External Match Register. The EMR controls the match function and the external match pins.\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [emr](emr) module"]
pub type EMR = crate::Reg<u32, _EMR>;
#[allow(missing_docs)]
#[doc(hidden)]
pub struct _EMR;
#[doc = "`read()` method returns [emr::R](emr::R) reader structure"]
impl crate::Readable for EMR {}
#[doc = "`write(|w| ..)` method takes [emr::W](emr::W) writer structure"]
impl crate::Writable for EMR {}
#[doc = "External Match Register. The EMR controls the match function and the external match pins."]
pub mod emr;
#[doc = "Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting.\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctcr](ctcr) module"]
pub type CTCR = crate::Reg<u32, _CTCR>;
#[allow(missing_docs)]
#[doc(hidden)]
pub struct _CTCR;
#[doc = "`read()` method returns [ctcr::R](ctcr::R) reader structure"]
impl crate::Readable for CTCR {}
#[doc = "`write(|w| ..)` method takes [ctcr::W](ctcr::W) writer structure"]
impl crate::Writable for CTCR {}
#[doc = "Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting."]
pub mod ctcr;
#[doc = "PWM Control Register. This register enables PWM mode for the external match pins.\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pwmc](pwmc) module"]
pub type PWMC = crate::Reg<u32, _PWMC>;
#[allow(missing_docs)]
#[doc(hidden)]
pub struct _PWMC;
#[doc = "`read()` method returns [pwmc::R](pwmc::R) reader structure"]
impl crate::Readable for PWMC {}
#[doc = "`write(|w| ..)` method takes [pwmc::W](pwmc::W) writer structure"]
impl crate::Writable for PWMC {}
#[doc = "PWM Control Register. This register enables PWM mode for the external match pins."]
pub mod pwmc;
#[doc = "Match Shadow Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [msr](msr) module"]
pub type MSR = crate::Reg<u32, _MSR>;
#[allow(missing_docs)]
#[doc(hidden)]
pub struct _MSR;
#[doc = "`read()` method returns [msr::R](msr::R) reader structure"]
impl crate::Readable for MSR {}
#[doc = "`write(|w| ..)` method takes [msr::W](msr::W) writer structure"]
impl crate::Writable for MSR {}
#[doc = "Match Shadow Register"]
pub mod msr;