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lpc55_pac
adc0
ahb_secure_ctrl
anactrl
casper
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dma0
flash
flash_cfpa0
cmpa_prog_in_progress.rscustomer_defined.rsdcfg_cc_socu_dflt.rsdcfg_cc_socu_pin.rsenable_fa_mode.rsheader.rsimage_key_revoke.rsns_fw_version.rsprince_region0_iv_body0.rsprince_region0_iv_body1.rsprince_region0_iv_body10.rsprince_region0_iv_body11.rsprince_region0_iv_body2.rsprince_region0_iv_body3.rsprince_region0_iv_body4.rsprince_region0_iv_body5.rsprince_region0_iv_body6.rsprince_region0_iv_body7.rsprince_region0_iv_body8.rsprince_region0_iv_body9.rsprince_region0_iv_code0.rsprince_region0_iv_code1.rsprince_region0_iv_code10.rsprince_region0_iv_code11.rsprince_region0_iv_code12.rsprince_region0_iv_code13.rsprince_region0_iv_code2.rsprince_region0_iv_code3.rsprince_region0_iv_code4.rsprince_region0_iv_code5.rsprince_region0_iv_code6.rsprince_region0_iv_code7.rsprince_region0_iv_code8.rsprince_region0_iv_code9.rsprince_region0_iv_header0.rsprince_region0_iv_header1.rsprince_region1_iv_body0.rsprince_region1_iv_body1.rsprince_region1_iv_body10.rsprince_region1_iv_body11.rsprince_region1_iv_body2.rsprince_region1_iv_body3.rsprince_region1_iv_body4.rsprince_region1_iv_body5.rsprince_region1_iv_body6.rsprince_region1_iv_body7.rsprince_region1_iv_body8.rsprince_region1_iv_body9.rsprince_region1_iv_code0.rsprince_region1_iv_code1.rsprince_region1_iv_code10.rsprince_region1_iv_code11.rsprince_region1_iv_code12.rsprince_region1_iv_code13.rsprince_region1_iv_code2.rsprince_region1_iv_code3.rsprince_region1_iv_code4.rsprince_region1_iv_code5.rsprince_region1_iv_code6.rsprince_region1_iv_code7.rsprince_region1_iv_code8.rsprince_region1_iv_code9.rsprince_region1_iv_header0.rsprince_region1_iv_header1.rsprince_region2_iv_body0.rsprince_region2_iv_body1.rsprince_region2_iv_body10.rsprince_region2_iv_body11.rsprince_region2_iv_body2.rsprince_region2_iv_body3.rsprince_region2_iv_body4.rsprince_region2_iv_body5.rsprince_region2_iv_body6.rsprince_region2_iv_body7.rsprince_region2_iv_body8.rsprince_region2_iv_body9.rsprince_region2_iv_code0.rsprince_region2_iv_code1.rsprince_region2_iv_code10.rsprince_region2_iv_code11.rsprince_region2_iv_code12.rsprince_region2_iv_code13.rsprince_region2_iv_code2.rsprince_region2_iv_code3.rsprince_region2_iv_code4.rsprince_region2_iv_code5.rsprince_region2_iv_code6.rsprince_region2_iv_code7.rsprince_region2_iv_code8.rsprince_region2_iv_code9.rsprince_region2_iv_header0.rsprince_region2_iv_header1.rsrotkh_revoke.rss_fw_version.rssha256_digest.rsvendor_usage.rsversion.rs
flash_cmpa
flash_key_store
activation_code.rsheader.rsprince_region0_body0.rsprince_region0_body1.rsprince_region0_body10.rsprince_region0_body11.rsprince_region0_body2.rsprince_region0_body3.rsprince_region0_body4.rsprince_region0_body5.rsprince_region0_body6.rsprince_region0_body7.rsprince_region0_body8.rsprince_region0_body9.rsprince_region0_header0.rsprince_region0_header1.rsprince_region0_key_code0.rsprince_region0_key_code1.rsprince_region0_key_code10.rsprince_region0_key_code11.rsprince_region0_key_code12.rsprince_region0_key_code13.rsprince_region0_key_code2.rsprince_region0_key_code3.rsprince_region0_key_code4.rsprince_region0_key_code5.rsprince_region0_key_code6.rsprince_region0_key_code7.rsprince_region0_key_code8.rsprince_region0_key_code9.rsprince_region1_body0.rsprince_region1_body1.rsprince_region1_body10.rsprince_region1_body11.rsprince_region1_body2.rsprince_region1_body3.rsprince_region1_body4.rsprince_region1_body5.rsprince_region1_body6.rsprince_region1_body7.rsprince_region1_body8.rsprince_region1_body9.rsprince_region1_header0.rsprince_region1_header1.rsprince_region1_key_code0.rsprince_region1_key_code1.rsprince_region1_key_code10.rsprince_region1_key_code11.rsprince_region1_key_code12.rsprince_region1_key_code13.rsprince_region1_key_code2.rsprince_region1_key_code3.rsprince_region1_key_code4.rsprince_region1_key_code5.rsprince_region1_key_code6.rsprince_region1_key_code7.rsprince_region1_key_code8.rsprince_region1_key_code9.rsprince_region2_body0.rsprince_region2_body1.rsprince_region2_body10.rsprince_region2_body11.rsprince_region2_body2.rsprince_region2_body3.rsprince_region2_body4.rsprince_region2_body5.rsprince_region2_body6.rsprince_region2_body7.rsprince_region2_body8.rsprince_region2_body9.rsprince_region2_header0.rsprince_region2_header1.rsprince_region2_key_code0.rsprince_region2_key_code1.rsprince_region2_key_code10.rsprince_region2_key_code11.rsprince_region2_key_code12.rsprince_region2_key_code13.rsprince_region2_key_code2.rsprince_region2_key_code3.rsprince_region2_key_code4.rsprince_region2_key_code5.rsprince_region2_key_code6.rsprince_region2_key_code7.rsprince_region2_key_code8.rsprince_region2_key_code9.rspuf_discharge_time_in_ms.rssbkey_body0.rssbkey_body1.rssbkey_body10.rssbkey_body11.rssbkey_body2.rssbkey_body3.rssbkey_body4.rssbkey_body5.rssbkey_body6.rssbkey_body7.rssbkey_body8.rssbkey_body9.rssbkey_header0.rssbkey_header1.rssbkey_key_code0.rssbkey_key_code1.rssbkey_key_code10.rssbkey_key_code11.rssbkey_key_code12.rssbkey_key_code13.rssbkey_key_code2.rssbkey_key_code3.rssbkey_key_code4.rssbkey_key_code5.rssbkey_key_code6.rssbkey_key_code7.rssbkey_key_code8.rssbkey_key_code9.rsuds_body0.rsuds_body1.rsuds_body10.rsuds_body11.rsuds_body2.rsuds_body3.rsuds_body4.rsuds_body5.rsuds_body6.rsuds_body7.rsuds_body8.rsuds_body9.rsuds_header0.rsuds_header1.rsuds_key_code0.rsuds_key_code1.rsuds_key_code10.rsuds_key_code11.rsuds_key_code12.rsuds_key_code13.rsuds_key_code2.rsuds_key_code3.rsuds_key_code4.rsuds_key_code5.rsuds_key_code6.rsuds_key_code7.rsuds_key_code8.rsuds_key_code9.rsuser_kek_body0.rsuser_kek_body1.rsuser_kek_body10.rsuser_kek_body11.rsuser_kek_body2.rsuser_kek_body3.rsuser_kek_body4.rsuser_kek_body5.rsuser_kek_body6.rsuser_kek_body7.rsuser_kek_body8.rsuser_kek_body9.rsuser_kek_header0.rsuser_kek_header1.rsuser_kek_key_code0.rsuser_kek_key_code1.rsuser_kek_key_code10.rsuser_kek_key_code11.rsuser_kek_key_code12.rsuser_kek_key_code13.rsuser_kek_key_code2.rsuser_kek_key_code3.rsuser_kek_key_code4.rsuser_kek_key_code5.rsuser_kek_key_code6.rsuser_kek_key_code7.rsuser_kek_key_code8.rsuser_kek_key_code9.rs
flexcomm0
gint0
gpio
hashcrypt
i2c0
i2s0
inputmux
iocon
mailbox
mrt0
ostimer
pint
plu
pmc
powerquad
prince
puf
rng
rtc
sau
scn_scb
sct0
sdif
secgpio
spi0
syscon
adcclkdiv.rsadcclksel.rsahbclkctrl0.rsahbclkctrl1.rsahbclkctrl2.rsahbclkctrlclr.rsahbclkctrlset.rsahbclkdiv.rsahbmatprio.rsautoclkgateoverride.rsclkoutdiv.rsclkoutsel.rsclock_ctrl.rsclockgenupdatelockout.rscomp_int_ctrl.rscomp_int_status.rscpboot.rscpstat.rscpu0nstckcal.rscpu0stckcal.rscpu1stckcal.rscpucfg.rscpuctrl.rsctimerclksel0.rsctimerclksel1.rsctimerclksel2.rsctimerclksel3.rsctimerclksel4.rsctimerclkselx0.rsctimerclkselx1.rsctimerclkselx2.rsctimerclkselx3.rsctimerclkselx4.rsdebug_auth_beacon.rsdebug_features.rsdebug_features_dp.rsdebug_lock_en.rsdevice_id0.rsdieid.rsfcclksel0.rsfcclksel1.rsfcclksel2.rsfcclksel3.rsfcclksel4.rsfcclksel5.rsfcclksel6.rsfcclksel7.rsfcclkselx0.rsfcclkselx1.rsfcclkselx2.rsfcclkselx3.rsfcclkselx4.rsfcclkselx5.rsfcclkselx6.rsfcclkselx7.rsflexfrg0ctrl.rsflexfrg1ctrl.rsflexfrg2ctrl.rsflexfrg3ctrl.rsflexfrg4ctrl.rsflexfrg5ctrl.rsflexfrg6ctrl.rsflexfrg7ctrl.rsflexfrgxctrl0.rsflexfrgxctrl1.rsflexfrgxctrl2.rsflexfrgxctrl3.rsflexfrgxctrl4.rsflexfrgxctrl5.rsflexfrgxctrl6.rsflexfrgxctrl7.rsfmccr.rsfmcflush.rsfrohfdiv.rsgpiopsync.rshslspiclksel.rskey_block.rsmainclksela.rsmainclkselb.rsmclkclksel.rsmclkdiv.rsmclkio.rsmemoryremap.rsnmisrc.rspll0clkdiv.rspll0clksel.rspll0ctrl.rspll0ndec.rspll0pdec.rspll0sscg0.rspll0sscg1.rspll0stat.rspll1clksel.rspll1ctrl.rspll1mdec.rspll1ndec.rspll1pdec.rspll1stat.rspresetctrl0.rspresetctrl1.rspresetctrl2.rspresetctrlclr.rspresetctrlset.rssctclkdiv.rssctclksel.rssdioclkctrl.rssdioclkdiv.rssdioclksel.rsswr_reset.rssystickclkdiv0.rssystickclkdiv1.rssystickclksel0.rssystickclksel1.rssystickclkselx0.rssystickclkselx1.rstraceclkdiv.rstraceclksel.rsusb0clkdiv.rsusb0clksel.rsusb0needclkctrl.rsusb0needclkstat.rsusb1needclkctrl.rsusb1needclkstat.rswdtclkdiv.rs
sysctl
usart0
usb1
usbfsh
usbhsh
usbphy
utick0
wwdt
nb
r0
stable_deref_trait
typenum
usb_device
usbd_serial
vcell
void
volatile_register
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#[doc = "Reader of register AHBCLKDIV"]
pub type R = crate::R<u32, super::AHBCLKDIV>;
#[doc = "Writer for register AHBCLKDIV"]
pub type W = crate::W<u32, super::AHBCLKDIV>;
#[doc = "Register AHBCLKDIV `reset()`'s with value 0"]
impl crate::ResetValue for super::AHBCLKDIV {
    type Type = u32;
    #[inline(always)]
    fn reset_value() -> Self::Type {
        0
    }
}
#[doc = "Reader of field `DIV`"]
pub type DIV_R = crate::R<u8, u8>;
#[doc = "Write proxy for field `DIV`"]
pub struct DIV_W<'a> {
    w: &'a mut W,
}
impl<'a> DIV_W<'a> {
    #[doc = r"Writes raw bits to the field"]
    #[inline(always)]
    pub unsafe fn bits(self, value: u8) -> &'a mut W {
        self.w.bits = (self.w.bits & !0xff) | ((value as u32) & 0xff);
        self.w
    }
}
#[doc = "Resets the divider counter.\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum RESET_AW {
    #[doc = "0: Divider is not reset."]
    RELEASED = 0,
    #[doc = "1: Divider is reset."]
    ASSERTED = 1,
}
impl From<RESET_AW> for bool {
    #[inline(always)]
    fn from(variant: RESET_AW) -> Self {
        variant as u8 != 0
    }
}
#[doc = "Write proxy for field `RESET`"]
pub struct RESET_W<'a> {
    w: &'a mut W,
}
impl<'a> RESET_W<'a> {
    #[doc = r"Writes `variant` to the field"]
    #[inline(always)]
    pub fn variant(self, variant: RESET_AW) -> &'a mut W {
        {
            self.bit(variant.into())
        }
    }
    #[doc = "Divider is not reset."]
    #[inline(always)]
    pub fn released(self) -> &'a mut W {
        self.variant(RESET_AW::RELEASED)
    }
    #[doc = "Divider is reset."]
    #[inline(always)]
    pub fn asserted(self) -> &'a mut W {
        self.variant(RESET_AW::ASSERTED)
    }
    #[doc = r"Sets the field bit"]
    #[inline(always)]
    pub fn set_bit(self) -> &'a mut W {
        self.bit(true)
    }
    #[doc = r"Clears the field bit"]
    #[inline(always)]
    pub fn clear_bit(self) -> &'a mut W {
        self.bit(false)
    }
    #[doc = r"Writes raw bits to the field"]
    #[inline(always)]
    pub fn bit(self, value: bool) -> &'a mut W {
        self.w.bits = (self.w.bits & !(0x01 << 29)) | (((value as u32) & 0x01) << 29);
        self.w
    }
}
#[doc = "Halts the divider counter.\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum HALT_A {
    #[doc = "0: Divider clock is running."]
    RUN = 0,
    #[doc = "1: Divider clock is stoped."]
    HALT = 1,
}
impl From<HALT_A> for bool {
    #[inline(always)]
    fn from(variant: HALT_A) -> Self {
        variant as u8 != 0
    }
}
#[doc = "Reader of field `HALT`"]
pub type HALT_R = crate::R<bool, HALT_A>;
impl HALT_R {
    #[doc = r"Get enumerated values variant"]
    #[inline(always)]
    pub fn variant(&self) -> HALT_A {
        match self.bits {
            false => HALT_A::RUN,
            true => HALT_A::HALT,
        }
    }
    #[doc = "Checks if the value of the field is `RUN`"]
    #[inline(always)]
    pub fn is_run(&self) -> bool {
        *self == HALT_A::RUN
    }
    #[doc = "Checks if the value of the field is `HALT`"]
    #[inline(always)]
    pub fn is_halt(&self) -> bool {
        *self == HALT_A::HALT
    }
}
#[doc = "Write proxy for field `HALT`"]
pub struct HALT_W<'a> {
    w: &'a mut W,
}
impl<'a> HALT_W<'a> {
    #[doc = r"Writes `variant` to the field"]
    #[inline(always)]
    pub fn variant(self, variant: HALT_A) -> &'a mut W {
        {
            self.bit(variant.into())
        }
    }
    #[doc = "Divider clock is running."]
    #[inline(always)]
    pub fn run(self) -> &'a mut W {
        self.variant(HALT_A::RUN)
    }
    #[doc = "Divider clock is stoped."]
    #[inline(always)]
    pub fn halt(self) -> &'a mut W {
        self.variant(HALT_A::HALT)
    }
    #[doc = r"Sets the field bit"]
    #[inline(always)]
    pub fn set_bit(self) -> &'a mut W {
        self.bit(true)
    }
    #[doc = r"Clears the field bit"]
    #[inline(always)]
    pub fn clear_bit(self) -> &'a mut W {
        self.bit(false)
    }
    #[doc = r"Writes raw bits to the field"]
    #[inline(always)]
    pub fn bit(self, value: bool) -> &'a mut W {
        self.w.bits = (self.w.bits & !(0x01 << 30)) | (((value as u32) & 0x01) << 30);
        self.w
    }
}
#[doc = "Divider status flag.\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum REQFLAG_A {
    #[doc = "0: Divider clock is stable."]
    STABLE = 0,
    #[doc = "1: Clock frequency is not stable."]
    ONGOING = 1,
}
impl From<REQFLAG_A> for bool {
    #[inline(always)]
    fn from(variant: REQFLAG_A) -> Self {
        variant as u8 != 0
    }
}
#[doc = "Reader of field `REQFLAG`"]
pub type REQFLAG_R = crate::R<bool, REQFLAG_A>;
impl REQFLAG_R {
    #[doc = r"Get enumerated values variant"]
    #[inline(always)]
    pub fn variant(&self) -> REQFLAG_A {
        match self.bits {
            false => REQFLAG_A::STABLE,
            true => REQFLAG_A::ONGOING,
        }
    }
    #[doc = "Checks if the value of the field is `STABLE`"]
    #[inline(always)]
    pub fn is_stable(&self) -> bool {
        *self == REQFLAG_A::STABLE
    }
    #[doc = "Checks if the value of the field is `ONGOING`"]
    #[inline(always)]
    pub fn is_ongoing(&self) -> bool {
        *self == REQFLAG_A::ONGOING
    }
}
impl R {
    #[doc = "Bits 0:7 - Clock divider value."]
    #[inline(always)]
    pub fn div(&self) -> DIV_R {
        DIV_R::new((self.bits & 0xff) as u8)
    }
    #[doc = "Bit 30 - Halts the divider counter."]
    #[inline(always)]
    pub fn halt(&self) -> HALT_R {
        HALT_R::new(((self.bits >> 30) & 0x01) != 0)
    }
    #[doc = "Bit 31 - Divider status flag."]
    #[inline(always)]
    pub fn reqflag(&self) -> REQFLAG_R {
        REQFLAG_R::new(((self.bits >> 31) & 0x01) != 0)
    }
}
impl W {
    #[doc = "Bits 0:7 - Clock divider value."]
    #[inline(always)]
    pub fn div(&mut self) -> DIV_W {
        DIV_W { w: self }
    }
    #[doc = "Bit 29 - Resets the divider counter."]
    #[inline(always)]
    pub fn reset(&mut self) -> RESET_W {
        RESET_W { w: self }
    }
    #[doc = "Bit 30 - Halts the divider counter."]
    #[inline(always)]
    pub fn halt(&mut self) -> HALT_W {
        HALT_W { w: self }
    }
}