gint.rs.html -- source

Files

aligned

lib.rs sealed.rs

as_slice

bare_metal

bitfield

block_buffer

block_cipher

errors.rs lib.rs

cortex_m

cortex_m_rt

cortex_m_semihosting

debug.rs export.rs hio.rs lib.rs macros.rs nr.rs

digest

digest.rs errors.rs fixed.rs lib.rs variable.rs xof.rs

embedded_hal

blocking

delay.rs i2c.rs mod.rs rng.rs serial.rs spi.rs

digital

mod.rs v1.rs v1_compat.rs v2.rs v2_compat.rs

adc.rs fmt.rs lib.rs prelude.rs serial.rs spi.rs timer.rs watchdog.rs

generic_array

arr.rs functional.rs hex.rs impls.rs iter.rs lib.rs sequence.rs

lpc55_hal

lpc55_pac

adc0

ahb_secure_ctrl

cpu0_lock_reg.rs cpu1_lock_reg.rs master_sec_anti_pol_reg.rs master_sec_level.rs misc_ctrl_dp_reg.rs misc_ctrl_reg.rs sec_cpu_int_mask0.rs sec_cpu_int_mask1.rs sec_ctrl_ahb_port10_slave0_rule.rs sec_ctrl_ahb_port10_slave1_rule.rs sec_ctrl_ahb_port8_slave0_rule.rs sec_ctrl_ahb_port8_slave1_rule.rs sec_ctrl_ahb_port9_slave0_rule.rs sec_ctrl_ahb_port9_slave1_rule.rs sec_ctrl_ahb_sec_ctrl_mem_rule.rs sec_ctrl_apb_bridge0_mem_ctrl0.rs sec_ctrl_apb_bridge0_mem_ctrl1.rs sec_ctrl_apb_bridge0_mem_ctrl2.rs sec_ctrl_apb_bridge1_mem_ctrl0.rs sec_ctrl_apb_bridge1_mem_ctrl1.rs sec_ctrl_apb_bridge1_mem_ctrl2.rs sec_ctrl_apb_bridge1_mem_ctrl3.rs sec_ctrl_apb_bridge_slave_rule.rs sec_ctrl_flash_mem_rule0.rs sec_ctrl_flash_mem_rule1.rs sec_ctrl_flash_mem_rule2.rs sec_ctrl_flash_rom_slave_rule.rs sec_ctrl_ram0_mem_rule0.rs sec_ctrl_ram0_mem_rule1.rs sec_ctrl_ram0_slave_rule.rs sec_ctrl_ram1_mem_rule0.rs sec_ctrl_ram1_mem_rule1.rs sec_ctrl_ram1_slave_rule.rs sec_ctrl_ram2_mem_rule0.rs sec_ctrl_ram2_mem_rule1.rs sec_ctrl_ram2_slave_rule.rs sec_ctrl_ram3_mem_rule0.rs sec_ctrl_ram3_mem_rule1.rs sec_ctrl_ram3_slave_rule.rs sec_ctrl_ram4_mem_rule0.rs sec_ctrl_ram4_slave_rule.rs sec_ctrl_ramx_mem_rule0.rs sec_ctrl_ramx_slave_rule.rs sec_ctrl_rom_mem_rule0.rs sec_ctrl_rom_mem_rule1.rs sec_ctrl_rom_mem_rule2.rs sec_ctrl_rom_mem_rule3.rs sec_ctrl_usb_hs_mem_rule.rs sec_ctrl_usb_hs_slave_rule.rs sec_gpio_mask0.rs sec_gpio_mask1.rs sec_mask_lock.rs sec_vio_addr.rs sec_vio_info_valid.rs sec_vio_misc_info.rs

anactrl

analog_ctrl_status.rs bod_dcdc_int_ctrl.rs bod_dcdc_int_status.rs freq_me_ctrl.rs fro192m_ctrl.rs fro192m_status.rs ringo0_ctrl.rs ringo1_ctrl.rs ringo2_ctrl.rs usbhs_phy_ctrl.rs xo32m_ctrl.rs xo32m_status.rs

casper

areg.rs breg.rs creg.rs ctrl0.rs ctrl1.rs dreg.rs intenclr.rs intenset.rs intstat.rs loader.rs lock.rs mask.rs remask.rs res0.rs res1.rs res2.rs res3.rs status.rs

crc_engine

mode.rs seed.rs sum.rs wr_data.rs

ctimer0

ccr.rs cr.rs ctcr.rs emr.rs ir.rs mcr.rs mr.rs msr.rs pc.rs pr.rs pwmc.rs tc.rs tcr.rs

dbgmailbox

csw.rs id.rs request.rs return_.rs

dma0

channel

cfg.rs ctlstat.rs xfercfg.rs

abort0.rs active0.rs busy0.rs channel.rs ctrl.rs enableclr0.rs enableset0.rs errint0.rs inta0.rs intb0.rs intenclr0.rs intenset0.rs intstat.rs settrig0.rs setvalid0.rs srambase.rs

flash

cmd.rs dataw.rs event.rs int_clr_enable.rs int_clr_status.rs int_enable.rs int_set_enable.rs int_set_status.rs int_status.rs module_id.rs starta.rs stopa.rs

flash_cfpa0

cmpa_prog_in_progress.rs customer_defined.rs dcfg_cc_socu_dflt.rs dcfg_cc_socu_pin.rs enable_fa_mode.rs header.rs image_key_revoke.rs ns_fw_version.rs prince_region0_iv_body0.rs prince_region0_iv_body1.rs prince_region0_iv_body10.rs prince_region0_iv_body11.rs prince_region0_iv_body2.rs prince_region0_iv_body3.rs prince_region0_iv_body4.rs prince_region0_iv_body5.rs prince_region0_iv_body6.rs prince_region0_iv_body7.rs prince_region0_iv_body8.rs prince_region0_iv_body9.rs prince_region0_iv_code0.rs prince_region0_iv_code1.rs prince_region0_iv_code10.rs prince_region0_iv_code11.rs prince_region0_iv_code12.rs prince_region0_iv_code13.rs prince_region0_iv_code2.rs prince_region0_iv_code3.rs prince_region0_iv_code4.rs prince_region0_iv_code5.rs prince_region0_iv_code6.rs prince_region0_iv_code7.rs prince_region0_iv_code8.rs prince_region0_iv_code9.rs prince_region0_iv_header0.rs prince_region0_iv_header1.rs prince_region1_iv_body0.rs prince_region1_iv_body1.rs prince_region1_iv_body10.rs prince_region1_iv_body11.rs prince_region1_iv_body2.rs prince_region1_iv_body3.rs prince_region1_iv_body4.rs prince_region1_iv_body5.rs prince_region1_iv_body6.rs prince_region1_iv_body7.rs prince_region1_iv_body8.rs prince_region1_iv_body9.rs prince_region1_iv_code0.rs prince_region1_iv_code1.rs prince_region1_iv_code10.rs prince_region1_iv_code11.rs prince_region1_iv_code12.rs prince_region1_iv_code13.rs prince_region1_iv_code2.rs prince_region1_iv_code3.rs prince_region1_iv_code4.rs prince_region1_iv_code5.rs prince_region1_iv_code6.rs prince_region1_iv_code7.rs prince_region1_iv_code8.rs prince_region1_iv_code9.rs prince_region1_iv_header0.rs prince_region1_iv_header1.rs prince_region2_iv_body0.rs prince_region2_iv_body1.rs prince_region2_iv_body10.rs prince_region2_iv_body11.rs prince_region2_iv_body2.rs prince_region2_iv_body3.rs prince_region2_iv_body4.rs prince_region2_iv_body5.rs prince_region2_iv_body6.rs prince_region2_iv_body7.rs prince_region2_iv_body8.rs prince_region2_iv_body9.rs prince_region2_iv_code0.rs prince_region2_iv_code1.rs prince_region2_iv_code10.rs prince_region2_iv_code11.rs prince_region2_iv_code12.rs prince_region2_iv_code13.rs prince_region2_iv_code2.rs prince_region2_iv_code3.rs prince_region2_iv_code4.rs prince_region2_iv_code5.rs prince_region2_iv_code6.rs prince_region2_iv_code7.rs prince_region2_iv_code8.rs prince_region2_iv_code9.rs prince_region2_iv_header0.rs prince_region2_iv_header1.rs rotkh_revoke.rs s_fw_version.rs sha256_digest.rs vendor_usage.rs version.rs

flash_cmpa

boot_cfg.rs cc_socu_dflt.rs cc_socu_pin.rs customer_defined.rs prince_base_addr.rs prince_sr_0.rs prince_sr_1.rs prince_sr_2.rs rotkh.rs sdio_cfg.rs secure_boot_cfg.rs sha256_digest.rs spi_flash_cfg.rs usb_id.rs vendor_usage.rs xtal_16mhz_capabank_trim.rs xtal_32khz_capabank_trim.rs

flash_key_store

activation_code.rs header.rs prince_region0_body0.rs prince_region0_body1.rs prince_region0_body10.rs prince_region0_body11.rs prince_region0_body2.rs prince_region0_body3.rs prince_region0_body4.rs prince_region0_body5.rs prince_region0_body6.rs prince_region0_body7.rs prince_region0_body8.rs prince_region0_body9.rs prince_region0_header0.rs prince_region0_header1.rs prince_region0_key_code0.rs prince_region0_key_code1.rs prince_region0_key_code10.rs prince_region0_key_code11.rs prince_region0_key_code12.rs prince_region0_key_code13.rs prince_region0_key_code2.rs prince_region0_key_code3.rs prince_region0_key_code4.rs prince_region0_key_code5.rs prince_region0_key_code6.rs prince_region0_key_code7.rs prince_region0_key_code8.rs prince_region0_key_code9.rs prince_region1_body0.rs prince_region1_body1.rs prince_region1_body10.rs prince_region1_body11.rs prince_region1_body2.rs prince_region1_body3.rs prince_region1_body4.rs prince_region1_body5.rs prince_region1_body6.rs prince_region1_body7.rs prince_region1_body8.rs prince_region1_body9.rs prince_region1_header0.rs prince_region1_header1.rs prince_region1_key_code0.rs prince_region1_key_code1.rs prince_region1_key_code10.rs prince_region1_key_code11.rs prince_region1_key_code12.rs prince_region1_key_code13.rs prince_region1_key_code2.rs prince_region1_key_code3.rs prince_region1_key_code4.rs prince_region1_key_code5.rs prince_region1_key_code6.rs prince_region1_key_code7.rs prince_region1_key_code8.rs prince_region1_key_code9.rs prince_region2_body0.rs prince_region2_body1.rs prince_region2_body10.rs prince_region2_body11.rs prince_region2_body2.rs prince_region2_body3.rs prince_region2_body4.rs prince_region2_body5.rs prince_region2_body6.rs prince_region2_body7.rs prince_region2_body8.rs prince_region2_body9.rs prince_region2_header0.rs prince_region2_header1.rs prince_region2_key_code0.rs prince_region2_key_code1.rs prince_region2_key_code10.rs prince_region2_key_code11.rs prince_region2_key_code12.rs prince_region2_key_code13.rs prince_region2_key_code2.rs prince_region2_key_code3.rs prince_region2_key_code4.rs prince_region2_key_code5.rs prince_region2_key_code6.rs prince_region2_key_code7.rs prince_region2_key_code8.rs prince_region2_key_code9.rs puf_discharge_time_in_ms.rs sbkey_body0.rs sbkey_body1.rs sbkey_body10.rs sbkey_body11.rs sbkey_body2.rs sbkey_body3.rs sbkey_body4.rs sbkey_body5.rs sbkey_body6.rs sbkey_body7.rs sbkey_body8.rs sbkey_body9.rs sbkey_header0.rs sbkey_header1.rs sbkey_key_code0.rs sbkey_key_code1.rs sbkey_key_code10.rs sbkey_key_code11.rs sbkey_key_code12.rs sbkey_key_code13.rs sbkey_key_code2.rs sbkey_key_code3.rs sbkey_key_code4.rs sbkey_key_code5.rs sbkey_key_code6.rs sbkey_key_code7.rs sbkey_key_code8.rs sbkey_key_code9.rs uds_body0.rs uds_body1.rs uds_body10.rs uds_body11.rs uds_body2.rs uds_body3.rs uds_body4.rs uds_body5.rs uds_body6.rs uds_body7.rs uds_body8.rs uds_body9.rs uds_header0.rs uds_header1.rs uds_key_code0.rs uds_key_code1.rs uds_key_code10.rs uds_key_code11.rs uds_key_code12.rs uds_key_code13.rs uds_key_code2.rs uds_key_code3.rs uds_key_code4.rs uds_key_code5.rs uds_key_code6.rs uds_key_code7.rs uds_key_code8.rs uds_key_code9.rs user_kek_body0.rs user_kek_body1.rs user_kek_body10.rs user_kek_body11.rs user_kek_body2.rs user_kek_body3.rs user_kek_body4.rs user_kek_body5.rs user_kek_body6.rs user_kek_body7.rs user_kek_body8.rs user_kek_body9.rs user_kek_header0.rs user_kek_header1.rs user_kek_key_code0.rs user_kek_key_code1.rs user_kek_key_code10.rs user_kek_key_code11.rs user_kek_key_code12.rs user_kek_key_code13.rs user_kek_key_code2.rs user_kek_key_code3.rs user_kek_key_code4.rs user_kek_key_code5.rs user_kek_key_code6.rs user_kek_key_code7.rs user_kek_key_code8.rs user_kek_key_code9.rs

flexcomm0

pid.rs pselid.rs

gint0

ctrl.rs port_ena.rs port_pol.rs

gpio

b

w

b.rs clr.rs dir.rs dirclr.rs dirnot.rs dirset.rs mask.rs mpin.rs not.rs pin.rs set.rs w.rs

hashcrypt

alias.rs config.rs cryptcfg.rs ctrl.rs digest0.rs indata.rs intenclr.rs intenset.rs lock.rs mask.rs memaddr.rs memctrl.rs status.rs

i2c0

cfg.rs clkdiv.rs id.rs intenclr.rs intenset.rs intstat.rs monrxdat.rs mstctl.rs mstdat.rs msttime.rs slvadr0.rs slvadr1.rs slvadr2.rs slvadr3.rs slvctl.rs slvdat.rs slvqual0.rs stat.rs timeout.rs

i2s0

cfg1.rs cfg2.rs div.rs fifocfg.rs fifointenclr.rs fifointenset.rs fifointstat.rs fiford.rs fiford48h.rs fiford48hnopop.rs fifordnopop.rs fifostat.rs fifotrig.rs fifowr.rs fifowr48h.rs id.rs stat.rs

inputmux

iocon

mailbox

mboxirq

irq.rs irqclr.rs irqset.rs

mboxirq.rs mutex.rs

mrt0

channel

ctrl.rs intval.rs stat.rs timer.rs

channel.rs idle_ch.rs irq_flag.rs modcfg.rs

ostimer

capturen_h.rs capturen_l.rs evtimerh.rs evtimerl.rs matchn_h.rs matchn_l.rs osevent_ctrl.rs

pint

cienf.rs cienr.rs fall.rs ienf.rs ienr.rs isel.rs ist.rs pmcfg.rs pmctrl.rs pmsrc.rs rise.rs sienf.rs sienr.rs

plu

lut

lut.rs lut_truth.rs output_mux.rs outputs.rs wakeint_ctrl.rs

pmc

aoreg1.rs bodvbat.rs comp.rs ostimer.rs pdruncfg0.rs pdruncfgclr0.rs pdruncfgset0.rs resetctrl.rs rtcosc32k.rs statusclk.rs wakeiocause.rs

powerquad

prince

base_addr0.rs base_addr1.rs base_addr2.rs enc_enable.rs iv_lsb0.rs iv_lsb1.rs iv_lsb2.rs iv_msb0.rs iv_msb1.rs iv_msb2.rs lock.rs mask_lsb.rs mask_msb.rs sr_enable0.rs sr_enable1.rs sr_enable2.rs

puf

rng

counter_cfg.rs counter_val.rs moduleid.rs online_test_cfg.rs online_test_val.rs random_number.rs

rtc

count.rs ctrl.rs gpreg.rs match_.rs subsec.rs wake.rs

sau

ctrl.rs rbar.rs rlar.rs rnr.rs sfar.rs sfsr.rs type_.rs

scn_scb

sct0

ev

ev_ctrl.rs ev_state.rs

out

out_clr.rs out_set.rs

sdif

secgpio

spi0

cfg.rs div.rs dly.rs fifocfg.rs fifointenclr.rs fifointenset.rs fifointstat.rs fiford.rs fifordnopop.rs fifostat.rs fifotrig.rs fifowr.rs id.rs intenclr.rs intenset.rs intstat.rs stat.rs

syscon

adcclkdiv.rs adcclksel.rs ahbclkctrl0.rs ahbclkctrl1.rs ahbclkctrl2.rs ahbclkctrlclr.rs ahbclkctrlset.rs ahbclkdiv.rs ahbmatprio.rs autoclkgateoverride.rs clkoutdiv.rs clkoutsel.rs clock_ctrl.rs clockgenupdatelockout.rs comp_int_ctrl.rs comp_int_status.rs cpboot.rs cpstat.rs cpu0nstckcal.rs cpu0stckcal.rs cpu1stckcal.rs cpucfg.rs cpuctrl.rs ctimerclksel0.rs ctimerclksel1.rs ctimerclksel2.rs ctimerclksel3.rs ctimerclksel4.rs ctimerclkselx0.rs ctimerclkselx1.rs ctimerclkselx2.rs ctimerclkselx3.rs ctimerclkselx4.rs debug_auth_beacon.rs debug_features.rs debug_features_dp.rs debug_lock_en.rs device_id0.rs dieid.rs fcclksel0.rs fcclksel1.rs fcclksel2.rs fcclksel3.rs fcclksel4.rs fcclksel5.rs fcclksel6.rs fcclksel7.rs fcclkselx0.rs fcclkselx1.rs fcclkselx2.rs fcclkselx3.rs fcclkselx4.rs fcclkselx5.rs fcclkselx6.rs fcclkselx7.rs flexfrg0ctrl.rs flexfrg1ctrl.rs flexfrg2ctrl.rs flexfrg3ctrl.rs flexfrg4ctrl.rs flexfrg5ctrl.rs flexfrg6ctrl.rs flexfrg7ctrl.rs flexfrgxctrl0.rs flexfrgxctrl1.rs flexfrgxctrl2.rs flexfrgxctrl3.rs flexfrgxctrl4.rs flexfrgxctrl5.rs flexfrgxctrl6.rs flexfrgxctrl7.rs fmccr.rs fmcflush.rs frohfdiv.rs gpiopsync.rs hslspiclksel.rs key_block.rs mainclksela.rs mainclkselb.rs mclkclksel.rs mclkdiv.rs mclkio.rs memoryremap.rs nmisrc.rs pll0clkdiv.rs pll0clksel.rs pll0ctrl.rs pll0ndec.rs pll0pdec.rs pll0sscg0.rs pll0sscg1.rs pll0stat.rs pll1clksel.rs pll1ctrl.rs pll1mdec.rs pll1ndec.rs pll1pdec.rs pll1stat.rs presetctrl0.rs presetctrl1.rs presetctrl2.rs presetctrlclr.rs presetctrlset.rs sctclkdiv.rs sctclksel.rs sdioclkctrl.rs sdioclkdiv.rs sdioclksel.rs swr_reset.rs systickclkdiv0.rs systickclkdiv1.rs systickclksel0.rs systickclksel1.rs systickclkselx0.rs systickclkselx1.rs traceclkdiv.rs traceclksel.rs usb0clkdiv.rs usb0clksel.rs usb0needclkctrl.rs usb0needclkstat.rs usb1needclkctrl.rs usb1needclkstat.rs wdtclkdiv.rs

sysctl

fcctrlsel.rs sharedctrlset.rs updatelckout.rs usb_hs_status.rs

usart0

addr.rs brg.rs cfg.rs ctl.rs fifocfg.rs fifointenclr.rs fifointenset.rs fifointstat.rs fiford.rs fifordnopop.rs fifostat.rs fifotrig.rs fifowr.rs id.rs intenclr.rs intenset.rs intstat.rs osr.rs stat.rs

usb1

databufstart.rs devcmdstat.rs epbufcfg.rs epinuse.rs epliststart.rs epskip.rs eptoggle.rs info.rs inten.rs intsetstat.rs intstat.rs lpm.rs

usbfsh

usbhsh

atlptd.rs atlptdd.rs atlptds.rs caplength_chipid.rs datapayload.rs fladj_frindex.rs hcsparams.rs intptd.rs intptdd.rs intptds.rs isoptd.rs isoptdd.rs isoptds.rs lastptd.rs portmode.rs portsc1.rs usbcmd.rs usbintr.rs usbsts.rs

usbphy

utick0

cap.rs capclr.rs cfg.rs ctrl.rs stat.rs

wwdt

feed.rs mod_.rs tc.rs tv.rs warnint.rs window.rs

nb

r0

stable_deref_trait

typenum

array.rs bit.rs int.rs lib.rs marker_traits.rs operator_aliases.rs private.rs type_operators.rs uint.rs

usb_device

bus.rs class.rs control.rs control_pipe.rs descriptor.rs device.rs device_builder.rs endpoint.rs lib.rs test_class.rs

usbd_serial

buffer.rs cdc_acm.rs lib.rs serial_port.rs

vcell

void

volatile_register

#[allow(unused_imports)]
use cortex_m_semihosting::{dbg, hprint, hprintln};

use core::ops::Deref;

use crate::{
    peripherals::{
        syscon,
    },
    traits,
    typestates::{
        init_state,
    },
};

// Main struct
pub struct Gint<State: init_state::InitState = init_state::Unknown> {
    pub(crate) raw_gint0: raw::GINT0,
    pub(crate) raw_gint1: raw::GINT1,
    _state: State,
}

impl Gint {
    pub fn new(raw_gint0: raw::GINT0, raw_gint1: raw::GINT1) -> Self {
        Gint {
            raw_gint0,
            raw_gint1,
            _state: init_state::Unknown,
        }
    }
}

// do a little macro here

pub struct Gint0<State: init_state::InitState = init_state::Enabled> {
    pub(crate) raw: raw::GINT0,
    _state: State,
}
impl Deref for Gint0 {
    type Target = raw::gint0::RegisterBlock;
    fn deref(&self) -> &Self::Target {
        &self.raw
    }
}
impl traits::Gint for Gint0 {}

pub type EnabledGint0 = Gint0<init_state::Enabled>;

pub struct Gint1<State: init_state::InitState = init_state::Enabled> {
    pub(crate) raw: raw::GINT1,
    _state: State,
}
impl Deref for Gint1 {
    type Target = raw::gint0::RegisterBlock;
    fn deref(&self) -> &Self::Target {
        &self.raw
    }
}
impl traits::Gint for Gint1 {}

pub type EnabledGint1 = Gint1<init_state::Enabled>;

impl<State: init_state::InitState> Gint<State> {
    pub fn release(self) -> (raw::GINT0, raw::GINT1) {
        (self.raw_gint0, self.raw_gint1)
    }

    pub fn enabled(
        mut self,
        syscon: &mut syscon::Syscon,
    ) -> (Gint0, Gint1) {
        syscon.enable_clock(&mut (&mut self.raw_gint0, &mut self.raw_gint1));
        (
            Gint0 {
                raw: self.raw_gint0,
                _state: init_state::Enabled(()),
            },
            Gint1 {
                raw: self.raw_gint1,
                _state: init_state::Enabled(()),
            },
        )
    }
}

// impl (Gint0, Gint1) {
//     pub fn disabled(
//         mut self,
//         syscon: &mut syscon::Syscon,
//     ) -> Gint<init_state::Disabled> {
//         syscon.disable_clock(&mut self);

//         Gint {
//             raw_gint0: self.0.raw,
//             raw_gint1: self.1.raw,
//             _state: init_state::Disabled,
//         }
//     }
// }

impl From<(raw::GINT0, raw::GINT1)> for Gint {
    fn from(raw: (raw::GINT0, raw::GINT1)) -> Self {
        Gint::new(raw.0, raw.1)
    }
}