[−][src]Struct lpc55_pac::syscon::RegisterBlock

#[repr(C)]pub struct RegisterBlock {
    pub memoryremap: MEMORYREMAP,
    pub ahbmatprio: AHBMATPRIO,
    pub cpu0stckcal: CPU0STCKCAL,
    pub cpu0nstckcal: CPU0NSTCKCAL,
    pub cpu1stckcal: CPU1STCKCAL,
    pub nmisrc: NMISRC,
    pub presetctrl0: PRESETCTRL0,
    pub presetctrl1: PRESETCTRL1,
    pub presetctrl2: PRESETCTRL2,
    pub presetctrlset: [PRESETCTRLSET; 3],
    pub presetctrlclr: [PRESETCTRLCLR; 3],
    pub swr_reset: SWR_RESET,
    pub ahbclkctrl0: AHBCLKCTRL0,
    pub ahbclkctrl1: AHBCLKCTRL1,
    pub ahbclkctrl2: AHBCLKCTRL2,
    pub ahbclkctrlset: [AHBCLKCTRLSET; 3],
    pub ahbclkctrlclr: [AHBCLKCTRLCLR; 3],
    pub traceclksel: TRACECLKSEL,
    pub mainclksela: MAINCLKSELA,
    pub mainclkselb: MAINCLKSELB,
    pub clkoutsel: CLKOUTSEL,
    pub pll0clksel: PLL0CLKSEL,
    pub pll1clksel: PLL1CLKSEL,
    pub adcclksel: ADCCLKSEL,
    pub usb0clksel: USB0CLKSEL,
    pub hslspiclksel: HSLSPICLKSEL,
    pub mclkclksel: MCLKCLKSEL,
    pub sctclksel: SCTCLKSEL,
    pub sdioclksel: SDIOCLKSEL,
    pub systickclkdiv0: SYSTICKCLKDIV0,
    pub systickclkdiv1: SYSTICKCLKDIV1,
    pub traceclkdiv: TRACECLKDIV,
    pub ahbclkdiv: AHBCLKDIV,
    pub clkoutdiv: CLKOUTDIV,
    pub frohfdiv: FROHFDIV,
    pub wdtclkdiv: WDTCLKDIV,
    pub adcclkdiv: ADCCLKDIV,
    pub usb0clkdiv: USB0CLKDIV,
    pub mclkdiv: MCLKDIV,
    pub sctclkdiv: SCTCLKDIV,
    pub sdioclkdiv: SDIOCLKDIV,
    pub pll0clkdiv: PLL0CLKDIV,
    pub clockgenupdatelockout: CLOCKGENUPDATELOCKOUT,
    pub fmccr: FMCCR,
    pub usb0needclkctrl: USB0NEEDCLKCTRL,
    pub usb0needclkstat: USB0NEEDCLKSTAT,
    pub fmcflush: FMCFLUSH,
    pub mclkio: MCLKIO,
    pub usb1needclkctrl: USB1NEEDCLKCTRL,
    pub usb1needclkstat: USB1NEEDCLKSTAT,
    pub sdioclkctrl: SDIOCLKCTRL,
    pub pll1ctrl: PLL1CTRL,
    pub pll1stat: PLL1STAT,
    pub pll1ndec: PLL1NDEC,
    pub pll1mdec: PLL1MDEC,
    pub pll1pdec: PLL1PDEC,
    pub pll0ctrl: PLL0CTRL,
    pub pll0stat: PLL0STAT,
    pub pll0ndec: PLL0NDEC,
    pub pll0pdec: PLL0PDEC,
    pub pll0sscg0: PLL0SSCG0,
    pub pll0sscg1: PLL0SSCG1,
    pub cpuctrl: CPUCTRL,
    pub cpboot: CPBOOT,
    pub cpstat: CPSTAT,
    pub clock_ctrl: CLOCK_CTRL,
    pub comp_int_ctrl: COMP_INT_CTRL,
    pub comp_int_status: COMP_INT_STATUS,
    pub autoclkgateoverride: AUTOCLKGATEOVERRIDE,
    pub gpiopsync: GPIOPSYNC,
    pub debug_lock_en: DEBUG_LOCK_EN,
    pub debug_features: DEBUG_FEATURES,
    pub debug_features_dp: DEBUG_FEATURES_DP,
    pub key_block: KEY_BLOCK,
    pub debug_auth_beacon: DEBUG_AUTH_BEACON,
    pub cpucfg: CPUCFG,
    pub device_id0: DEVICE_ID0,
    pub dieid: DIEID,
    // some fields omitted
}

Register block

Fields

memoryremap: MEMORYREMAP

0x00 - Memory Remap control register

ahbmatprio: AHBMATPRIO

0x10 - AHB Matrix priority control register Priority values are 3 = highest, 0 = lowest

cpu0stckcal: CPU0STCKCAL

0x38 - System tick calibration for secure part of CPU0

cpu0nstckcal: CPU0NSTCKCAL

0x3c - System tick calibration for non-secure part of CPU0

cpu1stckcal: CPU1STCKCAL

0x40 - System tick calibration for CPU1

nmisrc: NMISRC

0x48 - NMI Source Select

presetctrl0: PRESETCTRL0

0x100 - Peripheral reset control 0

presetctrl1: PRESETCTRL1

0x104 - Peripheral reset control 1

presetctrl2: PRESETCTRL2

0x108 - Peripheral reset control 2

presetctrlset: [PRESETCTRLSET; 3]

0x120 - Peripheral reset control set register

presetctrlclr: [PRESETCTRLCLR; 3]

0x140 - Peripheral reset control clear register

swr_reset: SWR_RESET

0x160 - generate a software_reset

ahbclkctrl0: AHBCLKCTRL0

0x200 - AHB Clock control 0

ahbclkctrl1: AHBCLKCTRL1

0x204 - AHB Clock control 1

ahbclkctrl2: AHBCLKCTRL2

0x208 - AHB Clock control 2

ahbclkctrlset: [AHBCLKCTRLSET; 3]

0x220 - Peripheral reset control register

ahbclkctrlclr: [AHBCLKCTRLCLR; 3]

0x240 - Peripheral reset control register

traceclksel: TRACECLKSEL

0x268 - Trace clock source select

mainclksela: MAINCLKSELA

0x280 - Main clock A source select

mainclkselb: MAINCLKSELB

0x284 - Main clock source select

clkoutsel: CLKOUTSEL

0x288 - CLKOUT clock source select

pll0clksel: PLL0CLKSEL

0x290 - PLL0 clock source select

pll1clksel: PLL1CLKSEL

0x294 - PLL1 clock source select

adcclksel: ADCCLKSEL

0x2a4 - ADC clock source select

usb0clksel: USB0CLKSEL

0x2a8 - FS USB clock source select

hslspiclksel: HSLSPICLKSEL

0x2d0 - HS LSPI clock source select

mclkclksel: MCLKCLKSEL

0x2e0 - MCLK clock source select

sctclksel: SCTCLKSEL

0x2f0 - SCTimer/PWM clock source select

sdioclksel: SDIOCLKSEL

0x2f8 - SDIO clock source select

systickclkdiv0: SYSTICKCLKDIV0

0x300 - System Tick Timer divider for CPU0

systickclkdiv1: SYSTICKCLKDIV1

0x304 - System Tick Timer divider for CPU1

traceclkdiv: TRACECLKDIV

0x308 - TRACE clock divider

ahbclkdiv: AHBCLKDIV

0x380 - System clock divider

clkoutdiv: CLKOUTDIV

0x384 - CLKOUT clock divider

frohfdiv: FROHFDIV

0x388 - FRO_HF (96MHz) clock divider

wdtclkdiv: WDTCLKDIV

0x38c - WDT clock divider

adcclkdiv: ADCCLKDIV

0x394 - ADC clock divider

usb0clkdiv: USB0CLKDIV

0x398 - USB0 Clock divider

mclkdiv: MCLKDIV

0x3ac - I2S MCLK clock divider

sctclkdiv: SCTCLKDIV

0x3b4 - SCT/PWM clock divider

sdioclkdiv: SDIOCLKDIV

0x3bc - SDIO clock divider

pll0clkdiv: PLL0CLKDIV

0x3c4 - PLL0 clock divider

clockgenupdatelockout: CLOCKGENUPDATELOCKOUT

0x3fc - Control clock configuration registers access (like xxxDIV, xxxSEL)

fmccr: FMCCR

0x400 - FMC configuration register

usb0needclkctrl: USB0NEEDCLKCTRL

0x40c - USB0 need clock control

usb0needclkstat: USB0NEEDCLKSTAT

0x410 - USB0 need clock status

fmcflush: FMCFLUSH

0x41c - FMCflush control

mclkio: MCLKIO

0x420 - MCLK control

usb1needclkctrl: USB1NEEDCLKCTRL

0x424 - USB1 need clock control

usb1needclkstat: USB1NEEDCLKSTAT

0x428 - USB1 need clock status

sdioclkctrl: SDIOCLKCTRL

0x460 - SDIO CCLKIN phase and delay control

pll1ctrl: PLL1CTRL

0x560 - PLL1 550m control

pll1stat: PLL1STAT

0x564 - PLL1 550m status

pll1ndec: PLL1NDEC

0x568 - PLL1 550m N divider

pll1mdec: PLL1MDEC

0x56c - PLL1 550m M divider

pll1pdec: PLL1PDEC

0x570 - PLL1 550m P divider

pll0ctrl: PLL0CTRL

0x580 - PLL0 550m control

pll0stat: PLL0STAT

0x584 - PLL0 550m status

pll0ndec: PLL0NDEC

0x588 - PLL0 550m N divider

pll0pdec: PLL0PDEC

0x58c - PLL0 550m P divider

pll0sscg0: PLL0SSCG0

0x590 - PLL0 Spread Spectrum Wrapper control register 0

pll0sscg1: PLL0SSCG1

0x594 - PLL0 Spread Spectrum Wrapper control register 1

cpuctrl: CPUCTRL

0x800 - CPU Control for multiple processors

cpboot: CPBOOT

0x804 - Coprocessor Boot Address

cpstat: CPSTAT

0x80c - CPU Status

clock_ctrl: CLOCK_CTRL

0xa18 - Various system clock controls : Flash clock (48 MHz) control, clocks to Frequency Measures

comp_int_ctrl: COMP_INT_CTRL

0xb10 - Comparator Interrupt control

comp_int_status: COMP_INT_STATUS

0xb14 - Comparator Interrupt status

autoclkgateoverride: AUTOCLKGATEOVERRIDE

0xe04 - Control automatic clock gating

gpiopsync: GPIOPSYNC

0xe08 - Enable bypass of the first stage of synchonization inside GPIO_INT module

debug_lock_en: DEBUG_LOCK_EN

0xfa0 - Control write access to security registers.

debug_features: DEBUG_FEATURES

0xfa4 - Cortex M33 (CPU0) and micro Cortex M33 (CPU1) debug features control.

debug_features_dp: DEBUG_FEATURES_DP

0xfa8 - Cortex M33 (CPU0) and micro Cortex M33 (CPU1) debug features control DUPLICATE register.

key_block: KEY_BLOCK

0xfbc - block quiddikey/PUF all index.

debug_auth_beacon: DEBUG_AUTH_BEACON

0xfc0 - Debug authentication BEACON register

cpucfg: CPUCFG

0xfd4 - CPUs configuration register

device_id0: DEVICE_ID0

0xff8 - Device ID

dieid: DIEID

0xffc - Chip revision ID and Number

Implementations

`impl RegisterBlock`[src]

`pub fn systickclkselx0(&self) -> &SYSTICKCLKSELX0`[src]

0x260 - Peripheral reset control register

`pub fn systickclkselx0_mut(&self) -> &mut SYSTICKCLKSELX0`[src]

0x260 - Peripheral reset control register

`pub fn systickclksel0(&self) -> &SYSTICKCLKSEL0`[src]

0x260 - System Tick Timer for CPU0 source select

`pub fn systickclksel0_mut(&self) -> &mut SYSTICKCLKSEL0`[src]

0x260 - System Tick Timer for CPU0 source select

`pub fn systickclkselx1(&self) -> &SYSTICKCLKSELX1`[src]

0x264 - Peripheral reset control register

`pub fn systickclkselx1_mut(&self) -> &mut SYSTICKCLKSELX1`[src]

0x264 - Peripheral reset control register

`pub fn systickclksel1(&self) -> &SYSTICKCLKSEL1`[src]

0x264 - System Tick Timer for CPU1 source select

`pub fn systickclksel1_mut(&self) -> &mut SYSTICKCLKSEL1`[src]

0x264 - System Tick Timer for CPU1 source select

`pub fn ctimerclkselx0(&self) -> &CTIMERCLKSELX0`[src]

0x26c - Peripheral reset control register

`pub fn ctimerclkselx0_mut(&self) -> &mut CTIMERCLKSELX0`[src]

0x26c - Peripheral reset control register

`pub fn ctimerclksel0(&self) -> &CTIMERCLKSEL0`[src]

0x26c - CTimer 0 clock source select

`pub fn ctimerclksel0_mut(&self) -> &mut CTIMERCLKSEL0`[src]

0x26c - CTimer 0 clock source select

`pub fn ctimerclkselx1(&self) -> &CTIMERCLKSELX1`[src]

0x270 - Peripheral reset control register

`pub fn ctimerclkselx1_mut(&self) -> &mut CTIMERCLKSELX1`[src]

0x270 - Peripheral reset control register

`pub fn ctimerclksel1(&self) -> &CTIMERCLKSEL1`[src]

0x270 - CTimer 1 clock source select

`pub fn ctimerclksel1_mut(&self) -> &mut CTIMERCLKSEL1`[src]

0x270 - CTimer 1 clock source select

`pub fn ctimerclkselx2(&self) -> &CTIMERCLKSELX2`[src]

0x274 - Peripheral reset control register

`pub fn ctimerclkselx2_mut(&self) -> &mut CTIMERCLKSELX2`[src]

0x274 - Peripheral reset control register

`pub fn ctimerclksel2(&self) -> &CTIMERCLKSEL2`[src]

0x274 - CTimer 2 clock source select

`pub fn ctimerclksel2_mut(&self) -> &mut CTIMERCLKSEL2`[src]

0x274 - CTimer 2 clock source select

`pub fn ctimerclkselx3(&self) -> &CTIMERCLKSELX3`[src]

0x278 - Peripheral reset control register

`pub fn ctimerclkselx3_mut(&self) -> &mut CTIMERCLKSELX3`[src]

0x278 - Peripheral reset control register

`pub fn ctimerclksel3(&self) -> &CTIMERCLKSEL3`[src]

0x278 - CTimer 3 clock source select

`pub fn ctimerclksel3_mut(&self) -> &mut CTIMERCLKSEL3`[src]

0x278 - CTimer 3 clock source select

`pub fn ctimerclkselx4(&self) -> &CTIMERCLKSELX4`[src]

0x27c - Peripheral reset control register

`pub fn ctimerclkselx4_mut(&self) -> &mut CTIMERCLKSELX4`[src]

0x27c - Peripheral reset control register

`pub fn ctimerclksel4(&self) -> &CTIMERCLKSEL4`[src]

0x27c - CTimer 4 clock source select

`pub fn ctimerclksel4_mut(&self) -> &mut CTIMERCLKSEL4`[src]

0x27c - CTimer 4 clock source select

`pub fn fcclkselx0(&self) -> &FCCLKSELX0`[src]

0x2b0 - Peripheral reset control register

`pub fn fcclkselx0_mut(&self) -> &mut FCCLKSELX0`[src]

0x2b0 - Peripheral reset control register

`pub fn fcclksel0(&self) -> &FCCLKSEL0`[src]

0x2b0 - Flexcomm Interface 0 clock source select for Fractional Rate Divider

`pub fn fcclksel0_mut(&self) -> &mut FCCLKSEL0`[src]

0x2b0 - Flexcomm Interface 0 clock source select for Fractional Rate Divider

`pub fn fcclkselx1(&self) -> &FCCLKSELX1`[src]

0x2b4 - Peripheral reset control register

`pub fn fcclkselx1_mut(&self) -> &mut FCCLKSELX1`[src]

0x2b4 - Peripheral reset control register

`pub fn fcclksel1(&self) -> &FCCLKSEL1`[src]

0x2b4 - Flexcomm Interface 1 clock source select for Fractional Rate Divider

`pub fn fcclksel1_mut(&self) -> &mut FCCLKSEL1`[src]

0x2b4 - Flexcomm Interface 1 clock source select for Fractional Rate Divider

`pub fn fcclkselx2(&self) -> &FCCLKSELX2`[src]

0x2b8 - Peripheral reset control register

`pub fn fcclkselx2_mut(&self) -> &mut FCCLKSELX2`[src]

0x2b8 - Peripheral reset control register

`pub fn fcclksel2(&self) -> &FCCLKSEL2`[src]

0x2b8 - Flexcomm Interface 2 clock source select for Fractional Rate Divider

`pub fn fcclksel2_mut(&self) -> &mut FCCLKSEL2`[src]

0x2b8 - Flexcomm Interface 2 clock source select for Fractional Rate Divider

`pub fn fcclkselx3(&self) -> &FCCLKSELX3`[src]

0x2bc - Peripheral reset control register

`pub fn fcclkselx3_mut(&self) -> &mut FCCLKSELX3`[src]

0x2bc - Peripheral reset control register

`pub fn fcclksel3(&self) -> &FCCLKSEL3`[src]

0x2bc - Flexcomm Interface 3 clock source select for Fractional Rate Divider

`pub fn fcclksel3_mut(&self) -> &mut FCCLKSEL3`[src]

0x2bc - Flexcomm Interface 3 clock source select for Fractional Rate Divider

`pub fn fcclkselx4(&self) -> &FCCLKSELX4`[src]

0x2c0 - Peripheral reset control register

`pub fn fcclkselx4_mut(&self) -> &mut FCCLKSELX4`[src]

0x2c0 - Peripheral reset control register

`pub fn fcclksel4(&self) -> &FCCLKSEL4`[src]

0x2c0 - Flexcomm Interface 4 clock source select for Fractional Rate Divider

`pub fn fcclksel4_mut(&self) -> &mut FCCLKSEL4`[src]

0x2c0 - Flexcomm Interface 4 clock source select for Fractional Rate Divider

`pub fn fcclkselx5(&self) -> &FCCLKSELX5`[src]

0x2c4 - Peripheral reset control register

`pub fn fcclkselx5_mut(&self) -> &mut FCCLKSELX5`[src]

0x2c4 - Peripheral reset control register

`pub fn fcclksel5(&self) -> &FCCLKSEL5`[src]

0x2c4 - Flexcomm Interface 5 clock source select for Fractional Rate Divider

`pub fn fcclksel5_mut(&self) -> &mut FCCLKSEL5`[src]

0x2c4 - Flexcomm Interface 5 clock source select for Fractional Rate Divider

`pub fn fcclkselx6(&self) -> &FCCLKSELX6`[src]

0x2c8 - Peripheral reset control register

`pub fn fcclkselx6_mut(&self) -> &mut FCCLKSELX6`[src]

0x2c8 - Peripheral reset control register

`pub fn fcclksel6(&self) -> &FCCLKSEL6`[src]

0x2c8 - Flexcomm Interface 6 clock source select for Fractional Rate Divider

`pub fn fcclksel6_mut(&self) -> &mut FCCLKSEL6`[src]

0x2c8 - Flexcomm Interface 6 clock source select for Fractional Rate Divider

`pub fn fcclkselx7(&self) -> &FCCLKSELX7`[src]

0x2cc - Peripheral reset control register

`pub fn fcclkselx7_mut(&self) -> &mut FCCLKSELX7`[src]

0x2cc - Peripheral reset control register

`pub fn fcclksel7(&self) -> &FCCLKSEL7`[src]

0x2cc - Flexcomm Interface 7 clock source select for Fractional Rate Divider

`pub fn fcclksel7_mut(&self) -> &mut FCCLKSEL7`[src]

0x2cc - Flexcomm Interface 7 clock source select for Fractional Rate Divider

`pub fn flexfrgxctrl0(&self) -> &FLEXFRGXCTRL0`[src]

0x320 - Peripheral reset control register

`pub fn flexfrgxctrl0_mut(&self) -> &mut FLEXFRGXCTRL0`[src]

0x320 - Peripheral reset control register

`pub fn flexfrg0ctrl(&self) -> &FLEXFRG0CTRL`[src]

0x320 - Fractional rate divider for flexcomm 0

`pub fn flexfrg0ctrl_mut(&self) -> &mut FLEXFRG0CTRL`[src]

0x320 - Fractional rate divider for flexcomm 0

`pub fn flexfrgxctrl1(&self) -> &FLEXFRGXCTRL1`[src]

0x324 - Peripheral reset control register

`pub fn flexfrgxctrl1_mut(&self) -> &mut FLEXFRGXCTRL1`[src]

0x324 - Peripheral reset control register

`pub fn flexfrg1ctrl(&self) -> &FLEXFRG1CTRL`[src]

0x324 - Fractional rate divider for flexcomm 1

`pub fn flexfrg1ctrl_mut(&self) -> &mut FLEXFRG1CTRL`[src]

0x324 - Fractional rate divider for flexcomm 1

`pub fn flexfrgxctrl2(&self) -> &FLEXFRGXCTRL2`[src]

0x328 - Peripheral reset control register

`pub fn flexfrgxctrl2_mut(&self) -> &mut FLEXFRGXCTRL2`[src]

0x328 - Peripheral reset control register

`pub fn flexfrg2ctrl(&self) -> &FLEXFRG2CTRL`[src]

0x328 - Fractional rate divider for flexcomm 2

`pub fn flexfrg2ctrl_mut(&self) -> &mut FLEXFRG2CTRL`[src]

0x328 - Fractional rate divider for flexcomm 2

`pub fn flexfrgxctrl3(&self) -> &FLEXFRGXCTRL3`[src]

0x32c - Peripheral reset control register

`pub fn flexfrgxctrl3_mut(&self) -> &mut FLEXFRGXCTRL3`[src]

0x32c - Peripheral reset control register

`pub fn flexfrg3ctrl(&self) -> &FLEXFRG3CTRL`[src]

0x32c - Fractional rate divider for flexcomm 3

`pub fn flexfrg3ctrl_mut(&self) -> &mut FLEXFRG3CTRL`[src]

0x32c - Fractional rate divider for flexcomm 3

`pub fn flexfrgxctrl4(&self) -> &FLEXFRGXCTRL4`[src]

0x330 - Peripheral reset control register

`pub fn flexfrgxctrl4_mut(&self) -> &mut FLEXFRGXCTRL4`[src]

0x330 - Peripheral reset control register

`pub fn flexfrg4ctrl(&self) -> &FLEXFRG4CTRL`[src]

0x330 - Fractional rate divider for flexcomm 4

`pub fn flexfrg4ctrl_mut(&self) -> &mut FLEXFRG4CTRL`[src]

0x330 - Fractional rate divider for flexcomm 4

`pub fn flexfrgxctrl5(&self) -> &FLEXFRGXCTRL5`[src]

0x334 - Peripheral reset control register

`pub fn flexfrgxctrl5_mut(&self) -> &mut FLEXFRGXCTRL5`[src]

0x334 - Peripheral reset control register

`pub fn flexfrg5ctrl(&self) -> &FLEXFRG5CTRL`[src]

0x334 - Fractional rate divider for flexcomm 5

`pub fn flexfrg5ctrl_mut(&self) -> &mut FLEXFRG5CTRL`[src]

0x334 - Fractional rate divider for flexcomm 5

`pub fn flexfrgxctrl6(&self) -> &FLEXFRGXCTRL6`[src]

0x338 - Peripheral reset control register

`pub fn flexfrgxctrl6_mut(&self) -> &mut FLEXFRGXCTRL6`[src]

0x338 - Peripheral reset control register

`pub fn flexfrg6ctrl(&self) -> &FLEXFRG6CTRL`[src]

0x338 - Fractional rate divider for flexcomm 6

`pub fn flexfrg6ctrl_mut(&self) -> &mut FLEXFRG6CTRL`[src]

0x338 - Fractional rate divider for flexcomm 6

`pub fn flexfrgxctrl7(&self) -> &FLEXFRGXCTRL7`[src]

0x33c - Peripheral reset control register

`pub fn flexfrgxctrl7_mut(&self) -> &mut FLEXFRGXCTRL7`[src]

0x33c - Peripheral reset control register

`pub fn flexfrg7ctrl(&self) -> &FLEXFRG7CTRL`[src]

0x33c - Fractional rate divider for flexcomm 7

`pub fn flexfrg7ctrl_mut(&self) -> &mut FLEXFRG7CTRL`[src]

0x33c - Fractional rate divider for flexcomm 7

Auto Trait Implementations

`impl Send for RegisterBlock`

`impl !Sync for RegisterBlock`

`impl Unpin for RegisterBlock`

Blanket Implementations

`impl<T> Any for T where T: 'static + ?Sized,` [src]

`fn type_id(&self) -> TypeId`[src]

`impl<T> Borrow<T> for T where T: ?Sized,` [src]

`fn borrow(&self) -> &T`[src]

`impl<T> BorrowMut<T> for T where T: ?Sized,` [src]

`fn borrow_mut(&mut self) -> &mut T`[src]

`impl<T> From<T> for T`[src]

`fn from(t: T) -> T`[src]

`impl<T, U> Into for T where U: From<T>,` [src]

`fn into(self) -> U`[src]

`impl<T> Same<T> for T`[src]

`type Output = T`

Should always be Self

`impl<T, U> TryFrom for T where U: Into<T>,` [src]

`type Error = Infallible`

The type returned in the event of a conversion error.

`fn try_from(value: U) -> Result<T, <T as TryFrom>::Error>`[src]

`impl<T, U> TryInto for T where U: TryFrom<T>,` [src]

`type Error = >::Error`

The type returned in the event of a conversion error.

[−][src]Struct lpc55_pac::syscon::RegisterBlock

Fields

Implementations

impl RegisterBlock[src]

pub fn systickclkselx0(&self) -> &SYSTICKCLKSELX0[src]

pub fn systickclkselx0_mut(&self) -> &mut SYSTICKCLKSELX0[src]

pub fn systickclksel0(&self) -> &SYSTICKCLKSEL0[src]

pub fn systickclksel0_mut(&self) -> &mut SYSTICKCLKSEL0[src]

pub fn systickclkselx1(&self) -> &SYSTICKCLKSELX1[src]

pub fn systickclkselx1_mut(&self) -> &mut SYSTICKCLKSELX1[src]

pub fn systickclksel1(&self) -> &SYSTICKCLKSEL1[src]

pub fn systickclksel1_mut(&self) -> &mut SYSTICKCLKSEL1[src]

pub fn ctimerclkselx0(&self) -> &CTIMERCLKSELX0[src]

pub fn ctimerclkselx0_mut(&self) -> &mut CTIMERCLKSELX0[src]

pub fn ctimerclksel0(&self) -> &CTIMERCLKSEL0[src]

pub fn ctimerclksel0_mut(&self) -> &mut CTIMERCLKSEL0[src]

pub fn ctimerclkselx1(&self) -> &CTIMERCLKSELX1[src]

pub fn ctimerclkselx1_mut(&self) -> &mut CTIMERCLKSELX1[src]

pub fn ctimerclksel1(&self) -> &CTIMERCLKSEL1[src]

pub fn ctimerclksel1_mut(&self) -> &mut CTIMERCLKSEL1[src]

pub fn ctimerclkselx2(&self) -> &CTIMERCLKSELX2[src]

pub fn ctimerclkselx2_mut(&self) -> &mut CTIMERCLKSELX2[src]

pub fn ctimerclksel2(&self) -> &CTIMERCLKSEL2[src]

pub fn ctimerclksel2_mut(&self) -> &mut CTIMERCLKSEL2[src]

pub fn ctimerclkselx3(&self) -> &CTIMERCLKSELX3[src]

pub fn ctimerclkselx3_mut(&self) -> &mut CTIMERCLKSELX3[src]

pub fn ctimerclksel3(&self) -> &CTIMERCLKSEL3[src]

pub fn ctimerclksel3_mut(&self) -> &mut CTIMERCLKSEL3[src]

pub fn ctimerclkselx4(&self) -> &CTIMERCLKSELX4[src]

pub fn ctimerclkselx4_mut(&self) -> &mut CTIMERCLKSELX4[src]

pub fn ctimerclksel4(&self) -> &CTIMERCLKSEL4[src]

pub fn ctimerclksel4_mut(&self) -> &mut CTIMERCLKSEL4[src]

pub fn fcclkselx0(&self) -> &FCCLKSELX0[src]

pub fn fcclkselx0_mut(&self) -> &mut FCCLKSELX0[src]

pub fn fcclksel0(&self) -> &FCCLKSEL0[src]

pub fn fcclksel0_mut(&self) -> &mut FCCLKSEL0[src]

pub fn fcclkselx1(&self) -> &FCCLKSELX1[src]

pub fn fcclkselx1_mut(&self) -> &mut FCCLKSELX1[src]

pub fn fcclksel1(&self) -> &FCCLKSEL1[src]

pub fn fcclksel1_mut(&self) -> &mut FCCLKSEL1[src]

pub fn fcclkselx2(&self) -> &FCCLKSELX2[src]

pub fn fcclkselx2_mut(&self) -> &mut FCCLKSELX2[src]

pub fn fcclksel2(&self) -> &FCCLKSEL2[src]

pub fn fcclksel2_mut(&self) -> &mut FCCLKSEL2[src]

pub fn fcclkselx3(&self) -> &FCCLKSELX3[src]

pub fn fcclkselx3_mut(&self) -> &mut FCCLKSELX3[src]

pub fn fcclksel3(&self) -> &FCCLKSEL3[src]

pub fn fcclksel3_mut(&self) -> &mut FCCLKSEL3[src]

pub fn fcclkselx4(&self) -> &FCCLKSELX4[src]

pub fn fcclkselx4_mut(&self) -> &mut FCCLKSELX4[src]

pub fn fcclksel4(&self) -> &FCCLKSEL4[src]

pub fn fcclksel4_mut(&self) -> &mut FCCLKSEL4[src]

pub fn fcclkselx5(&self) -> &FCCLKSELX5[src]

pub fn fcclkselx5_mut(&self) -> &mut FCCLKSELX5[src]

pub fn fcclksel5(&self) -> &FCCLKSEL5[src]

pub fn fcclksel5_mut(&self) -> &mut FCCLKSEL5[src]

pub fn fcclkselx6(&self) -> &FCCLKSELX6[src]

pub fn fcclkselx6_mut(&self) -> &mut FCCLKSELX6[src]

pub fn fcclksel6(&self) -> &FCCLKSEL6[src]

pub fn fcclksel6_mut(&self) -> &mut FCCLKSEL6[src]

pub fn fcclkselx7(&self) -> &FCCLKSELX7[src]

pub fn fcclkselx7_mut(&self) -> &mut FCCLKSELX7[src]

pub fn fcclksel7(&self) -> &FCCLKSEL7[src]

pub fn fcclksel7_mut(&self) -> &mut FCCLKSEL7[src]

pub fn flexfrgxctrl0(&self) -> &FLEXFRGXCTRL0[src]

pub fn flexfrgxctrl0_mut(&self) -> &mut FLEXFRGXCTRL0[src]

pub fn flexfrg0ctrl(&self) -> &FLEXFRG0CTRL[src]

pub fn flexfrg0ctrl_mut(&self) -> &mut FLEXFRG0CTRL[src]

pub fn flexfrgxctrl1(&self) -> &FLEXFRGXCTRL1[src]

pub fn flexfrgxctrl1_mut(&self) -> &mut FLEXFRGXCTRL1[src]

pub fn flexfrg1ctrl(&self) -> &FLEXFRG1CTRL[src]

pub fn flexfrg1ctrl_mut(&self) -> &mut FLEXFRG1CTRL[src]

pub fn flexfrgxctrl2(&self) -> &FLEXFRGXCTRL2[src]

pub fn flexfrgxctrl2_mut(&self) -> &mut FLEXFRGXCTRL2[src]

pub fn flexfrg2ctrl(&self) -> &FLEXFRG2CTRL[src]

pub fn flexfrg2ctrl_mut(&self) -> &mut FLEXFRG2CTRL[src]

pub fn flexfrgxctrl3(&self) -> &FLEXFRGXCTRL3[src]

pub fn flexfrgxctrl3_mut(&self) -> &mut FLEXFRGXCTRL3[src]

pub fn flexfrg3ctrl(&self) -> &FLEXFRG3CTRL[src]

pub fn flexfrg3ctrl_mut(&self) -> &mut FLEXFRG3CTRL[src]