[−][src]Type Definition lpc55_pac::syscon::SYSTICKCLKDIV1
type SYSTICKCLKDIV1 = Reg<u32, _SYSTICKCLKDIV1>;
System Tick Timer divider for CPU1
This register you can read, reset, write, write_with_zero, modify. See API.
For information about available fields see systickclkdiv1 module
Trait Implementations
impl Readable for SYSTICKCLKDIV1[src]
read() method returns systickclkdiv1::R reader structure
impl ResetValue for SYSTICKCLKDIV1[src]
Register SYSTICKCLKDIV1 reset()'s with value 0x4000_0000
impl Writable for SYSTICKCLKDIV1[src]
write(|w| ..) method takes systickclkdiv1::W writer structure