[−][src]Type Definition lpc55_pac::syscon::FCCLKSEL7
type FCCLKSEL7 = Reg<u32, _FCCLKSEL7>;
Flexcomm Interface 7 clock source select for Fractional Rate Divider
This register you can read, reset, write, write_with_zero, modify. See API.
For information about available fields see fcclksel7 module
Trait Implementations
impl Readable for FCCLKSEL7[src]
read() method returns fcclksel7::R reader structure
impl ResetValue for FCCLKSEL7[src][+]
type Type = u32
fn reset_value() -> Self::Type[src][−]
impl Writable for FCCLKSEL7[src]
write(|w| ..) method takes fcclksel7::W writer structure