[−][src]Struct lpc55_pac::generic::W

pub struct W<U, REG> { /* fields omitted */ }

Register writer

Used as an argument to the closures in the write and modify methods of the register

Implementations

`impl W<u32, Reg<u32, _ROTKH_REVOKE>>`[src]

`pub fn ro_tk0_en(&mut self) -> ROTK0_EN_W<'_>`[src]

Bits 0:1 - RoT Key 0 enable. 00 - Invalid 01 - Enabled 10, 11 - Key revoked

`pub fn ro_tk1_en(&mut self) -> ROTK1_EN_W<'_>`[src]

Bits 2:3 - RoT Key 1 enable. 00 - Invalid 01 - Enabled 10, 11 - Key revoked

`pub fn ro_tk2_en(&mut self) -> ROTK2_EN_W<'_>`[src]

Bits 4:5 - RoT Key 2 enable. 00 - Invalid 01 - Enabled 10, 11 - Key revoked

`impl W<u32, Reg<u32, _VENDOR_USAGE>>`[src]

`pub fn dbg_vendor_usage(&mut self) -> DBG_VENDOR_USAGE_W<'_>`[src]

Bits 0:15 - DBG_VENDOR_USAGE.

`pub fn inverse_value(&mut self) -> INVERSE_VALUE_W<'_>`[src]

Bits 16:31 - inverse value of bits [15:0]

`impl W<u32, Reg<u32, _DCFG_CC_SOCU_PIN>>`[src]

`pub fn niden(&mut self) -> NIDEN_W<'_>`[src]

Bit 0 - Non Secure non-invasive debug enable

`pub fn dbgen(&mut self) -> DBGEN_W<'_>`[src]

Bit 1 - Non Secure debug enable

`pub fn spniden(&mut self) -> SPNIDEN_W<'_>`[src]

Bit 2 - Secure non-invasive debug enable

`pub fn spiden(&mut self) -> SPIDEN_W<'_>`[src]

Bit 3 - Secure invasive debug enable

`pub fn tapen(&mut self) -> TAPEN_W<'_>`[src]

Bit 4 - JTAG TAP enable

`pub fn cpu1_dbgen(&mut self) -> CPU1_DBGEN_W<'_>`[src]

Bit 5 - CPU1 (Micro cortex M33) invasive debug enable

`pub fn isp_cmd_en(&mut self) -> ISP_CMD_EN_W<'_>`[src]

Bit 6 - ISP Boot Command enable

`pub fn fa_cmd_en(&mut self) -> FA_CMD_EN_W<'_>`[src]

Bit 7 - FA Command enable

`pub fn me_cmd_en(&mut self) -> ME_CMD_EN_W<'_>`[src]

Bit 8 - Flash Mass Erase Command enable

`pub fn cpu1_niden(&mut self) -> CPU1_NIDEN_W<'_>`[src]

Bit 9 - CPU1 (Micro cortex M33) non-invasive debug enable

`pub fn uuid_check(&mut self) -> UUID_CHECK_W<'_>`[src]

Bit 15 - Enforce UUID match during Debug authentication.

`pub fn inverse_value(&mut self) -> INVERSE_VALUE_W<'_>`[src]

Bits 16:31 - inverse value of bits [15:0]

`impl W<u32, Reg<u32, _DCFG_CC_SOCU_DFLT>>`[src]

`pub fn niden(&mut self) -> NIDEN_W<'_>`[src]

Bit 0 - Non Secure non-invasive debug fixed state

`pub fn dbgen(&mut self) -> DBGEN_W<'_>`[src]

Bit 1 - Non Secure debug fixed state

`pub fn spniden(&mut self) -> SPNIDEN_W<'_>`[src]

Bit 2 - Secure non-invasive debug fixed state

`pub fn spiden(&mut self) -> SPIDEN_W<'_>`[src]

Bit 3 - Secure invasive debug fixed state

`pub fn tapen(&mut self) -> TAPEN_W<'_>`[src]

Bit 4 - JTAG TAP fixed state

`pub fn cpu1_dbgen(&mut self) -> CPU1_DBGEN_W<'_>`[src]

Bit 5 - CPU1 (Micro cortex M33) invasive debug fixed state

`pub fn isp_cmd_en(&mut self) -> ISP_CMD_EN_W<'_>`[src]

Bit 6 - ISP Boot Command fixed state

`pub fn fa_cmd_en(&mut self) -> FA_CMD_EN_W<'_>`[src]

Bit 7 - FA Command fixed state

`pub fn me_cmd_en(&mut self) -> ME_CMD_EN_W<'_>`[src]

Bit 8 - Flash Mass Erase Command fixed state

`pub fn cpu1_niden(&mut self) -> CPU1_NIDEN_W<'_>`[src]

Bit 9 - CPU1 (Micro cortex M33) non-invasive debug fixed state

`pub fn inverse_value(&mut self) -> INVERSE_VALUE_W<'_>`[src]

Bits 16:31 - inverse value of bits [15:0]

`impl W<u32, Reg<u32, _ENABLE_FA_MODE>>`[src]

`impl W<u32, Reg<u32, _PRINCE_REGION1_IV_HEADER1>>`[src]

`pub fn type_(&mut self) -> TYPE_W<'_>`[src]

Bits 0:1 - .

`pub fn index(&mut self) -> INDEX_W<'_>`[src]

`impl W<u32, Reg<u32, _PRINCE_REGION2_IV_HEADER1>>`[src]

`pub fn type_(&mut self) -> TYPE_W<'_>`[src]

Bits 0:1 - .

`pub fn index(&mut self) -> INDEX_W<'_>`[src]

`pub fn boot_speed(&mut self) -> BOOT_SPEED_W<'_>`[src]

Bits 7:8 - Core clock:

`pub fn boot_failure_pin(&mut self) -> BOOT_FAILURE_PIN_W<'_>`[src]

Bits 24:31 - GPIO port and pin number to use for indicating failure reason. The toggle rate of the pin is used to decode the error type. [2:0]

Defines GPIO port [7:3]
Defines GPIO pin

`impl W<u32, Reg<u32, _SPI_FLASH_CFG>>`[src]

`pub fn spi_recovery_boot_en(&mut self) -> SPI_RECOVERY_BOOT_EN_W<'_>`[src]

Bits 0:4 - SPI flash recovery boot is enabled, if non-zero value is written to this field.

`impl W<u32, Reg<u32, _USB_ID>>`[src]

`pub fn usb_vendor_id(&mut self) -> USB_VENDOR_ID_W<'_>`[src]

Bits 0:15 - .

`pub fn usb_product_id(&mut self) -> USB_PRODUCT_ID_W<'_>`[src]

Bits 16:31 - .

`impl W<u32, Reg<u32, _SDIO_CFG>>`[src]

`pub fn field(&mut self) -> FIELD_W<'_>`[src]

Bits 0:31 - .

`impl W<u32, Reg<u32, _CC_SOCU_PIN>>`[src]

`pub fn niden(&mut self) -> NIDEN_W<'_>`[src]

Bit 0 - Non Secure non-invasive debug enable

`pub fn dbgen(&mut self) -> DBGEN_W<'_>`[src]

Bit 1 - Non Secure debug enable

`pub fn spniden(&mut self) -> SPNIDEN_W<'_>`[src]

Bit 2 - Secure non-invasive debug enable

`pub fn spiden(&mut self) -> SPIDEN_W<'_>`[src]

Bit 3 - Secure invasive debug enable

`pub fn tapen(&mut self) -> TAPEN_W<'_>`[src]

Bit 4 - JTAG TAP enable

`pub fn cpu1_dbgen(&mut self) -> CPU1_DBGEN_W<'_>`[src]

Bit 5 - CPU1 (Micro cortex M33) invasive debug enable

`pub fn isp_cmd_en(&mut self) -> ISP_CMD_EN_W<'_>`[src]

Bit 6 - ISP Boot Command enable

`pub fn fa_cmd_en(&mut self) -> FA_CMD_EN_W<'_>`[src]

Bit 7 - FA Command enable

`pub fn me_cmd_en(&mut self) -> ME_CMD_EN_W<'_>`[src]

Bit 8 - Flash Mass Erase Command enable

`pub fn cpu1_niden(&mut self) -> CPU1_NIDEN_W<'_>`[src]

Bit 9 - CPU1 (Micro cortex M33) non-invasive debug enable

`pub fn uuid_check(&mut self) -> UUID_CHECK_W<'_>`[src]

Bit 15 - Enforce UUID match during Debug authentication.

`pub fn inverse_value(&mut self) -> INVERSE_VALUE_W<'_>`[src]

Bits 16:31 - inverse value of bits [15:0]

`impl W<u32, Reg<u32, _CC_SOCU_DFLT>>`[src]

`pub fn niden(&mut self) -> NIDEN_W<'_>`[src]

Bit 0 - Non Secure non-invasive debug fixed state

`pub fn dbgen(&mut self) -> DBGEN_W<'_>`[src]

Bit 1 - Non Secure debug fixed state

`pub fn spniden(&mut self) -> SPNIDEN_W<'_>`[src]

Bit 2 - Secure non-invasive debug fixed state

`pub fn spiden(&mut self) -> SPIDEN_W<'_>`[src]

Bit 3 - Secure invasive debug fixed state

`pub fn tapen(&mut self) -> TAPEN_W<'_>`[src]

Bit 4 - JTAG TAP fixed state

`pub fn cpu1_dbgen(&mut self) -> CPU1_DBGEN_W<'_>`[src]

Bit 5 - CPU1 (Micro cortex M33) invasive debug fixed state

`pub fn isp_cmd_en(&mut self) -> ISP_CMD_EN_W<'_>`[src]

Bit 6 - ISP Boot Command fixed state

`pub fn fa_cmd_en(&mut self) -> FA_CMD_EN_W<'_>`[src]

Bit 7 - FA Command fixed state

`pub fn me_cmd_en(&mut self) -> ME_CMD_EN_W<'_>`[src]

Bit 8 - Flash Mass Erase Command fixed state

`pub fn cpu1_niden(&mut self) -> CPU1_NIDEN_W<'_>`[src]

Bit 9 - CPU1 (Micro cortex M33) non-invasive debug fixed state

`pub fn inverse_value(&mut self) -> INVERSE_VALUE_W<'_>`[src]

Bits 16:31 - inverse value of bits [15:0]

`impl W<u32, Reg<u32, _VENDOR_USAGE>>`[src]

`pub fn vendor_usage(&mut self) -> VENDOR_USAGE_W<'_>`[src]

Bits 16:31 - Upper 16 bits of vendor usage field defined in DAP. Lower 16-bits come from customer field area.

`impl W<u32, Reg<u32, _SECURE_BOOT_CFG>>`[src]

`pub fn rsa4k(&mut self) -> RSA4K_W<'_>`[src]

Bits 0:1 - Use RSA4096 keys only. 00- RSA2048 keys 01, 10, 11 - RSA4096 keys

`pub fn dice_enc_nxp_cfg(&mut self) -> DICE_ENC_NXP_CFG_W<'_>`[src]

Bits 2:3 - Include NXP area in DICE computation. 00 - not included 01, 10, 11 - included

`pub fn dice_cust_cfg(&mut self) -> DICE_CUST_CFG_W<'_>`[src]

Bits 4:5 - Include Customer factory area (including keys) in DICE computation. 00 - not included 01, 10, 11 - included

`pub fn skip_dice(&mut self) -> SKIP_DICE_W<'_>`[src]

Bits 6:7 - Skip DICE computation. 00 - Enable DICE 01,10,11 - Disable DICE

`pub fn tzm_image_type(&mut self) -> TZM_IMAGE_TYPE_W<'_>`[src]

Bits 8:9 - TrustZone-M mode. 00 - TZM mode in image header. 01 - Disable TZ-M. Boots to NonSecure. 10 - TZ-M enable boots to secure mode. 11 - Preset TZM checker from image header.

`pub fn block_set_key(&mut self) -> BLOCK_SET_KEY_W<'_>`[src]

Bits 10:11 - Block PUF key code generation. 00 - Enable Key code generation 01, 10, 11 - Disable key code generation

`pub fn block_enroll(&mut self) -> BLOCK_ENROLL_W<'_>`[src]

Bits 12:13 - Block PUF enrollement. 00 - Enable enrollment mode 01, 10, 11 - Disable further enrollmnet

`pub fn dice_inc_sec_epoch(&mut self) -> DICE_INC_SEC_EPOCH_W<'_>`[src]

Bits 14:15 - Include security EPOCH in DICE

`pub fn sec_boot_en(&mut self) -> SEC_BOOT_EN_W<'_>`[src]

Bits 30:31 - Secure boot enable. 00 - Plain image (internal flash with or without CRC) 01, 10, 11 - Boot signed images. (internal flash, RSA signed)

`impl W<u32, Reg<u32, _PRINCE_BASE_ADDR>>`[src]

`pub fn addr0_prg(&mut self) -> ADDR0_PRG_W<'_>`[src]

Bits 0:3 - Programmable portion of the base address of region 0.

`pub fn addr1_prg(&mut self) -> ADDR1_PRG_W<'_>`[src]

Bits 4:7 - Programmable portion of the base address of region 1.

`pub fn addr2_prg(&mut self) -> ADDR2_PRG_W<'_>`[src]

Bits 8:11 - Programmable portion of the base address of region 2.

`pub fn lock_reg0(&mut self) -> LOCK_REG0_W<'_>`[src]

Bits 16:17 - Lock PRINCE region0 settings. 00 - Region is not locked. 01, 10, 11 - Region is locked.

`pub fn lock_reg1(&mut self) -> LOCK_REG1_W<'_>`[src]

Bits 18:19 - Lock PRINCE region1 settings. 00 - Region is not locked. 01, 10, 11 - Region is locked.

`pub fn lock_reg2(&mut self) -> LOCK_REG2_W<'_>`[src]

Bits 20:21 - Lock PRINCE region2 settings. 00 - Region is not locked. 01, 10, 11 - Region is locked.

`pub fn reg0_erase_check_en(&mut self) -> REG0_ERASE_CHECK_EN_W<'_>`[src]

Bits 24:25 - For PRINCE region0 enable checking whether all encrypted pages are erased together. 00 - Check is disabled. 01, 10, 11 - Check is enabled.

`pub fn reg1_erase_check_en(&mut self) -> REG1_ERASE_CHECK_EN_W<'_>`[src]

Bits 26:27 - For PRINCE region1 enable checking whether all encrypted pages are erased together. 00 - Check is disabled. 01, 10, 11 - Check is enabled.

`pub fn reg2_erase_check_en(&mut self) -> REG2_ERASE_CHECK_EN_W<'_>`[src]

Bits 28:29 - For PRINCE region2 enable checking whether all encrypted pages are erased together. 00 - Check is disabled. 01, 10, 11 - Check is enabled.

`impl W<u32, Reg<u32, _PRINCE_SR_0>>`[src]

`pub fn field(&mut self) -> FIELD_W<'_>`[src]

Bits 0:31 - .

`impl W<u32, Reg<u32, _PRINCE_SR_1>>`[src]

`pub fn field(&mut self) -> FIELD_W<'_>`[src]

Bits 0:31 - .

`impl W<u32, Reg<u32, _PRINCE_SR_2>>`[src]

`pub fn field(&mut self) -> FIELD_W<'_>`[src]

Bits 0:31 - .

`impl W<u32, Reg<u32, _XTAL_32KHZ_CAPABANK_TRIM>>`[src]

`pub fn trim_valid(&mut self) -> TRIM_VALID_W<'_>`[src]

Bit 0 - 0 : Capa Bank trimmings not valid. Default trimmings value are used. 1 : Capa Bank trimmings valid.

`pub fn xtal_load_cap_iec_pf_x100(&mut self) -> XTAL_LOAD_CAP_IEC_PF_X100_W<'_>`[src]

Bits 1:10 - Load capacitance, pF x 100. For example, 6pF becomes 600.

`pub fn pcb_xin_para_cap_pf_x100(&mut self) -> PCB_XIN_PARA_CAP_PF_X100_W<'_>`[src]

Bits 11:20 - PCB XIN parasitic capacitance, pF x 100. For example, 6pF becomes 600.

`pub fn pcb_xout_para_cap_pf_x100(&mut self) -> PCB_XOUT_PARA_CAP_PF_X100_W<'_>`[src]

Bits 21:30 - PCB XOUT parasitic capacitance, pF x 100. For example, 6pF becomes 600.

`impl W<u32, Reg<u32, _XTAL_16MHZ_CAPABANK_TRIM>>`[src]

`pub fn trim_valid(&mut self) -> TRIM_VALID_W<'_>`[src]

Bit 0 - 0 : Capa Bank trimmings not valid. Default trimmings value are used. 1 : Capa Bank trimmings valid.

`pub fn xtal_load_cap_iec_pf_x100(&mut self) -> XTAL_LOAD_CAP_IEC_PF_X100_W<'_>`[src]

Bits 1:10 - Load capacitance, pF x 100. For example, 6pF becomes 600.

`pub fn pcb_xin_para_cap_pf_x100(&mut self) -> PCB_XIN_PARA_CAP_PF_X100_W<'_>`[src]

`pub fn index(&mut self) -> INDEX_W<'_>`[src]

`impl W<u32, Reg<u32, _USER_KEK_HEADER1>>`[src]

`pub fn type_(&mut self) -> TYPE_W<'_>`[src]

Bits 0:1 - .

`pub fn index(&mut self) -> INDEX_W<'_>`[src]

`impl W<u32, Reg<u32, _UDS_HEADER1>>`[src]

`pub fn type_(&mut self) -> TYPE_W<'_>`[src]

Bits 0:1 - .

`pub fn index(&mut self) -> INDEX_W<'_>`[src]

`impl W<u32, Reg<u32, _PRINCE_REGION0_HEADER1>>`[src]

`pub fn type_(&mut self) -> TYPE_W<'_>`[src]

Bits 0:1 - .

`pub fn index(&mut self) -> INDEX_W<'_>`[src]

`impl W<u32, Reg<u32, _PRINCE_REGION1_HEADER1>>`[src]

`pub fn type_(&mut self) -> TYPE_W<'_>`[src]

Bits 0:1 - .

`pub fn index(&mut self) -> INDEX_W<'_>`[src]

`impl W<u32, Reg<u32, _PRINCE_REGION2_HEADER1>>`[src]

`pub fn type_(&mut self) -> TYPE_W<'_>`[src]

Bits 0:1 - .

`pub fn index(&mut self) -> INDEX_W<'_>`[src]

`pub fn pri_cpu0_sbus(&mut self) -> PRI_CPU0_SBUS_W<'_>`[src]

Bits 2:3 - CPU0 S-AHB bus.

`pub fn pri_cpu1_cbus(&mut self) -> PRI_CPU1_CBUS_W<'_>`[src]

Bits 4:5 - CPU1 C-AHB bus.

`pub fn pri_cpu1_sbus(&mut self) -> PRI_CPU1_SBUS_W<'_>`[src]

Bits 6:7 - CPU1 S-AHB bus.

`pub fn pri_usb_fs(&mut self) -> PRI_USB_FS_W<'_>`[src]

Bits 8:9 - USB-FS.(USB0)

`pub fn pri_sdma0(&mut self) -> PRI_SDMA0_W<'_>`[src]

Bits 10:11 - DMA0 controller priority.

`pub fn pri_sdio(&mut self) -> PRI_SDIO_W<'_>`[src]

Bits 16:17 - SDIO.

`pub fn pri_pq(&mut self) -> PRI_PQ_W<'_>`[src]

Bits 18:19 - PQ (HW Accelerator).

`pub fn pri_hash_aes(&mut self) -> PRI_HASH_AES_W<'_>`[src]

Bits 20:21 - HASH_AES.

`pub fn pri_usb_hs(&mut self) -> PRI_USB_HS_W<'_>`[src]

Bits 22:23 - USB-HS.(USB1)

`pub fn pri_sdma1(&mut self) -> PRI_SDMA1_W<'_>`[src]

Bits 24:25 - DMA1 controller priority.

`impl W<u32, Reg<u32, _CPU0STCKCAL>>`[src]

`pub fn tenms(&mut self) -> TENMS_W<'_>`[src]

Bits 0:23 - Reload value for 10ms (100Hz) timing, subject to system clock skew errors. If the value reads as zero, the calibration value is not known.

`pub fn skew(&mut self) -> SKEW_W<'_>`[src]

Bit 24 - Initial value for the Systick timer.

`pub fn noref(&mut self) -> NOREF_W<'_>`[src]

Bit 25 - Indicates whether the device provides a reference clock to the processor: 0 = reference clock provided; 1 = no reference clock provided.

`impl W<u32, Reg<u32, _CPU0NSTCKCAL>>`[src]

`pub fn tenms(&mut self) -> TENMS_W<'_>`[src]

Bits 0:23 - Reload value for 10 ms (100 Hz) timing, subject to system clock skew errors. If the value reads as zero, the calibration value is not known.

`pub fn skew(&mut self) -> SKEW_W<'_>`[src]

Bit 24 - Indicates whether the TENMS value is exact: 0 = TENMS value is exact; 1 = TENMS value is inexact, or not given.

`pub fn noref(&mut self) -> NOREF_W<'_>`[src]

Bit 25 - Initial value for the Systick timer.

`impl W<u32, Reg<u32, _CPU1STCKCAL>>`[src]

`pub fn tenms(&mut self) -> TENMS_W<'_>`[src]

Bits 0:23 - Reload value for 10ms (100Hz) timing, subject to system clock skew errors. If the value reads as zero, the calibration value is not known.

`pub fn skew(&mut self) -> SKEW_W<'_>`[src]

Bit 24 - Indicates whether the TENMS value is exact: 0 = TENMS value is exact; 1 = TENMS value is inexact, or not given.

`pub fn noref(&mut self) -> NOREF_W<'_>`[src]

Bit 25 - Indicates whether the device provides a reference clock to the processor: 0 = reference clock provided; 1 = no reference clock provided.

`impl W<u32, Reg<u32, _NMISRC>>`[src]

`pub fn irqcpu0(&mut self) -> IRQCPU0_W<'_>`[src]

Bits 0:5 - The IRQ number of the interrupt that acts as the Non-Maskable Interrupt (NMI) for the CPU0, if enabled by NMIENCPU0.

`pub fn irqcpu1(&mut self) -> IRQCPU1_W<'_>`[src]

Bits 8:13 - The IRQ number of the interrupt that acts as the Non-Maskable Interrupt (NMI) for the CPU1, if enabled by NMIENCPU1.

`pub fn nmiencpu1(&mut self) -> NMIENCPU1_W<'_>`[src]

Bit 30 - Write a 1 to this bit to enable the Non-Maskable Interrupt (NMI) source selected by IRQCPU1.

`pub fn nmiencpu0(&mut self) -> NMIENCPU0_W<'_>`[src]

Bit 31 - Write a 1 to this bit to enable the Non-Maskable Interrupt (NMI) source selected by IRQCPU0.

`impl W<u32, Reg<u32, _PRESETCTRL0>>`[src]

`pub fn rom_rst(&mut self) -> ROM_RST_W<'_>`[src]

Bit 1 - ROM reset control.

`pub fn sram_ctrl1_rst(&mut self) -> SRAM_CTRL1_RST_W<'_>`[src]

Bit 3 - SRAM Controller 1 reset control.

`pub fn sram_ctrl2_rst(&mut self) -> SRAM_CTRL2_RST_W<'_>`[src]

Bit 4 - SRAM Controller 2 reset control.

`pub fn sram_ctrl3_rst(&mut self) -> SRAM_CTRL3_RST_W<'_>`[src]

Bit 5 - SRAM Controller 3 reset control.

`pub fn sram_ctrl4_rst(&mut self) -> SRAM_CTRL4_RST_W<'_>`[src]

Bit 6 - SRAM Controller 4 reset control.

`pub fn flash_rst(&mut self) -> FLASH_RST_W<'_>`[src]

Bit 7 - Flash controller reset control.

`pub fn fmc_rst(&mut self) -> FMC_RST_W<'_>`[src]

Bit 8 - FMC controller reset control.

`pub fn mux_rst(&mut self) -> MUX_RST_W<'_>`[src]

Bit 11 - Input Mux reset control.

`pub fn iocon_rst(&mut self) -> IOCON_RST_W<'_>`[src]

Bit 13 - I/O controller reset control.

`pub fn gpio0_rst(&mut self) -> GPIO0_RST_W<'_>`[src]

Bit 14 - GPIO0 reset control.

`pub fn gpio1_rst(&mut self) -> GPIO1_RST_W<'_>`[src]

Bit 15 - GPIO1 reset control.

`pub fn gpio2_rst(&mut self) -> GPIO2_RST_W<'_>`[src]

Bit 16 - GPIO2 reset control.

`pub fn gpio3_rst(&mut self) -> GPIO3_RST_W<'_>`[src]

Bit 17 - GPIO3 reset control.

`pub fn pint_rst(&mut self) -> PINT_RST_W<'_>`[src]

Bit 18 - Pin interrupt (PINT) reset control.

`pub fn gint_rst(&mut self) -> GINT_RST_W<'_>`[src]

Bit 19 - Group interrupt (GINT) reset control.

`pub fn dma0_rst(&mut self) -> DMA0_RST_W<'_>`[src]

Bit 20 - DMA0 reset control.

`pub fn crcgen_rst(&mut self) -> CRCGEN_RST_W<'_>`[src]

Bit 21 - CRCGEN reset control.

`pub fn wwdt_rst(&mut self) -> WWDT_RST_W<'_>`[src]

Bit 22 - Watchdog Timer reset control.

`pub fn rtc_rst(&mut self) -> RTC_RST_W<'_>`[src]

Bit 23 - Real Time Clock (RTC) reset control.

`pub fn mailbox_rst(&mut self) -> MAILBOX_RST_W<'_>`[src]

Bit 26 - Inter CPU communication Mailbox reset control.

`pub fn adc_rst(&mut self) -> ADC_RST_W<'_>`[src]

Bit 27 - ADC reset control.

`impl W<u32, Reg<u32, _PRESETCTRL1>>`[src]

`pub fn mrt_rst(&mut self) -> MRT_RST_W<'_>`[src]

Bit 0 - MRT reset control.

`pub fn ostimer_rst(&mut self) -> OSTIMER_RST_W<'_>`[src]

Bit 1 - OS Event Timer reset control.

`pub fn sct_rst(&mut self) -> SCT_RST_W<'_>`[src]

Bit 2 - SCT reset control.

`pub fn sctipu_rst(&mut self) -> SCTIPU_RST_W<'_>`[src]

Bit 6 - SCTIPU reset control.

`pub fn utick_rst(&mut self) -> UTICK_RST_W<'_>`[src]

Bit 10 - UTICK reset control.

`pub fn fc0_rst(&mut self) -> FC0_RST_W<'_>`[src]

Bit 11 - FC0 reset control.

`pub fn fc1_rst(&mut self) -> FC1_RST_W<'_>`[src]

Bit 12 - FC1 reset control.

`pub fn fc2_rst(&mut self) -> FC2_RST_W<'_>`[src]

Bit 13 - FC2 reset control.

`pub fn fc3_rst(&mut self) -> FC3_RST_W<'_>`[src]

Bit 14 - FC3 reset control.

`pub fn fc4_rst(&mut self) -> FC4_RST_W<'_>`[src]

Bit 15 - FC4 reset control.

`pub fn fc5_rst(&mut self) -> FC5_RST_W<'_>`[src]

Bit 16 - FC5 reset control.

`pub fn fc6_rst(&mut self) -> FC6_RST_W<'_>`[src]

Bit 17 - FC6 reset control.

`pub fn fc7_rst(&mut self) -> FC7_RST_W<'_>`[src]

Bit 18 - FC7 reset control.

`pub fn timer2_rst(&mut self) -> TIMER2_RST_W<'_>`[src]

Bit 22 - Timer 2 reset control.

`pub fn usb0_dev_rst(&mut self) -> USB0_DEV_RST_W<'_>`[src]

Bit 25 - USB0 DEV reset control.

`pub fn timer0_rst(&mut self) -> TIMER0_RST_W<'_>`[src]

Bit 26 - Timer 0 reset control.

`pub fn timer1_rst(&mut self) -> TIMER1_RST_W<'_>`[src]

Bit 27 - Timer 1 reset control.

`impl W<u32, Reg<u32, _PRESETCTRL2>>`[src]

`pub fn dma1_rst(&mut self) -> DMA1_RST_W<'_>`[src]

Bit 1 - DMA1 reset control.

`pub fn comp_rst(&mut self) -> COMP_RST_W<'_>`[src]

Bit 2 - Comparator reset control.

`pub fn sdio_rst(&mut self) -> SDIO_RST_W<'_>`[src]

Bit 3 - SDIO reset control.

`pub fn usb1_host_rst(&mut self) -> USB1_HOST_RST_W<'_>`[src]

Bit 4 - USB1 Host reset control.

`pub fn usb1_dev_rst(&mut self) -> USB1_DEV_RST_W<'_>`[src]

Bit 5 - USB1 dev reset control.

`pub fn usb1_ram_rst(&mut self) -> USB1_RAM_RST_W<'_>`[src]

Bit 6 - USB1 RAM reset control.

`pub fn usb1_phy_rst(&mut self) -> USB1_PHY_RST_W<'_>`[src]

Bit 7 - USB1 PHY reset control.

`pub fn freqme_rst(&mut self) -> FREQME_RST_W<'_>`[src]

Bit 8 - Frequency meter reset control.

`pub fn rng_rst(&mut self) -> RNG_RST_W<'_>`[src]

Bit 13 - RNG reset control.

`pub fn sysctl_rst(&mut self) -> SYSCTL_RST_W<'_>`[src]

Bit 15 - SYSCTL Block reset.

`pub fn usb0_hostm_rst(&mut self) -> USB0_HOSTM_RST_W<'_>`[src]

Bit 16 - USB0 Host Master reset control.

`pub fn usb0_hosts_rst(&mut self) -> USB0_HOSTS_RST_W<'_>`[src]

Bit 17 - USB0 Host Slave reset control.

`pub fn hash_aes_rst(&mut self) -> HASH_AES_RST_W<'_>`[src]

Bit 18 - HASH_AES reset control.

`pub fn pq_rst(&mut self) -> PQ_RST_W<'_>`[src]

Bit 19 - Power Quad reset control.

`pub fn plulut_rst(&mut self) -> PLULUT_RST_W<'_>`[src]

Bit 20 - PLU LUT reset control.

`pub fn timer3_rst(&mut self) -> TIMER3_RST_W<'_>`[src]

Bit 21 - Timer 3 reset control.

`pub fn timer4_rst(&mut self) -> TIMER4_RST_W<'_>`[src]

Bit 22 - Timer 4 reset control.

`pub fn puf_rst(&mut self) -> PUF_RST_W<'_>`[src]

Bit 23 - PUF reset control reset control.

`pub fn casper_rst(&mut self) -> CASPER_RST_W<'_>`[src]

Bit 24 - Casper reset control.

`pub fn analog_ctrl_rst(&mut self) -> ANALOG_CTRL_RST_W<'_>`[src]

Bit 27 - analog control reset control.

`pub fn hs_lspi_rst(&mut self) -> HS_LSPI_RST_W<'_>`[src]

Bit 28 - HS LSPI reset control.

`pub fn gpio_sec_rst(&mut self) -> GPIO_SEC_RST_W<'_>`[src]

Bit 29 - GPIO secure reset control.

`pub fn gpio_sec_int_rst(&mut self) -> GPIO_SEC_INT_RST_W<'_>`[src]

Bit 30 - GPIO secure int reset control.

`impl W<u32, Reg<u32, _PRESETCTRLSET>>`[src]

`pub fn data(&mut self) -> DATA_W<'_>`[src]

Bits 0:31 - Data array value

`impl W<u32, Reg<u32, _PRESETCTRLCLR>>`[src]

`pub fn data(&mut self) -> DATA_W<'_>`[src]

Bits 0:31 - Data array value

`impl W<u32, Reg<u32, _SWR_RESET>>`[src]

`pub fn swr_reset(&mut self) -> SWR_RESET_W<'_>`[src]

Bits 0:31 - Write 0x5A00_0001 to generate a software_reset.

`impl W<u32, Reg<u32, _AHBCLKCTRL0>>`[src]

`pub fn rom(&mut self) -> ROM_W<'_>`[src]

Bit 1 - Enables the clock for the ROM.

`pub fn sram_ctrl1(&mut self) -> SRAM_CTRL1_W<'_>`[src]

Bit 3 - Enables the clock for the SRAM Controller 1.

`pub fn sram_ctrl2(&mut self) -> SRAM_CTRL2_W<'_>`[src]

Bit 4 - Enables the clock for the SRAM Controller 2.

`pub fn sram_ctrl3(&mut self) -> SRAM_CTRL3_W<'_>`[src]

Bit 5 - Enables the clock for the SRAM Controller 3.

`pub fn sram_ctrl4(&mut self) -> SRAM_CTRL4_W<'_>`[src]

Bit 6 - Enables the clock for the SRAM Controller 4.

`pub fn flash(&mut self) -> FLASH_W<'_>`[src]

Bit 7 - Enables the clock for the Flash controller.

`pub fn fmc(&mut self) -> FMC_W<'_>`[src]

Bit 8 - Enables the clock for the FMC controller.

`pub fn mux(&mut self) -> MUX_W<'_>`[src]

Bit 11 - Enables the clock for the Input Mux.

`pub fn iocon(&mut self) -> IOCON_W<'_>`[src]

Bit 13 - Enables the clock for the I/O controller.

`pub fn gpio0(&mut self) -> GPIO0_W<'_>`[src]

Bit 14 - Enables the clock for the GPIO0.

`pub fn gpio1(&mut self) -> GPIO1_W<'_>`[src]

Bit 15 - Enables the clock for the GPIO1.

`pub fn gpio2(&mut self) -> GPIO2_W<'_>`[src]

Bit 16 - Enables the clock for the GPIO2.

`pub fn gpio3(&mut self) -> GPIO3_W<'_>`[src]

Bit 17 - Enables the clock for the GPIO3.

`pub fn pint(&mut self) -> PINT_W<'_>`[src]

Bit 18 - Enables the clock for the Pin interrupt (PINT).

`pub fn gint(&mut self) -> GINT_W<'_>`[src]

Bit 19 - Enables the clock for the Group interrupt (GINT).

`pub fn dma0(&mut self) -> DMA0_W<'_>`[src]

Bit 20 - Enables the clock for the DMA0.

`pub fn crcgen(&mut self) -> CRCGEN_W<'_>`[src]

Bit 21 - Enables the clock for the CRCGEN.

`pub fn wwdt(&mut self) -> WWDT_W<'_>`[src]

Bit 22 - Enables the clock for the Watchdog Timer.

`pub fn rtc(&mut self) -> RTC_W<'_>`[src]

Bit 23 - Enables the clock for the Real Time Clock (RTC).

`pub fn mailbox(&mut self) -> MAILBOX_W<'_>`[src]

Bit 26 - Enables the clock for the Inter CPU communication Mailbox.

`pub fn adc(&mut self) -> ADC_W<'_>`[src]

Bit 27 - Enables the clock for the ADC.

`impl W<u32, Reg<u32, _AHBCLKCTRL1>>`[src]

`pub fn mrt(&mut self) -> MRT_W<'_>`[src]

Bit 0 - Enables the clock for the MRT.

`pub fn ostimer(&mut self) -> OSTIMER_W<'_>`[src]

Bit 1 - Enables the clock for the OS Event Timer.

`pub fn sct(&mut self) -> SCT_W<'_>`[src]

Bit 2 - Enables the clock for the SCT.

`pub fn utick(&mut self) -> UTICK_W<'_>`[src]

Bit 10 - Enables the clock for the UTICK.

`pub fn fc0(&mut self) -> FC0_W<'_>`[src]

Bit 11 - Enables the clock for the FC0.

`pub fn fc1(&mut self) -> FC1_W<'_>`[src]

Bit 12 - Enables the clock for the FC1.

`pub fn fc2(&mut self) -> FC2_W<'_>`[src]

Bit 13 - Enables the clock for the FC2.

`pub fn fc3(&mut self) -> FC3_W<'_>`[src]

Bit 14 - Enables the clock for the FC3.

`pub fn fc4(&mut self) -> FC4_W<'_>`[src]

Bit 15 - Enables the clock for the FC4.

`pub fn fc5(&mut self) -> FC5_W<'_>`[src]

Bit 16 - Enables the clock for the FC5.

`pub fn fc6(&mut self) -> FC6_W<'_>`[src]

Bit 17 - Enables the clock for the FC6.

`pub fn fc7(&mut self) -> FC7_W<'_>`[src]

Bit 18 - Enables the clock for the FC7.

`pub fn timer2(&mut self) -> TIMER2_W<'_>`[src]

Bit 22 - Enables the clock for the Timer 2.

`pub fn usb0_dev(&mut self) -> USB0_DEV_W<'_>`[src]

Bit 25 - Enables the clock for the USB0 DEV.

`pub fn timer0(&mut self) -> TIMER0_W<'_>`[src]

Bit 26 - Enables the clock for the Timer 0.

`pub fn timer1(&mut self) -> TIMER1_W<'_>`[src]

Bit 27 - Enables the clock for the Timer 1.

`impl W<u32, Reg<u32, _AHBCLKCTRL2>>`[src]

`pub fn dma1(&mut self) -> DMA1_W<'_>`[src]

Bit 1 - Enables the clock for the DMA1.

`pub fn comp(&mut self) -> COMP_W<'_>`[src]

Bit 2 - Enables the clock for the Comparator.

`pub fn sdio(&mut self) -> SDIO_W<'_>`[src]

Bit 3 - Enables the clock for the SDIO.

`pub fn usb1_host(&mut self) -> USB1_HOST_W<'_>`[src]

Bit 4 - Enables the clock for the USB1 Host.

`pub fn usb1_dev(&mut self) -> USB1_DEV_W<'_>`[src]

Bit 5 - Enables the clock for the USB1 dev.

`pub fn usb1_ram(&mut self) -> USB1_RAM_W<'_>`[src]

Bit 6 - Enables the clock for the USB1 RAM.

`pub fn usb1_phy(&mut self) -> USB1_PHY_W<'_>`[src]

Bit 7 - Enables the clock for the USB1 PHY.

`pub fn freqme(&mut self) -> FREQME_W<'_>`[src]

Bit 8 - Enables the clock for the Frequency meter.

`pub fn rng(&mut self) -> RNG_W<'_>`[src]

Bit 13 - Enables the clock for the RNG.

`pub fn sysctl(&mut self) -> SYSCTL_W<'_>`[src]

Bit 15 - SYSCTL block clock.

`pub fn usb0_hostm(&mut self) -> USB0_HOSTM_W<'_>`[src]

Bit 16 - Enables the clock for the USB0 Host Master.

`pub fn usb0_hosts(&mut self) -> USB0_HOSTS_W<'_>`[src]

Bit 17 - Enables the clock for the USB0 Host Slave.

`pub fn hash_aes(&mut self) -> HASH_AES_W<'_>`[src]

Bit 18 - Enables the clock for the HASH_AES.

`pub fn pq(&mut self) -> PQ_W<'_>`[src]

Bit 19 - Enables the clock for the Power Quad.

`pub fn plulut(&mut self) -> PLULUT_W<'_>`[src]

Bit 20 - Enables the clock for the PLU LUT.

`pub fn timer3(&mut self) -> TIMER3_W<'_>`[src]

Bit 21 - Enables the clock for the Timer 3.

`pub fn timer4(&mut self) -> TIMER4_W<'_>`[src]

Bit 22 - Enables the clock for the Timer 4.

`pub fn puf(&mut self) -> PUF_W<'_>`[src]

Bit 23 - Enables the clock for the PUF reset control.

`pub fn casper(&mut self) -> CASPER_W<'_>`[src]

Bit 24 - Enables the clock for the Casper.

`pub fn analog_ctrl(&mut self) -> ANALOG_CTRL_W<'_>`[src]

Bit 27 - Enables the clock for the analog control.

`pub fn hs_lspi(&mut self) -> HS_LSPI_W<'_>`[src]

Bit 28 - Enables the clock for the HS LSPI.

`pub fn gpio_sec(&mut self) -> GPIO_SEC_W<'_>`[src]

`impl W<u32, Reg<u32, _SYSTICKCLKDIV0>>`[src]

`pub fn div(&mut self) -> DIV_W<'_>`[src]

Bits 0:7 - Clock divider value.

`pub fn reset(&mut self) -> RESET_W<'_>`[src]

Bit 29 - Resets the divider counter.

`pub fn halt(&mut self) -> HALT_W<'_>`[src]

Bit 30 - Halts the divider counter.

`impl W<u32, Reg<u32, _SYSTICKCLKDIV1>>`[src]

`pub fn div(&mut self) -> DIV_W<'_>`[src]

Bits 0:7 - Clock divider value.

`pub fn reset(&mut self) -> RESET_W<'_>`[src]

Bit 29 - Resets the divider counter.

`pub fn halt(&mut self) -> HALT_W<'_>`[src]

Bit 30 - Halts the divider counter.

`impl W<u32, Reg<u32, _TRACECLKDIV>>`[src]

`pub fn div(&mut self) -> DIV_W<'_>`[src]

Bits 0:7 - Clock divider value.

`pub fn reset(&mut self) -> RESET_W<'_>`[src]

Bit 29 - Resets the divider counter.

`pub fn halt(&mut self) -> HALT_W<'_>`[src]

Bit 30 - Halts the divider counter.

`impl W<u32, Reg<u32, _FLEXFRG0CTRL>>`[src]

`pub fn div(&mut self) -> DIV_W<'_>`[src]

Bits 0:7 - Denominator of the fractional rate divider.

`pub fn mult(&mut self) -> MULT_W<'_>`[src]

Bits 8:15 - Numerator of the fractional rate divider.

`impl W<u32, Reg<u32, _FLEXFRGXCTRL0>>`[src]

`pub fn data(&mut self) -> DATA_W<'_>`[src]

Bits 0:31 - Data array value

`impl W<u32, Reg<u32, _FLEXFRG1CTRL>>`[src]

`pub fn div(&mut self) -> DIV_W<'_>`[src]

Bits 0:7 - Denominator of the fractional rate divider.

`pub fn mult(&mut self) -> MULT_W<'_>`[src]

Bits 8:15 - Numerator of the fractional rate divider.

`impl W<u32, Reg<u32, _FLEXFRGXCTRL1>>`[src]

`pub fn data(&mut self) -> DATA_W<'_>`[src]

Bits 0:31 - Data array value

`impl W<u32, Reg<u32, _FLEXFRG2CTRL>>`[src]

`pub fn div(&mut self) -> DIV_W<'_>`[src]

Bits 0:7 - Denominator of the fractional rate divider.

`pub fn mult(&mut self) -> MULT_W<'_>`[src]

Bits 8:15 - Numerator of the fractional rate divider.

`impl W<u32, Reg<u32, _FLEXFRGXCTRL2>>`[src]

`pub fn data(&mut self) -> DATA_W<'_>`[src]

Bits 0:31 - Data array value

`impl W<u32, Reg<u32, _FLEXFRG3CTRL>>`[src]

`pub fn div(&mut self) -> DIV_W<'_>`[src]

Bits 0:7 - Denominator of the fractional rate divider.

`pub fn mult(&mut self) -> MULT_W<'_>`[src]

Bits 8:15 - Numerator of the fractional rate divider.

`impl W<u32, Reg<u32, _FLEXFRGXCTRL3>>`[src]

`pub fn data(&mut self) -> DATA_W<'_>`[src]

Bits 0:31 - Data array value

`impl W<u32, Reg<u32, _FLEXFRG4CTRL>>`[src]

`pub fn div(&mut self) -> DIV_W<'_>`[src]

Bits 0:7 - Denominator of the fractional rate divider.

`pub fn mult(&mut self) -> MULT_W<'_>`[src]

Bits 8:15 - Numerator of the fractional rate divider.

`impl W<u32, Reg<u32, _FLEXFRGXCTRL4>>`[src]

`pub fn data(&mut self) -> DATA_W<'_>`[src]

Bits 0:31 - Data array value

`impl W<u32, Reg<u32, _FLEXFRG5CTRL>>`[src]

`pub fn div(&mut self) -> DIV_W<'_>`[src]

Bits 0:7 - Denominator of the fractional rate divider.

`pub fn mult(&mut self) -> MULT_W<'_>`[src]

Bits 8:15 - Numerator of the fractional rate divider.

`impl W<u32, Reg<u32, _FLEXFRGXCTRL5>>`[src]

`pub fn data(&mut self) -> DATA_W<'_>`[src]

Bits 0:31 - Data array value

`impl W<u32, Reg<u32, _FLEXFRG6CTRL>>`[src]

`pub fn div(&mut self) -> DIV_W<'_>`[src]

Bits 0:7 - Denominator of the fractional rate divider.

`pub fn mult(&mut self) -> MULT_W<'_>`[src]

Bits 8:15 - Numerator of the fractional rate divider.

`impl W<u32, Reg<u32, _FLEXFRGXCTRL6>>`[src]

`pub fn data(&mut self) -> DATA_W<'_>`[src]

Bits 0:31 - Data array value

`impl W<u32, Reg<u32, _FLEXFRG7CTRL>>`[src]

`pub fn div(&mut self) -> DIV_W<'_>`[src]

Bits 0:7 - Denominator of the fractional rate divider.

`pub fn mult(&mut self) -> MULT_W<'_>`[src]

Bits 8:15 - Numerator of the fractional rate divider.

`impl W<u32, Reg<u32, _FLEXFRGXCTRL7>>`[src]

`pub fn data(&mut self) -> DATA_W<'_>`[src]

Bits 0:31 - Data array value

`impl W<u32, Reg<u32, _AHBCLKDIV>>`[src]

`pub fn div(&mut self) -> DIV_W<'_>`[src]

Bits 0:7 - Clock divider value.

`pub fn reset(&mut self) -> RESET_W<'_>`[src]

Bit 29 - Resets the divider counter.

`pub fn halt(&mut self) -> HALT_W<'_>`[src]

Bit 30 - Halts the divider counter.

`impl W<u32, Reg<u32, _CLKOUTDIV>>`[src]

`pub fn div(&mut self) -> DIV_W<'_>`[src]

Bits 0:7 - Clock divider value.

`pub fn reset(&mut self) -> RESET_W<'_>`[src]

Bit 29 - Resets the divider counter.

`pub fn halt(&mut self) -> HALT_W<'_>`[src]

Bit 30 - Halts the divider counter.

`impl W<u32, Reg<u32, _FROHFDIV>>`[src]

`pub fn div(&mut self) -> DIV_W<'_>`[src]

Bits 0:7 - Clock divider value.

`pub fn reset(&mut self) -> RESET_W<'_>`[src]

Bit 29 - Resets the divider counter.

`pub fn halt(&mut self) -> HALT_W<'_>`[src]

Bit 30 - Halts the divider counter.

`impl W<u32, Reg<u32, _WDTCLKDIV>>`[src]

`pub fn div(&mut self) -> DIV_W<'_>`[src]

Bits 0:5 - Clock divider value.

`pub fn reset(&mut self) -> RESET_W<'_>`[src]

Bit 29 - Resets the divider counter.

`pub fn halt(&mut self) -> HALT_W<'_>`[src]

Bit 30 - Halts the divider counter.

`impl W<u32, Reg<u32, _ADCCLKDIV>>`[src]

`pub fn div(&mut self) -> DIV_W<'_>`[src]

Bits 0:2 - Clock divider value.

`pub fn reset(&mut self) -> RESET_W<'_>`[src]

Bit 29 - Resets the divider counter.

`pub fn halt(&mut self) -> HALT_W<'_>`[src]

Bit 30 - Halts the divider counter.

`impl W<u32, Reg<u32, _USB0CLKDIV>>`[src]

`pub fn div(&mut self) -> DIV_W<'_>`[src]

Bits 0:7 - Clock divider value.

`pub fn reset(&mut self) -> RESET_W<'_>`[src]

Bit 29 - Resets the divider counter.

`pub fn halt(&mut self) -> HALT_W<'_>`[src]

Bit 30 - Halts the divider counter.

`impl W<u32, Reg<u32, _MCLKDIV>>`[src]

`pub fn div(&mut self) -> DIV_W<'_>`[src]

Bits 0:7 - Clock divider value.

`pub fn reset(&mut self) -> RESET_W<'_>`[src]

Bit 29 - Resets the divider counter.

`pub fn halt(&mut self) -> HALT_W<'_>`[src]

Bit 30 - Halts the divider counter.

`impl W<u32, Reg<u32, _SCTCLKDIV>>`[src]

`pub fn div(&mut self) -> DIV_W<'_>`[src]

Bits 0:7 - Clock divider value.

`pub fn reset(&mut self) -> RESET_W<'_>`[src]

Bit 29 - Resets the divider counter.

`pub fn halt(&mut self) -> HALT_W<'_>`[src]

Bit 30 - Halts the divider counter.

`impl W<u32, Reg<u32, _SDIOCLKDIV>>`[src]

`pub fn div(&mut self) -> DIV_W<'_>`[src]

Bits 0:7 - Clock divider value.

`pub fn reset(&mut self) -> RESET_W<'_>`[src]

Bit 29 - Resets the divider counter.

`pub fn halt(&mut self) -> HALT_W<'_>`[src]

Bit 30 - Halts the divider counter.

`impl W<u32, Reg<u32, _PLL0CLKDIV>>`[src]

`pub fn div(&mut self) -> DIV_W<'_>`[src]

Bits 0:7 - Clock divider value.

`pub fn reset(&mut self) -> RESET_W<'_>`[src]

Bit 29 - Resets the divider counter.

`pub fn halt(&mut self) -> HALT_W<'_>`[src]

Bit 30 - Halts the divider counter.

`impl W<u32, Reg<u32, _CLOCKGENUPDATELOCKOUT>>`[src]

`pub fn clockgenupdatelockout(&mut self) -> CLOCKGENUPDATELOCKOUT_W<'_>`[src]

Bits 0:31 - Control clock configuration registers access (like xxxDIV, xxxSEL).

`impl W<u32, Reg<u32, _FMCCR>>`[src]

`pub fn flashtim(&mut self) -> FLASHTIM_W<'_>`[src]

Bits 12:15 - Flash memory access time.

`impl W<u32, Reg<u32, _USB0NEEDCLKCTRL>>`[src]

`pub fn ap_fs_dev_needclk(&mut self) -> AP_FS_DEV_NEEDCLK_W<'_>`[src]

Bit 0 - USB0 Device USB0_NEEDCLK signal control:.

`pub fn pol_fs_dev_needclk(&mut self) -> POL_FS_DEV_NEEDCLK_W<'_>`[src]

Bit 1 - USB0 Device USB0_NEEDCLK polarity for triggering the USB0 wake-up interrupt:.

`pub fn ap_fs_host_needclk(&mut self) -> AP_FS_HOST_NEEDCLK_W<'_>`[src]

Bit 2 - USB0 Host USB0_NEEDCLK signal control:.

`pub fn pol_fs_host_needclk(&mut self) -> POL_FS_HOST_NEEDCLK_W<'_>`[src]

Bit 3 - USB0 Host USB0_NEEDCLK polarity for triggering the USB0 wake-up interrupt:.

`impl W<u32, Reg<u32, _FMCFLUSH>>`[src]

`pub fn flush(&mut self) -> FLUSH_W<'_>`[src]

Bit 0 - Flush control

`impl W<u32, Reg<u32, _MCLKIO>>`[src]

`pub fn mclkio(&mut self) -> MCLKIO_W<'_>`[src]

Bit 0 - MCLK control.

`impl W<u32, Reg<u32, _USB1NEEDCLKCTRL>>`[src]

`pub fn ap_hs_dev_needclk(&mut self) -> AP_HS_DEV_NEEDCLK_W<'_>`[src]

Bit 0 - USB1 Device need_clock signal control:

`pub fn pol_hs_dev_needclk(&mut self) -> POL_HS_DEV_NEEDCLK_W<'_>`[src]

Bit 1 - USB1 device need clock polarity for triggering the USB1_NEEDCLK wake-up interrupt:

`pub fn ap_hs_host_needclk(&mut self) -> AP_HS_HOST_NEEDCLK_W<'_>`[src]

Bit 2 - USB1 Host need clock signal control:

`pub fn pol_hs_host_needclk(&mut self) -> POL_HS_HOST_NEEDCLK_W<'_>`[src]

Bit 3 - USB1 host need clock polarity for triggering the USB1_NEEDCLK wake-up interrupt.

`pub fn hs_dev_wakeup_n(&mut self) -> HS_DEV_WAKEUP_N_W<'_>`[src]

Bit 4 - Software override of device controller PHY wake up logic.

`impl W<u32, Reg<u32, _SDIOCLKCTRL>>`[src]

`pub fn cclk_drv_phase(&mut self) -> CCLK_DRV_PHASE_W<'_>`[src]

Bits 0:1 - Programmable delay value by which cclk_in_drv is phase-shifted with regard to cclk_in.

`pub fn cclk_sample_phase(&mut self) -> CCLK_SAMPLE_PHASE_W<'_>`[src]

Bits 2:3 - Programmable delay value by which cclk_in_sample is delayed with regard to cclk_in.

`pub fn phase_active(&mut self) -> PHASE_ACTIVE_W<'_>`[src]

Bit 7 - Enables the delays CCLK_DRV_PHASE and CCLK_SAMPLE_PHASE.

`pub fn cclk_drv_delay(&mut self) -> CCLK_DRV_DELAY_W<'_>`[src]

Bits 16:20 - Programmable delay value by which cclk_in_drv is delayed with regard to cclk_in.

`pub fn cclk_drv_delay_active(&mut self) -> CCLK_DRV_DELAY_ACTIVE_W<'_>`[src]

Bit 23 - Enables drive delay, as controlled by the CCLK_DRV_DELAY field.

`pub fn cclk_sample_delay(&mut self) -> CCLK_SAMPLE_DELAY_W<'_>`[src]

Bits 24:28 - Programmable delay value by which cclk_in_sample is delayed with regard to cclk_in.

`pub fn cclk_sample_delay_active(&mut self) -> CCLK_SAMPLE_DELAY_ACTIVE_W<'_>`[src]

Bit 31 - Enables sample delay, as controlled by the CCLK_SAMPLE_DELAY field.

`impl W<u32, Reg<u32, _PLL1CTRL>>`[src]

`pub fn selr(&mut self) -> SELR_W<'_>`[src]

Bits 0:3 - Bandwidth select R value.

`pub fn seli(&mut self) -> SELI_W<'_>`[src]

Bits 4:9 - Bandwidth select I value.

`pub fn selp(&mut self) -> SELP_W<'_>`[src]

Bits 10:14 - Bandwidth select P value.

`pub fn bypasspll(&mut self) -> BYPASSPLL_W<'_>`[src]

Bit 15 - Bypass PLL input clock is sent directly to the PLL output (default).

`pub fn bypasspostdiv2(&mut self) -> BYPASSPOSTDIV2_W<'_>`[src]

Bit 16 - bypass of the divide-by-2 divider in the post-divider.

`pub fn limupoff(&mut self) -> LIMUPOFF_W<'_>`[src]

Bit 17 - limup_off = 1 in spread spectrum and fractional PLL applications.

`pub fn bwdirect(&mut self) -> BWDIRECT_W<'_>`[src]

Bit 18 - control of the bandwidth of the PLL.

`pub fn bypassprediv(&mut self) -> BYPASSPREDIV_W<'_>`[src]

Bit 19 - bypass of the pre-divider.

`pub fn bypasspostdiv(&mut self) -> BYPASSPOSTDIV_W<'_>`[src]

Bit 20 - bypass of the post-divider.

`pub fn clken(&mut self) -> CLKEN_W<'_>`[src]

Bit 21 - enable the output clock.

`pub fn frmen(&mut self) -> FRMEN_W<'_>`[src]

Bit 22 - 1: free running mode.

`pub fn frmclkstable(&mut self) -> FRMCLKSTABLE_W<'_>`[src]

Bit 23 - free running mode clockstable: Warning: Only make frm_clockstable = 1 after the PLL output frequency is stable.

`pub fn skewen(&mut self) -> SKEWEN_W<'_>`[src]

Bit 24 - Skew mode.

`impl W<u32, Reg<u32, _PLL1NDEC>>`[src]

`pub fn ndiv(&mut self) -> NDIV_W<'_>`[src]

Bits 0:7 - pre-divider divider ratio (N-divider).

`pub fn nreq(&mut self) -> NREQ_W<'_>`[src]

Bit 8 - pre-divider ratio change request.

`impl W<u32, Reg<u32, _PLL1MDEC>>`[src]

`pub fn mdiv(&mut self) -> MDIV_W<'_>`[src]

Bits 0:15 - feedback divider divider ratio (M-divider).

`pub fn mreq(&mut self) -> MREQ_W<'_>`[src]

Bit 16 - feedback ratio change request.

`impl W<u32, Reg<u32, _PLL1PDEC>>`[src]

`pub fn pdiv(&mut self) -> PDIV_W<'_>`[src]

Bits 0:4 - post-divider divider ratio (P-divider)

`pub fn preq(&mut self) -> PREQ_W<'_>`[src]

Bit 5 - feedback ratio change request.

`impl W<u32, Reg<u32, _PLL0CTRL>>`[src]

`pub fn selr(&mut self) -> SELR_W<'_>`[src]

Bits 0:3 - Bandwidth select R value.

`pub fn seli(&mut self) -> SELI_W<'_>`[src]

Bits 4:9 - Bandwidth select I value.

`pub fn selp(&mut self) -> SELP_W<'_>`[src]

Bits 10:14 - Bandwidth select P value.

`pub fn bypasspll(&mut self) -> BYPASSPLL_W<'_>`[src]

Bit 15 - Bypass PLL input clock is sent directly to the PLL output (default).

`pub fn bypasspostdiv2(&mut self) -> BYPASSPOSTDIV2_W<'_>`[src]

Bit 16 - bypass of the divide-by-2 divider in the post-divider.

`pub fn limupoff(&mut self) -> LIMUPOFF_W<'_>`[src]

Bit 17 - limup_off = 1 in spread spectrum and fractional PLL applications.

`pub fn bwdirect(&mut self) -> BWDIRECT_W<'_>`[src]

Bit 18 - Control of the bandwidth of the PLL.

`pub fn bypassprediv(&mut self) -> BYPASSPREDIV_W<'_>`[src]

Bit 19 - bypass of the pre-divider.

`pub fn bypasspostdiv(&mut self) -> BYPASSPOSTDIV_W<'_>`[src]

Bit 20 - bypass of the post-divider.

`pub fn clken(&mut self) -> CLKEN_W<'_>`[src]

Bit 21 - enable the output clock.

`pub fn frmen(&mut self) -> FRMEN_W<'_>`[src]

Bit 22 - free running mode.

`pub fn frmclkstable(&mut self) -> FRMCLKSTABLE_W<'_>`[src]

Bit 23 - free running mode clockstable: Warning: Only make frm_clockstable =1 after the PLL output frequency is stable.

`pub fn skewen(&mut self) -> SKEWEN_W<'_>`[src]

Bit 24 - skew mode.

`impl W<u32, Reg<u32, _PLL0NDEC>>`[src]

`pub fn ndiv(&mut self) -> NDIV_W<'_>`[src]

Bits 0:7 - pre-divider divider ratio (N-divider).

`pub fn nreq(&mut self) -> NREQ_W<'_>`[src]

Bit 8 - pre-divider ratio change request.

`impl W<u32, Reg<u32, _PLL0PDEC>>`[src]

`pub fn pdiv(&mut self) -> PDIV_W<'_>`[src]

Bits 0:4 - post-divider divider ratio (P-divider)

`pub fn preq(&mut self) -> PREQ_W<'_>`[src]

Bit 5 - feedback ratio change request.

`impl W<u32, Reg<u32, _PLL0SSCG0>>`[src]

`pub fn md_lbs(&mut self) -> MD_LBS_W<'_>`[src]

Bits 0:31 - input word of the wrapper bit 31 to 0.

`impl W<u32, Reg<u32, _PLL0SSCG1>>`[src]

`pub fn md_mbs(&mut self) -> MD_MBS_W<'_>`[src]

Bit 0 - input word of the wrapper bit 32.

`pub fn md_req(&mut self) -> MD_REQ_W<'_>`[src]

Bit 1 - md change request.

`pub fn mf(&mut self) -> MF_W<'_>`[src]

Bits 2:4 - programmable modulation frequency fm = Fref/Nss mf[2:0] = 000 => Nss=512 (fm ~ 3.

`pub fn mr(&mut self) -> MR_W<'_>`[src]

Bits 5:7 - programmable frequency modulation depth Dfmodpk-pk = Frefkss/Fcco = kss/(2md[32:25]dec) mr[2:0] = 000 => kss = 0 (no spread spectrum) mr[2:0] = 001 => kss ~ 1 mr[2:0] = 010 => kss ~ 1.

`pub fn mc(&mut self) -> MC_W<'_>`[src]

Bits 8:9 - modulation waveform control Compensation for low pass filtering of the PLL to get a triangular modulation at the output of the PLL, giving a flat frequency spectrum.

`pub fn mdiv_ext(&mut self) -> MDIV_EXT_W<'_>`[src]

Bits 10:25 - to select an external mdiv value.

`pub fn mreq(&mut self) -> MREQ_W<'_>`[src]

Bit 26 - to select an external mreq value.

`pub fn dither(&mut self) -> DITHER_W<'_>`[src]

Bit 27 - dithering between two modulation frequencies in a random way or in a pseudo random way (white noise), in order to decrease the probability that the modulated waveform will occur with the same phase on a particular point on the screen.

`pub fn sel_ext(&mut self) -> SEL_EXT_W<'_>`[src]

Bit 28 - to select mdiv_ext and mreq_ext sel_ext = 0: mdiv ~ md[32:0], mreq = 1 sel_ext = 1 : mdiv = mdiv_ext, mreq = mreq_ext.

`impl W<u32, Reg<u32, _CPUCTRL>>`[src]

`pub fn cpu1clken(&mut self) -> CPU1CLKEN_W<'_>`[src]

Bit 3 - CPU1 clock enable.

`pub fn cpu1rsten(&mut self) -> CPU1RSTEN_W<'_>`[src]

Bit 5 - CPU1 reset.

`impl W<u32, Reg<u32, _CPBOOT>>`[src]

`pub fn cpboot(&mut self) -> CPBOOT_W<'_>`[src]

Bits 0:31 - Coprocessor Boot Address for CPU1.

`impl W<u32, Reg<u32, _CLOCK_CTRL>>`[src]

`pub fn xtal32mhz_freqm_ena(&mut self) -> XTAL32MHZ_FREQM_ENA_W<'_>`[src]

Bit 1 - Enable XTAL32MHz clock for Frequency Measure module.

`pub fn fro1mhz_utick_ena(&mut self) -> FRO1MHZ_UTICK_ENA_W<'_>`[src]

Bit 2 - Enable FRO 1MHz clock for Frequency Measure module and for UTICK.

`pub fn fro12mhz_freqm_ena(&mut self) -> FRO12MHZ_FREQM_ENA_W<'_>`[src]

Bit 3 - Enable FRO 12MHz clock for Frequency Measure module.

`pub fn fro_hf_freqm_ena(&mut self) -> FRO_HF_FREQM_ENA_W<'_>`[src]

Bit 4 - Enable FRO 96MHz clock for Frequency Measure module.

`pub fn clkin_ena(&mut self) -> CLKIN_ENA_W<'_>`[src]

Bit 5 - Enable clock_in clock for clock module.

`pub fn fro1mhz_clk_ena(&mut self) -> FRO1MHZ_CLK_ENA_W<'_>`[src]

Bit 6 - Enable FRO 1MHz clock for clock muxing in clock gen.

`pub fn ana_fro12m_clk_ena(&mut self) -> ANA_FRO12M_CLK_ENA_W<'_>`[src]

Bit 7 - Enable FRO 12MHz clock for analog control of the FRO 192MHz.

`pub fn xo_cal_clk_ena(&mut self) -> XO_CAL_CLK_ENA_W<'_>`[src]

Bit 8 - Enable clock for cristal oscilator calibration.

`pub fn plu_deglitch_clk_ena(&mut self) -> PLU_DEGLITCH_CLK_ENA_W<'_>`[src]

Bit 9 - Enable clocks FRO_1MHz and FRO_12MHz for PLU deglitching.

`impl W<u32, Reg<u32, _COMP_INT_CTRL>>`[src]

`pub fn int_enable(&mut self) -> INT_ENABLE_W<'_>`[src]

Bit 0 - Analog Comparator interrupt enable control:.

`pub fn int_clear(&mut self) -> INT_CLEAR_W<'_>`[src]

Bit 1 - Analog Comparator interrupt clear.

`pub fn int_ctrl(&mut self) -> INT_CTRL_W<'_>`[src]

Bits 2:4 - Comparator interrupt type selector:.

`pub fn int_source(&mut self) -> INT_SOURCE_W<'_>`[src]

Bit 5 - Select which Analog comparator output (filtered our un-filtered) is used for interrupt detection.

`impl W<u32, Reg<u32, _AUTOCLKGATEOVERRIDE>>`[src]

`pub fn rom(&mut self) -> ROM_W<'_>`[src]

Bit 0 - Control automatic clock gating of ROM controller.

`pub fn ramx_ctrl(&mut self) -> RAMX_CTRL_W<'_>`[src]

Bit 1 - Control automatic clock gating of RAMX controller.

`pub fn ram0_ctrl(&mut self) -> RAM0_CTRL_W<'_>`[src]

Bit 2 - Control automatic clock gating of RAM0 controller.

`pub fn ram1_ctrl(&mut self) -> RAM1_CTRL_W<'_>`[src]

Bit 3 - Control automatic clock gating of RAM1 controller.

`pub fn ram2_ctrl(&mut self) -> RAM2_CTRL_W<'_>`[src]

Bit 4 - Control automatic clock gating of RAM2 controller.

`pub fn ram3_ctrl(&mut self) -> RAM3_CTRL_W<'_>`[src]

Bit 5 - Control automatic clock gating of RAM3 controller.

`pub fn ram4_ctrl(&mut self) -> RAM4_CTRL_W<'_>`[src]

Bit 6 - Control automatic clock gating of RAM4 controller.

`pub fn sync0_apb(&mut self) -> SYNC0_APB_W<'_>`[src]

Bit 7 - Control automatic clock gating of synchronous bridge controller 0.

`pub fn sync1_apb(&mut self) -> SYNC1_APB_W<'_>`[src]

Bit 8 - Control automatic clock gating of synchronous bridge controller 1.

`pub fn crcgen(&mut self) -> CRCGEN_W<'_>`[src]

Bit 11 - Control automatic clock gating of CRCGEN controller.

`pub fn sdma0(&mut self) -> SDMA0_W<'_>`[src]

Bit 12 - Control automatic clock gating of DMA0 controller.

`pub fn sdma1(&mut self) -> SDMA1_W<'_>`[src]

Bit 13 - Control automatic clock gating of DMA1 controller.

`pub fn usb0(&mut self) -> USB0_W<'_>`[src]

Bit 14 - Control automatic clock gating of USB controller.

`pub fn syscon(&mut self) -> SYSCON_W<'_>`[src]

Bit 15 - Control automatic clock gating of synchronous system controller registers bank.

`pub fn enableupdate(&mut self) -> ENABLEUPDATE_W<'_>`[src]

Bits 16:31 - The value 0xC0DE must be written for AUTOCLKGATEOVERRIDE registers fields updates to have effect.

`impl W<u32, Reg<u32, _GPIOPSYNC>>`[src]

`pub fn psync(&mut self) -> PSYNC_W<'_>`[src]

Bit 0 - Enable bypass of the first stage of synchonization inside GPIO_INT module.

`impl W<u32, Reg<u32, _DEBUG_LOCK_EN>>`[src]

`pub fn lock_all(&mut self) -> LOCK_ALL_W<'_>`[src]

Bits 0:3 - Control write access to CODESECURITYPROTTEST, CODESECURITYPROTCPU0, CODESECURITYPROTCPU1, CPU0_DEBUG_FEATURES, CPU1_DEBUG_FEATURES and DBG_AUTH_SCRATCH registers.

`impl W<u32, Reg<u32, _DEBUG_FEATURES>>`[src]

`pub fn cpu0_dbgen(&mut self) -> CPU0_DBGEN_W<'_>`[src]

Bits 0:1 - CPU0 Invasive debug control:.

`pub fn cpu0_niden(&mut self) -> CPU0_NIDEN_W<'_>`[src]

Bits 2:3 - CPU0 Non Invasive debug control:.

`pub fn cpu0_spiden(&mut self) -> CPU0_SPIDEN_W<'_>`[src]

Bits 4:5 - CPU0 Secure Invasive debug control:.

`pub fn cpu0_spniden(&mut self) -> CPU0_SPNIDEN_W<'_>`[src]

Bits 6:7 - CPU0 Secure Non Invasive debug control:.

`pub fn cpu1_dbgen(&mut self) -> CPU1_DBGEN_W<'_>`[src]

Bits 8:9 - CPU1 Invasive debug control:.

`pub fn cpu1_niden(&mut self) -> CPU1_NIDEN_W<'_>`[src]

Bits 10:11 - CPU1 Non Invasive debug control:.

`impl W<u32, Reg<u32, _DEBUG_FEATURES_DP>>`[src]

`pub fn cpu0_dbgen(&mut self) -> CPU0_DBGEN_W<'_>`[src]

Bits 0:1 - CPU0 (CPU0) Invasive debug control:.

`pub fn cpu0_niden(&mut self) -> CPU0_NIDEN_W<'_>`[src]

Bits 2:3 - CPU0 Non Invasive debug control:.

`pub fn cpu0_spiden(&mut self) -> CPU0_SPIDEN_W<'_>`[src]

Bits 4:5 - CPU0 Secure Invasive debug control:.

`pub fn cpu0_spniden(&mut self) -> CPU0_SPNIDEN_W<'_>`[src]

Bits 6:7 - CPU0 Secure Non Invasive debug control:.

`pub fn cpu1_dbgen(&mut self) -> CPU1_DBGEN_W<'_>`[src]

Bits 8:9 - CPU1 Invasive debug control:.

`pub fn cpu1_niden(&mut self) -> CPU1_NIDEN_W<'_>`[src]

Bits 10:11 - CPU1 Non Invasive debug control:.

`impl W<u32, Reg<u32, _KEY_BLOCK>>`[src]

`pub fn key_block(&mut self) -> KEY_BLOCK_W<'_>`[src]

Bits 0:31 - Write a value to block quiddikey/PUF all index.

`impl W<u32, Reg<u32, _DEBUG_AUTH_BEACON>>`[src]

`pub fn beacon(&mut self) -> BEACON_W<'_>`[src]

Bits 0:31 - Set by the debug authentication code in ROM to pass the debug beacons (Credential Beacon and Authentication Beacon) to application code.

`impl W<u32, Reg<u32, _CPUCFG>>`[src]

`pub fn cpu1enable(&mut self) -> CPU1ENABLE_W<'_>`[src]

Bit 2 - Enable CPU1.

`impl W<u32, Reg<u32, _PIO0_0>>`[src]

`pub fn func(&mut self) -> FUNC_W<'_>`[src]

`pub fn asw(&mut self) -> ASW_W<'_>`[src]

Bit 10 - Analog switch input control.

`impl W<u32, Reg<u32, _PIO0_10>>`[src]

`pub fn func(&mut self) -> FUNC_W<'_>`[src]

Bits 0:3 - Selects pin function.

`pub fn mode(&mut self) -> MODE_W<'_>`[src]

Bits 4:5 - Selects function mode (on-chip pull-up/pull-down resistor control).

`pub fn slew(&mut self) -> SLEW_W<'_>`[src]

Bit 6 - Driver slew rate.

`pub fn invert(&mut self) -> INVERT_W<'_>`[src]

Bit 7 - Input polarity.

`pub fn digimode(&mut self) -> DIGIMODE_W<'_>`[src]

Bit 8 - Select Digital mode.

`pub fn od(&mut self) -> OD_W<'_>`[src]

Bit 9 - Controls open-drain mode.

`pub fn asw(&mut self) -> ASW_W<'_>`[src]

Bit 10 - Analog switch input control.

`impl W<u32, Reg<u32, _PIO0_11>>`[src]

`pub fn func(&mut self) -> FUNC_W<'_>`[src]

Bits 0:3 - Selects pin function.

`pub fn mode(&mut self) -> MODE_W<'_>`[src]

Bits 4:5 - Selects function mode (on-chip pull-up/pull-down resistor control).

`pub fn slew(&mut self) -> SLEW_W<'_>`[src]

Bit 6 - Driver slew rate.

`pub fn invert(&mut self) -> INVERT_W<'_>`[src]

Bit 7 - Input polarity.

`pub fn digimode(&mut self) -> DIGIMODE_W<'_>`[src]

Bit 8 - Select Digital mode.

`pub fn od(&mut self) -> OD_W<'_>`[src]

Bit 9 - Controls open-drain mode.

`pub fn asw(&mut self) -> ASW_W<'_>`[src]

Bit 10 - Analog switch input control.

`impl W<u32, Reg<u32, _PIO0_12>>`[src]

`pub fn func(&mut self) -> FUNC_W<'_>`[src]

Bits 0:3 - Selects pin function.

`pub fn mode(&mut self) -> MODE_W<'_>`[src]

Bits 4:5 - Selects function mode (on-chip pull-up/pull-down resistor control).

`pub fn slew(&mut self) -> SLEW_W<'_>`[src]

Bit 6 - Driver slew rate.

`pub fn invert(&mut self) -> INVERT_W<'_>`[src]

Bit 7 - Input polarity.

`pub fn digimode(&mut self) -> DIGIMODE_W<'_>`[src]

Bit 8 - Select Digital mode.

`pub fn od(&mut self) -> OD_W<'_>`[src]

Bit 9 - Controls open-drain mode.

`pub fn asw(&mut self) -> ASW_W<'_>`[src]

Bit 10 - Analog switch input control.

`impl W<u32, Reg<u32, _PIO0_13>>`[src]

`pub fn func(&mut self) -> FUNC_W<'_>`[src]

Bits 0:3 - Selects pin function.

`pub fn mode(&mut self) -> MODE_W<'_>`[src]

Bits 4:5 - Selects function mode (on-chip pull-up/pull-down resistor control).

`pub fn slew(&mut self) -> SLEW_W<'_>`[src]

Bit 6 - Driver slew rate.

`pub fn invert(&mut self) -> INVERT_W<'_>`[src]

Bit 7 - Input polarity.

`pub fn digimode(&mut self) -> DIGIMODE_W<'_>`[src]

Bit 8 - Select Digital mode.

`pub fn od(&mut self) -> OD_W<'_>`[src]

Bit 9 - Controls open-drain mode in standard GPIO mode (EGP = 1). This bit has no effect in I2C mode (EGP=0).

`pub fn ssel(&mut self) -> SSEL_W<'_>`[src]

Bit 11 - Supply Selection bit.

`pub fn filteroff(&mut self) -> FILTEROFF_W<'_>`[src]

Bit 12 - Controls input glitch filter.

`pub fn ecs(&mut self) -> ECS_W<'_>`[src]

Bit 13 - Pull-up current source enable in I2C mode.

`pub fn egp(&mut self) -> EGP_W<'_>`[src]

Bit 14 - Switch between GPIO mode and I2C mode.

`pub fn i2cfilter(&mut self) -> I2CFILTER_W<'_>`[src]

Bit 15 - Configures I2C features for standard mode, fast mode, and Fast Mode Plus operation and High-Speed mode operation.

`impl W<u32, Reg<u32, _PIO0_14>>`[src]

`pub fn func(&mut self) -> FUNC_W<'_>`[src]

Bits 0:3 - Selects pin function.

`pub fn mode(&mut self) -> MODE_W<'_>`[src]

Bits 4:5 - Selects function mode (on-chip pull-up/pull-down resistor control).

`pub fn slew(&mut self) -> SLEW_W<'_>`[src]

Bit 6 - Driver slew rate.

`pub fn invert(&mut self) -> INVERT_W<'_>`[src]

Bit 7 - Input polarity.

`pub fn digimode(&mut self) -> DIGIMODE_W<'_>`[src]

Bit 8 - Select Digital mode.

`pub fn od(&mut self) -> OD_W<'_>`[src]

Bit 9 - Controls open-drain mode in standard GPIO mode (EGP = 1). This bit has no effect in I2C mode (EGP=0).

`pub fn ssel(&mut self) -> SSEL_W<'_>`[src]

Bit 11 - Supply Selection bit.

`pub fn filteroff(&mut self) -> FILTEROFF_W<'_>`[src]

Bit 12 - Controls input glitch filter.

`pub fn ecs(&mut self) -> ECS_W<'_>`[src]

Bit 13 - Pull-up current source enable in I2C mode.

`pub fn egp(&mut self) -> EGP_W<'_>`[src]

Bit 14 - Switch between GPIO mode and I2C mode.

`pub fn i2cfilter(&mut self) -> I2CFILTER_W<'_>`[src]

Bit 15 - Configures I2C features for standard mode, fast mode, and Fast Mode Plus operation and High-Speed mode operation.

`impl W<u32, Reg<u32, _PIO0_15>>`[src]

`pub fn func(&mut self) -> FUNC_W<'_>`[src]

Bits 0:3 - Selects pin function.

`pub fn mode(&mut self) -> MODE_W<'_>`[src]

Bits 4:5 - Selects function mode (on-chip pull-up/pull-down resistor control).

`pub fn slew(&mut self) -> SLEW_W<'_>`[src]

Bit 6 - Driver slew rate.

`pub fn invert(&mut self) -> INVERT_W<'_>`[src]

Bit 7 - Input polarity.

`pub fn digimode(&mut self) -> DIGIMODE_W<'_>`[src]

Bit 8 - Select Digital mode.

`pub fn od(&mut self) -> OD_W<'_>`[src]

Bit 9 - Controls open-drain mode.

`pub fn asw(&mut self) -> ASW_W<'_>`[src]

Bit 10 - Analog switch input control.

`impl W<u32, Reg<u32, _PIO0_16>>`[src]

`pub fn func(&mut self) -> FUNC_W<'_>`[src]

`pub fn od(&mut self) -> OD_W<'_>`[src]

Bit 9 - Controls open-drain mode.

`pub fn asw(&mut self) -> ASW_W<'_>`[src]

Bit 10 - Analog switch input control.

`impl W<u32, Reg<u32, _PIO1_0>>`[src]

`pub fn func(&mut self) -> FUNC_W<'_>`[src]

`pub fn asw(&mut self) -> ASW_W<'_>`[src]

Bit 10 - Analog switch input control.

`impl W<u32, Reg<u32, _PIO1_9>>`[src]

`pub fn func(&mut self) -> FUNC_W<'_>`[src]

Bits 0:31 - Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt.

`impl W<u32, Reg<u32, _PORT_ENA>>`[src]

`pub fn ena(&mut self) -> ENA_W<'_>`[src]

Bits 0:31 - Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt.

`impl W<u32, Reg<u32, _ISEL>>`[src]

`pub fn pmode(&mut self) -> PMODE_W<'_>`[src]

Bits 0:7 - Selects the interrupt mode for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Edge sensitive 1 = Level sensitive

`impl W<u32, Reg<u32, _IENR>>`[src]

`pub fn enrl(&mut self) -> ENRL_W<'_>`[src]

Bits 0:7 - Enables the rising edge or level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable rising edge or level interrupt. 1 = Enable rising edge or level interrupt.

`impl W<u32, Reg<u32, _SIENR>>`[src]

`pub fn setenrl(&mut self) -> SETENRL_W<'_>`[src]

Bits 0:7 - Ones written to this address set bits in the IENR, thus enabling interrupts. Bit n sets bit n in the IENR register. 0 = No operation. 1 = Enable rising edge or level interrupt.

`impl W<u32, Reg<u32, _CIENR>>`[src]

`pub fn cenrl(&mut self) -> CENRL_W<'_>`[src]

Bits 0:7 - Ones written to this address clear bits in the IENR, thus disabling the interrupts. Bit n clears bit n in the IENR register. 0 = No operation. 1 = Disable rising edge or level interrupt.

`impl W<u32, Reg<u32, _IENF>>`[src]

`pub fn enaf(&mut self) -> ENAF_W<'_>`[src]

Bits 0:7 - Enables the falling edge or configures the active level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable falling edge interrupt or set active interrupt level LOW. 1 = Enable falling edge interrupt enabled or set active interrupt level HIGH.

`impl W<u32, Reg<u32, _SIENF>>`[src]

`pub fn setenaf(&mut self) -> SETENAF_W<'_>`[src]

Bits 0:7 - Ones written to this address set bits in the IENF, thus enabling interrupts. Bit n sets bit n in the IENF register. 0 = No operation. 1 = Select HIGH-active interrupt or enable falling edge interrupt.

`impl W<u32, Reg<u32, _CIENF>>`[src]

`pub fn cenaf(&mut self) -> CENAF_W<'_>`[src]

Bits 0:7 - Ones written to this address clears bits in the IENF, thus disabling interrupts. Bit n clears bit n in the IENF register. 0 = No operation. 1 = LOW-active interrupt selected or falling edge interrupt disabled.

`impl W<u32, Reg<u32, _RISE>>`[src]

`pub fn rdet(&mut self) -> RDET_W<'_>`[src]

Bits 0:7 - Rising edge detect. Bit n detects the rising edge of the pin selected in PINTSELn. Read 0: No rising edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a rising edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear rising edge detection for this pin.

`impl W<u32, Reg<u32, _FALL>>`[src]

`pub fn fdet(&mut self) -> FDET_W<'_>`[src]

Bits 0:7 - Falling edge detect. Bit n detects the falling edge of the pin selected in PINTSELn. Read 0: No falling edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a falling edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear falling edge detection for this pin.

`impl W<u32, Reg<u32, _IST>>`[src]

`pub fn pstat(&mut self) -> PSTAT_W<'_>`[src]

Bits 0:7 - Pin interrupt status. Bit n returns the status, clears the edge interrupt, or inverts the active level of the pin selected in PINTSELn. Read 0: interrupt is not being requested for this interrupt pin. Write 0: no operation. Read 1: interrupt is being requested for this interrupt pin. Write 1 (edge-sensitive): clear rising- and falling-edge detection for this pin. Write 1 (level-sensitive): switch the active level for this pin (in the IENF register).

`impl W<u32, Reg<u32, _PMCTRL>>`[src]

`pub fn sel_pmatch(&mut self) -> SEL_PMATCH_W<'_>`[src]

Bit 0 - Specifies whether the 8 pin interrupts are controlled by the pin interrupt function or by the pattern match function.

`pub fn ena_rxev(&mut self) -> ENA_RXEV_W<'_>`[src]

Bit 1 - Enables the RXEV output to the CPU and/or to a GPIO output when the specified boolean expression evaluates to true.

`pub fn pmat(&mut self) -> PMAT_W<'_>`[src]

Bits 24:31 - This field displays the current state of pattern matches. A 1 in any bit of this field indicates that the corresponding product term is matched by the current state of the appropriate inputs.

`impl W<u32, Reg<u32, _PMSRC>>`[src]

`pub fn src0(&mut self) -> SRC0_W<'_>`[src]

Bits 8:10 - Selects the input source for bit slice 0

`pub fn src1(&mut self) -> SRC1_W<'_>`[src]

Bits 11:13 - Selects the input source for bit slice 1

`pub fn src2(&mut self) -> SRC2_W<'_>`[src]

Bits 14:16 - Selects the input source for bit slice 2

`pub fn src3(&mut self) -> SRC3_W<'_>`[src]

Bits 17:19 - Selects the input source for bit slice 3

`pub fn src4(&mut self) -> SRC4_W<'_>`[src]

Bits 20:22 - Selects the input source for bit slice 4

`pub fn src5(&mut self) -> SRC5_W<'_>`[src]

Bits 23:25 - Selects the input source for bit slice 5

`pub fn src6(&mut self) -> SRC6_W<'_>`[src]

Bits 26:28 - Selects the input source for bit slice 6

`pub fn src7(&mut self) -> SRC7_W<'_>`[src]

Bits 29:31 - Selects the input source for bit slice 7

`impl W<u32, Reg<u32, _PMCFG>>`[src]

`pub fn prod_endpts0(&mut self) -> PROD_ENDPTS0_W<'_>`[src]

Bit 0 - Determines whether slice 0 is an endpoint.

`pub fn prod_endpts1(&mut self) -> PROD_ENDPTS1_W<'_>`[src]

Bit 1 - Determines whether slice 1 is an endpoint.

`pub fn prod_endpts2(&mut self) -> PROD_ENDPTS2_W<'_>`[src]

Bit 2 - Determines whether slice 2 is an endpoint.

`pub fn prod_endpts3(&mut self) -> PROD_ENDPTS3_W<'_>`[src]

Bit 3 - Determines whether slice 3 is an endpoint.

`pub fn prod_endpts4(&mut self) -> PROD_ENDPTS4_W<'_>`[src]

Bit 4 - Determines whether slice 4 is an endpoint.

`pub fn prod_endpts5(&mut self) -> PROD_ENDPTS5_W<'_>`[src]

Bit 5 - Determines whether slice 5 is an endpoint.

`pub fn prod_endpts6(&mut self) -> PROD_ENDPTS6_W<'_>`[src]

Bit 6 - Determines whether slice 6 is an endpoint.

`pub fn cfg0(&mut self) -> CFG0_W<'_>`[src]

Bits 8:10 - Specifies the match contribution condition for bit slice 0.

`pub fn cfg1(&mut self) -> CFG1_W<'_>`[src]

Bits 11:13 - Specifies the match contribution condition for bit slice 1.

`pub fn cfg2(&mut self) -> CFG2_W<'_>`[src]

Bits 14:16 - Specifies the match contribution condition for bit slice 2.

`pub fn cfg3(&mut self) -> CFG3_W<'_>`[src]

Bits 17:19 - Specifies the match contribution condition for bit slice 3.

`pub fn cfg4(&mut self) -> CFG4_W<'_>`[src]

Bits 20:22 - Specifies the match contribution condition for bit slice 4.

`pub fn cfg5(&mut self) -> CFG5_W<'_>`[src]

Bits 23:25 - Specifies the match contribution condition for bit slice 5.

`pub fn cfg6(&mut self) -> CFG6_W<'_>`[src]

Bits 26:28 - Specifies the match contribution condition for bit slice 6.

`pub fn cfg7(&mut self) -> CFG7_W<'_>`[src]

Bits 29:31 - Specifies the match contribution condition for bit slice 7.

`impl W<u32, Reg<u32, _SCT0_INMUX>>`[src]

`pub fn inp_n(&mut self) -> INP_N_W<'_>`[src]

Bits 0:4 - Input number to SCT0 inputs 0 to 6.

`impl W<u32, Reg<u32, _TIMER0CAPTSEL>>`[src]

`pub fn captsel(&mut self) -> CAPTSEL_W<'_>`[src]

Bits 0:4 - Input number to TIMER%s capture inputs 0 to 4

`impl W<u32, Reg<u32, _TIMER1CAPTSEL>>`[src]

`pub fn captsel(&mut self) -> CAPTSEL_W<'_>`[src]

Bits 0:4 - Input number to TIMER%s capture inputs 0 to 4

`impl W<u32, Reg<u32, _TIMER2CAPTSEL>>`[src]

`pub fn captsel(&mut self) -> CAPTSEL_W<'_>`[src]

Bits 0:4 - Input number to TIMER%s capture inputs 0 to 4

`impl W<u32, Reg<u32, _PINTSEL>>`[src]

`pub fn intpin(&mut self) -> INTPIN_W<'_>`[src]

Bits 0:6 - Pin number select for pin interrupt or pattern match engine input. For PIOx_y: INTPIN = (x * 32) + y. PIO0_0 to PIO1_31 correspond to numbers 0 to 63.

`impl W<u32, Reg<u32, _DMA0_ITRIG_INMUX>>`[src]

`pub fn inp(&mut self) -> INP_W<'_>`[src]

Bits 0:4 - Trigger input number (decimal value) for DMA channel n (n = 0 to 22).

`impl W<u32, Reg<u32, _DMA0_OTRIG_INMUX>>`[src]

`pub fn inp(&mut self) -> INP_W<'_>`[src]

Bits 0:4 - DMA trigger output number (decimal value) for DMA channel n (n = 0 to 22).

`impl W<u32, Reg<u32, _FREQMEAS_REF>>`[src]

`pub fn clkin(&mut self) -> CLKIN_W<'_>`[src]

Bits 0:4 - Clock source number (decimal value) for frequency measure function target clock: 0 = CLK_IN 1 = FRO 12 MHz oscillator 2 = Watchdog oscillator 3 = 32 kHz RTC oscillator 4 = Main clock (see Section 4.5.23) 5 = PIO0_4 6 = PIO0_20 7 = PIO0_24 8 = PIO1_4

`impl W<u32, Reg<u32, _FREQMEAS_TARGET>>`[src]

`pub fn clkin(&mut self) -> CLKIN_W<'_>`[src]

Bits 0:4 - Clock source number (decimal value) for frequency measure function target clock: 0 = CLK_IN 1 = FRO 12 MHz oscillator 2 = Watchdog oscillator 3 = 32 kHz RTC oscillator 4 = Main clock (see Section 4.5.23) 5 = PIO0_4 6 = PIO0_20 7 = PIO0_24 8 = PIO1_4

`impl W<u32, Reg<u32, _TIMER3CAPTSEL>>`[src]

`pub fn captsel(&mut self) -> CAPTSEL_W<'_>`[src]

Bits 0:4 - Input number to TIMER%s capture inputs 0 to 4

`impl W<u32, Reg<u32, _TIMER4CAPTSEL>>`[src]

`pub fn captsel(&mut self) -> CAPTSEL_W<'_>`[src]

Bits 0:4 - Input number to TIMER%s capture inputs 0 to 4

`impl W<u32, Reg<u32, _PINTSECSEL>>`[src]

`pub fn intpin(&mut self) -> INTPIN_W<'_>`[src]

Bits 0:5 - Pin number select for pin interrupt secure or pattern match engine input. For PIO0_x: INTPIN = x. PIO0_0 to PIO0_31 correspond to numbers 0 to 31.

`impl W<u32, Reg<u32, _DMA1_ITRIG_INMUX>>`[src]

`pub fn inp(&mut self) -> INP_W<'_>`[src]

Bits 0:3 - Trigger input number (decimal value) for DMA channel n (n = 0 to 9).

`impl W<u32, Reg<u32, _DMA1_OTRIG_INMUX>>`[src]

`pub fn inp(&mut self) -> INP_W<'_>`[src]

Bits 0:3 - DMA trigger output number (decimal value) for DMA channel n (n = 0 to 9).

`impl W<u32, Reg<u32, _DMA0_REQ_ENA>>`[src]

`pub fn req_ena(&mut self) -> REQ_ENA_W<'_>`[src]

Bits 0:22 - Controls the 23 request inputs of DMA0. If bit i is '1' the DMA request input #i is enabled.

`impl W<u32, Reg<u32, _DMA0_REQ_ENA_SET>>`[src]

`pub fn set(&mut self) -> SET_W<'_>`[src]

Bits 0:22 - Write : If bit #i = 1, bit #i in DMA0_REQ_ENA register is set to 1; if bit #i = 0 , no change in DMA0_REQ_ENA register

`impl W<u32, Reg<u32, _DMA0_REQ_ENA_CLR>>`[src]

`pub fn clr(&mut self) -> CLR_W<'_>`[src]

Bits 0:22 - Write : If bit #i = 1, bit #i in DMA0_REQ_ENA register is reset to 0; if bit #i = 0 , no change in DMA0_REQ_ENA register

`impl W<u32, Reg<u32, _DMA1_REQ_ENA>>`[src]

`pub fn req_ena(&mut self) -> REQ_ENA_W<'_>`[src]

Bits 0:9 - Controls the 10 request inputs of DMA1. If bit i is '1' the DMA request input #i is enabled.

`impl W<u32, Reg<u32, _DMA1_REQ_ENA_SET>>`[src]

`pub fn set(&mut self) -> SET_W<'_>`[src]

Bits 0:9 - Write : If bit #i = 1, bit #i in DMA1_REQ_ENA register is set to 1; if bit #i = 0 , no change in DMA1_REQ_ENA register

`impl W<u32, Reg<u32, _DMA1_REQ_ENA_CLR>>`[src]

`pub fn clr(&mut self) -> CLR_W<'_>`[src]

Bits 0:9 - Write : If bit #i = 1, bit #i in DMA1_REQ_ENA register is reset to 0; if bit #i = 0 , no change in DMA1_REQ_ENA register

`impl W<u32, Reg<u32, _DMA0_ITRIG_ENA>>`[src]

`pub fn itrig_ena(&mut self) -> ITRIG_ENA_W<'_>`[src]

Bits 0:21 - Controls the 22 trigger inputs of DMA0. If bit i is '1' the DMA trigger input #i is enabled.

`impl W<u32, Reg<u32, _DMA0_ITRIG_ENA_SET>>`[src]

`pub fn set(&mut self) -> SET_W<'_>`[src]

Bits 0:21 - Write : If bit #i = 1, bit #i in DMA0_ITRIG_ENA register is set to 1; if bit #i = 0 , no change in DMA0_ITRIG_ENA register

`impl W<u32, Reg<u32, _DMA0_ITRIG_ENA_CLR>>`[src]

`pub fn clr(&mut self) -> CLR_W<'_>`[src]

Bits 0:21 - Write : If bit #i = 1, bit #i in DMA0_ITRIG_ENA register is reset to 0; if bit #i = 0 , no change in DMA0_ITRIG_ENA register

`impl W<u32, Reg<u32, _DMA1_ITRIG_ENA>>`[src]

`pub fn itrig_ena(&mut self) -> ITRIG_ENA_W<'_>`[src]

Bits 0:14 - Controls the 15 trigger inputs of DMA1. If bit i is '1' the DMA trigger input #i is enabled.

`impl W<u32, Reg<u32, _DMA1_ITRIG_ENA_SET>>`[src]

`pub fn set(&mut self) -> SET_W<'_>`[src]

Bits 0:14 - Write : If bit #i = 1, bit #i in DMA1_ITRIG_ENA register is set to 1; if bit #i = 0 , no change in DMA1_ITRIG_ENA register

`impl W<u32, Reg<u32, _DMA1_ITRIG_ENA_CLR>>`[src]

`pub fn clr(&mut self) -> CLR_W<'_>`[src]

Bits 0:14 - Write : If bit #i = 1, bit #i in DMA1_ITRIG_ENA register is reset to 0; if bit #i = 0 , no change in DMA1_ITRIG_ENA register

`impl W<u32, Reg<u32, _IR>>`[src]

`pub fn mr0int(&mut self) -> MR0INT_W<'_>`[src]

Bit 0 - Interrupt flag for match channel 0.

`pub fn mr1int(&mut self) -> MR1INT_W<'_>`[src]

Bit 1 - Interrupt flag for match channel 1.

`pub fn mr2int(&mut self) -> MR2INT_W<'_>`[src]

Bit 2 - Interrupt flag for match channel 2.

`pub fn mr3int(&mut self) -> MR3INT_W<'_>`[src]

Bit 3 - Interrupt flag for match channel 3.

`pub fn cr0int(&mut self) -> CR0INT_W<'_>`[src]

Bit 4 - Interrupt flag for capture channel 0 event.

`pub fn cr1int(&mut self) -> CR1INT_W<'_>`[src]

Bit 5 - Interrupt flag for capture channel 1 event.

`pub fn cr2int(&mut self) -> CR2INT_W<'_>`[src]

Bit 6 - Interrupt flag for capture channel 2 event.

`pub fn cr3int(&mut self) -> CR3INT_W<'_>`[src]

Bit 7 - Interrupt flag for capture channel 3 event.

`impl W<u32, Reg<u32, _TCR>>`[src]

`pub fn cen(&mut self) -> CEN_W<'_>`[src]

Bit 0 - Counter enable.

`pub fn crst(&mut self) -> CRST_W<'_>`[src]

Bit 1 - Counter reset.

`impl W<u32, Reg<u32, _TC>>`[src]

`pub fn tcval(&mut self) -> TCVAL_W<'_>`[src]

Bits 0:31 - Timer counter value.

`impl W<u32, Reg<u32, _PR>>`[src]

`pub fn prval(&mut self) -> PRVAL_W<'_>`[src]

Bits 0:31 - Prescale counter value.

`impl W<u32, Reg<u32, _PC>>`[src]

`pub fn pcval(&mut self) -> PCVAL_W<'_>`[src]

Bits 0:31 - Prescale counter value.

`impl W<u32, Reg<u32, _MCR>>`[src]

`pub fn mr0i(&mut self) -> MR0I_W<'_>`[src]

Bit 0 - Interrupt on MR0: an interrupt is generated when MR0 matches the value in the TC.

`pub fn mr0r(&mut self) -> MR0R_W<'_>`[src]

Bit 1 - Reset on MR0: the TC will be reset if MR0 matches it.

`pub fn mr0s(&mut self) -> MR0S_W<'_>`[src]

Bit 2 - Stop on MR0: the TC and PC will be stopped and TCR[0] will be set to 0 if MR0 matches the TC.

`pub fn mr1i(&mut self) -> MR1I_W<'_>`[src]

Bit 3 - Interrupt on MR1: an interrupt is generated when MR1 matches the value in the TC.

`pub fn mr1r(&mut self) -> MR1R_W<'_>`[src]

Bit 4 - Reset on MR1: the TC will be reset if MR1 matches it.

`pub fn mr1s(&mut self) -> MR1S_W<'_>`[src]

Bit 5 - Stop on MR1: the TC and PC will be stopped and TCR[0] will be set to 0 if MR1 matches the TC.

`pub fn mr2i(&mut self) -> MR2I_W<'_>`[src]

Bit 6 - Interrupt on MR2: an interrupt is generated when MR2 matches the value in the TC.

`pub fn mr2r(&mut self) -> MR2R_W<'_>`[src]

Bit 7 - Reset on MR2: the TC will be reset if MR2 matches it.

`pub fn mr2s(&mut self) -> MR2S_W<'_>`[src]

Bit 8 - Stop on MR2: the TC and PC will be stopped and TCR[0] will be set to 0 if MR2 matches the TC.

`pub fn mr3i(&mut self) -> MR3I_W<'_>`[src]

Bit 9 - Interrupt on MR3: an interrupt is generated when MR3 matches the value in the TC.

`pub fn mr3r(&mut self) -> MR3R_W<'_>`[src]

Bit 10 - Reset on MR3: the TC will be reset if MR3 matches it.

`pub fn mr3s(&mut self) -> MR3S_W<'_>`[src]

Bit 11 - Stop on MR3: the TC and PC will be stopped and TCR[0] will be set to 0 if MR3 matches the TC.

`pub fn mr0rl(&mut self) -> MR0RL_W<'_>`[src]

Bit 24 - Reload MR0 with the contents of the Match 0 Shadow Register when the TC is reset to zero (either via a match event or a write to bit 1 of the TCR).

`pub fn mr1rl(&mut self) -> MR1RL_W<'_>`[src]

Bit 25 - Reload MR1 with the contents of the Match 1 Shadow Register when the TC is reset to zero (either via a match event or a write to bit 1 of the TCR).

`pub fn mr2rl(&mut self) -> MR2RL_W<'_>`[src]

Bit 26 - Reload MR2 with the contents of the Match 2 Shadow Register when the TC is reset to zero (either via a match event or a write to bit 1 of the TCR).

`pub fn mr3rl(&mut self) -> MR3RL_W<'_>`[src]

Bit 27 - Reload MR3 with the contents of the Match 3 Shadow Register when the TC is reset to zero (either via a match event or a write to bit 1 of the TCR).

`impl W<u32, Reg<u32, _MR>>`[src]

`pub fn match_(&mut self) -> MATCH_W<'_>`[src]

Bits 0:31 - Timer counter match value.

`impl W<u32, Reg<u32, _CCR>>`[src]

`pub fn cap0re(&mut self) -> CAP0RE_W<'_>`[src]

Bit 0 - Rising edge of capture channel 0: a sequence of 0 then 1 causes CR0 to be loaded with the contents of TC. 0 = disabled. 1 = enabled.

`pub fn cap0fe(&mut self) -> CAP0FE_W<'_>`[src]

Bit 1 - Falling edge of capture channel 0: a sequence of 1 then 0 causes CR0 to be loaded with the contents of TC. 0 = disabled. 1 = enabled.

`pub fn cap0i(&mut self) -> CAP0I_W<'_>`[src]

Bit 2 - Generate interrupt on channel 0 capture event: a CR0 load generates an interrupt.

`pub fn cap1re(&mut self) -> CAP1RE_W<'_>`[src]

Bit 3 - Rising edge of capture channel 1: a sequence of 0 then 1 causes CR1 to be loaded with the contents of TC. 0 = disabled. 1 = enabled.

`pub fn cap1fe(&mut self) -> CAP1FE_W<'_>`[src]

Bit 4 - Falling edge of capture channel 1: a sequence of 1 then 0 causes CR1 to be loaded with the contents of TC. 0 = disabled. 1 = enabled.

`pub fn cap1i(&mut self) -> CAP1I_W<'_>`[src]

Bit 5 - Generate interrupt on channel 1 capture event: a CR1 load generates an interrupt.

`pub fn cap2re(&mut self) -> CAP2RE_W<'_>`[src]

Bit 6 - Rising edge of capture channel 2: a sequence of 0 then 1 causes CR2 to be loaded with the contents of TC. 0 = disabled. 1 = enabled.

`pub fn cap2fe(&mut self) -> CAP2FE_W<'_>`[src]

Bit 7 - Falling edge of capture channel 2: a sequence of 1 then 0 causes CR2 to be loaded with the contents of TC. 0 = disabled. 1 = enabled.

`pub fn cap2i(&mut self) -> CAP2I_W<'_>`[src]

Bit 8 - Generate interrupt on channel 2 capture event: a CR2 load generates an interrupt.

`pub fn cap3re(&mut self) -> CAP3RE_W<'_>`[src]

Bit 9 - Rising edge of capture channel 3: a sequence of 0 then 1 causes CR3 to be loaded with the contents of TC. 0 = disabled. 1 = enabled.

`pub fn cap3fe(&mut self) -> CAP3FE_W<'_>`[src]

Bit 10 - Falling edge of capture channel 3: a sequence of 1 then 0 causes CR3 to be loaded with the contents of TC. 0 = disabled. 1 = enabled.

`pub fn cap3i(&mut self) -> CAP3I_W<'_>`[src]

Bit 11 - Generate interrupt on channel 3 capture event: a CR3 load generates an interrupt.

`impl W<u32, Reg<u32, _EMR>>`[src]

`pub fn em0(&mut self) -> EM0_W<'_>`[src]

Bit 0 - External Match 0. This bit reflects the state of output MAT0, whether or not this output is connected to a pin. When a match occurs between the TC and MR0, this bit can either toggle, go LOW, go HIGH, or do nothing, as selected by EMR[5:4]. This bit is driven to the MAT pins if the match function is selected via IOCON. 0 = LOW. 1 = HIGH.

`pub fn em1(&mut self) -> EM1_W<'_>`[src]

Bit 1 - External Match 1. This bit reflects the state of output MAT1, whether or not this output is connected to a pin. When a match occurs between the TC and MR1, this bit can either toggle, go LOW, go HIGH, or do nothing, as selected by EMR[7:6]. This bit is driven to the MAT pins if the match function is selected via IOCON. 0 = LOW. 1 = HIGH.

`pub fn em2(&mut self) -> EM2_W<'_>`[src]

Bit 2 - External Match 2. This bit reflects the state of output MAT2, whether or not this output is connected to a pin. When a match occurs between the TC and MR2, this bit can either toggle, go LOW, go HIGH, or do nothing, as selected by EMR[9:8]. This bit is driven to the MAT pins if the match function is selected via IOCON. 0 = LOW. 1 = HIGH.

`pub fn em3(&mut self) -> EM3_W<'_>`[src]

Bit 3 - External Match 3. This bit reflects the state of output MAT3, whether or not this output is connected to a pin. When a match occurs between the TC and MR3, this bit can either toggle, go LOW, go HIGH, or do nothing, as selected by MR[11:10]. This bit is driven to the MAT pins if the match function is selected via IOCON. 0 = LOW. 1 = HIGH.

`pub fn emc0(&mut self) -> EMC0_W<'_>`[src]

Bits 4:5 - External Match Control 0. Determines the functionality of External Match 0.

`pub fn emc1(&mut self) -> EMC1_W<'_>`[src]

Bits 6:7 - External Match Control 1. Determines the functionality of External Match 1.

`pub fn emc2(&mut self) -> EMC2_W<'_>`[src]

Bits 8:9 - External Match Control 2. Determines the functionality of External Match 2.

`pub fn emc3(&mut self) -> EMC3_W<'_>`[src]

Bits 10:11 - External Match Control 3. Determines the functionality of External Match 3.

`impl W<u32, Reg<u32, _CTCR>>`[src]

`pub fn ctmode(&mut self) -> CTMODE_W<'_>`[src]

Bits 0:1 - Counter/Timer Mode This field selects which rising APB bus clock edges can increment Timer's Prescale Counter (PC), or clear PC and increment Timer Counter (TC). Timer Mode: the TC is incremented when the Prescale Counter matches the Prescale Register.

`pub fn cinsel(&mut self) -> CINSEL_W<'_>`[src]

Bits 2:3 - Count Input Select When bits 1:0 in this register are not 00, these bits select which CAP pin is sampled for clocking. Note: If Counter mode is selected for a particular CAPn input in the CTCR, the 3 bits for that input in the Capture Control Register (CCR) must be programmed as 000. However, capture and/or interrupt can be selected for the other 3 CAPn inputs in the same timer.

`pub fn encc(&mut self) -> ENCC_W<'_>`[src]

Bit 4 - Setting this bit to 1 enables clearing of the timer and the prescaler when the capture-edge event specified in bits 7:5 occurs.

`pub fn selcc(&mut self) -> SELCC_W<'_>`[src]

Bits 5:7 - Edge select. When bit 4 is 1, these bits select which capture input edge will cause the timer and prescaler to be cleared. These bits have no effect when bit 4 is low. Values 0x2 to 0x3 and 0x6 to 0x7 are reserved.

`impl W<u32, Reg<u32, _PWMC>>`[src]

`pub fn pwmen0(&mut self) -> PWMEN0_W<'_>`[src]

Bit 0 - PWM mode enable for channel0.

`pub fn pwmen1(&mut self) -> PWMEN1_W<'_>`[src]

Bit 1 - PWM mode enable for channel1.

`pub fn pwmen2(&mut self) -> PWMEN2_W<'_>`[src]

Bit 2 - PWM mode enable for channel2.

`pub fn pwmen3(&mut self) -> PWMEN3_W<'_>`[src]

Bit 3 - PWM mode enable for channel3. Note: It is recommended to use match channel 3 to set the PWM cycle.

`impl W<u32, Reg<u32, _MSR>>`[src]

`pub fn shadow(&mut self) -> SHADOW_W<'_>`[src]

Bits 0:31 - Timer counter match shadow value.

`impl W<u32, Reg<u32, _MOD>>`[src]

`pub fn wden(&mut self) -> WDEN_W<'_>`[src]

Bit 0 - Watchdog enable bit. Once this bit is set to one and a watchdog feed is performed, the watchdog timer will run permanently.

`pub fn wdreset(&mut self) -> WDRESET_W<'_>`[src]

Bit 1 - Watchdog reset enable bit. Once this bit has been written with a 1 it cannot be re-written with a 0.

`pub fn wdtof(&mut self) -> WDTOF_W<'_>`[src]

Bit 2 - Watchdog time-out flag. Set when the watchdog timer times out, by a feed error, or by events associated with WDPROTECT. Cleared by software writing a 0 to this bit position. Causes a chip reset if WDRESET = 1.

`pub fn wdint(&mut self) -> WDINT_W<'_>`[src]

Bit 3 - Warning interrupt flag. Set when the timer is at or below the value in WDWARNINT. Cleared by software writing a 1 to this bit position. Note that this bit cannot be cleared while the WARNINT value is equal to the value of the TV register. This can occur if the value of WARNINT is 0 and the WDRESET bit is 0 when TV decrements to 0.

`pub fn wdprotect(&mut self) -> WDPROTECT_W<'_>`[src]

Bit 4 - Watchdog update mode. This bit can be set once by software and is only cleared by a reset.

`impl W<u32, Reg<u32, _TC>>`[src]

`pub fn count(&mut self) -> COUNT_W<'_>`[src]

Bits 0:23 - Watchdog time-out value.

`impl W<u32, Reg<u32, _FEED>>`[src]

`pub fn feed(&mut self) -> FEED_W<'_>`[src]

Bits 0:7 - Feed value should be 0xAA followed by 0x55.

`impl W<u32, Reg<u32, _WARNINT>>`[src]

`pub fn warnint(&mut self) -> WARNINT_W<'_>`[src]

Bits 0:9 - Watchdog warning interrupt compare value.

`impl W<u32, Reg<u32, _WINDOW>>`[src]

`pub fn window(&mut self) -> WINDOW_W<'_>`[src]

Bits 0:23 - Watchdog window value.

`impl W<u32, Reg<u32, _INTVAL>>`[src]

`pub fn ivalue(&mut self) -> IVALUE_W<'_>`[src]

Bits 0:23 - Time interval load value. This value is loaded into the TIMERn register and the MRT channel n starts counting down from IVALUE -1. If the timer is idle, writing a non-zero value to this bit field starts the timer immediately. If the timer is running, writing a zero to this bit field does the following: If LOAD = 1, the timer stops immediately. If LOAD = 0, the timer stops at the end of the time interval.

`pub fn load(&mut self) -> LOAD_W<'_>`[src]

Bit 31 - Determines how the timer interval value IVALUE -1 is loaded into the TIMERn register. This bit is write-only. Reading this bit always returns 0.

`impl W<u32, Reg<u32, _CTRL>>`[src]

`pub fn inten(&mut self) -> INTEN_W<'_>`[src]

Bit 0 - Enable the TIMERn interrupt.

`pub fn mode(&mut self) -> MODE_W<'_>`[src]

Bits 1:2 - Selects timer mode.

`impl W<u32, Reg<u32, _STAT>>`[src]

`pub fn intflag(&mut self) -> INTFLAG_W<'_>`[src]

Bit 0 - Monitors the interrupt flag.

`pub fn run(&mut self) -> RUN_W<'_>`[src]

Bit 1 - Indicates the state of TIMERn. This bit is read-only.

`pub fn inuse(&mut self) -> INUSE_W<'_>`[src]

Bit 2 - Channel In Use flag. Operating details depend on the MULTITASK bit in the MODCFG register, and affects the use of IDLE_CH. See Idle channel register for details of the two operating modes.

`impl W<u32, Reg<u32, _MODCFG>>`[src]

`pub fn noc(&mut self) -> NOC_W<'_>`[src]

Bits 0:3 - Identifies the number of channels in this MRT.(4 channels on this device.)

`pub fn nob(&mut self) -> NOB_W<'_>`[src]

Bits 4:8 - Identifies the number of timer bits in this MRT. (24 bits wide on this device.)

`pub fn multitask(&mut self) -> MULTITASK_W<'_>`[src]

Bit 31 - Selects the operating mode for the INUSE flags and the IDLE_CH register.

`impl W<u32, Reg<u32, _IRQ_FLAG>>`[src]

`pub fn gflag0(&mut self) -> GFLAG0_W<'_>`[src]

Bit 0 - Monitors the interrupt flag of TIMER0.

`pub fn gflag1(&mut self) -> GFLAG1_W<'_>`[src]

Bit 1 - Monitors the interrupt flag of TIMER1. See description of channel 0.

`pub fn gflag2(&mut self) -> GFLAG2_W<'_>`[src]

Bit 2 - Monitors the interrupt flag of TIMER2. See description of channel 0.

`pub fn gflag3(&mut self) -> GFLAG3_W<'_>`[src]

Bit 3 - Monitors the interrupt flag of TIMER3. See description of channel 0.

`impl W<u32, Reg<u32, _CTRL>>`[src]

`pub fn delayval(&mut self) -> DELAYVAL_W<'_>`[src]

Bits 0:30 - Tick interval value. The delay will be equal to DELAYVAL + 1 periods of the timer clock. The minimum usable value is 1, for a delay of 2 timer clocks. A value of 0 stops the timer.

`pub fn repeat(&mut self) -> REPEAT_W<'_>`[src]

Bit 31 - Repeat delay. 0 = One-time delay. 1 = Delay repeats continuously.

`impl W<u32, Reg<u32, _STAT>>`[src]

`pub fn intr(&mut self) -> INTR_W<'_>`[src]

Bit 0 - Interrupt flag. 0 = No interrupt is pending. 1 = An interrupt is pending. A write of any value to this register clears this flag.

`pub fn active(&mut self) -> ACTIVE_W<'_>`[src]

Bit 1 - Active flag. 0 = The Micro-Tick Timer is stopped. 1 = The Micro-Tick Timer is currently active.

`impl W<u32, Reg<u32, _CFG>>`[src]

`pub fn capen0(&mut self) -> CAPEN0_W<'_>`[src]

Bit 0 - Enable Capture 0. 1 = Enabled, 0 = Disabled.

`pub fn capen1(&mut self) -> CAPEN1_W<'_>`[src]

Bit 1 - Enable Capture 1. 1 = Enabled, 0 = Disabled.

`pub fn capen2(&mut self) -> CAPEN2_W<'_>`[src]

Bit 2 - Enable Capture 2. 1 = Enabled, 0 = Disabled.

`pub fn capen3(&mut self) -> CAPEN3_W<'_>`[src]

Bit 3 - Enable Capture 3. 1 = Enabled, 0 = Disabled.

`pub fn cappol0(&mut self) -> CAPPOL0_W<'_>`[src]

Bit 8 - Capture Polarity 0. 0 = Positive edge capture, 1 = Negative edge capture.

`pub fn cappol1(&mut self) -> CAPPOL1_W<'_>`[src]

Bit 9 - Capture Polarity 1. 0 = Positive edge capture, 1 = Negative edge capture.

`pub fn cappol2(&mut self) -> CAPPOL2_W<'_>`[src]

Bit 10 - Capture Polarity 2. 0 = Positive edge capture, 1 = Negative edge capture.

`pub fn cappol3(&mut self) -> CAPPOL3_W<'_>`[src]

Bit 11 - Capture Polarity 3. 0 = Positive edge capture, 1 = Negative edge capture.

`impl W<u32, Reg<u32, _CAPCLR>>`[src]

`pub fn capclr0(&mut self) -> CAPCLR0_W<'_>`[src]

Bit 0 - Clear capture 0. Writing 1 to this bit clears the CAP0 register value.

`pub fn capclr1(&mut self) -> CAPCLR1_W<'_>`[src]

Bit 1 - Clear capture 1. Writing 1 to this bit clears the CAP1 register value.

`pub fn capclr2(&mut self) -> CAPCLR2_W<'_>`[src]

Bit 2 - Clear capture 2. Writing 1 to this bit clears the CAP2 register value.

`pub fn capclr3(&mut self) -> CAPCLR3_W<'_>`[src]

Bit 3 - Clear capture 3. Writing 1 to this bit clears the CAP3 register value.

`impl W<u32, Reg<u32, _FREQ_ME_CTRL>>`[src]

`pub fn capval_scale(&mut self) -> CAPVAL_SCALE_W<'_>`[src]

Bits 0:30 - Frequency measure result /Frequency measur scale

`pub fn prog(&mut self) -> PROG_W<'_>`[src]

Bit 31 - Set this bit to one to initiate a frequency measurement cycle. Hardware clears this bit when the measurement cycle has completed and there is valid capture data in the CAPVAL field (bits 30:0).

`impl W<u32, Reg<u32, _FRO192M_CTRL>>`[src]

`pub fn ena_12mhzclk(&mut self) -> ENA_12MHZCLK_W<'_>`[src]

Bit 14 - 12 MHz clock control.

`pub fn ena_48mhzclk(&mut self) -> ENA_48MHZCLK_W<'_>`[src]

Bit 15 - 48 MHz clock control.

`pub fn dac_trim(&mut self) -> DAC_TRIM_W<'_>`[src]

Bits 16:23 - Frequency trim.

`pub fn usbclkadj(&mut self) -> USBCLKADJ_W<'_>`[src]

Bit 24 - If this bit is set and the USB peripheral is enabled into full speed device mode, the USB block will provide FRO clock adjustments to lock it to the host clock using the SOF packets.

`pub fn ena_96mhzclk(&mut self) -> ENA_96MHZCLK_W<'_>`[src]

Bit 30 - 96 MHz clock control.

`impl W<u32, Reg<u32, _XO32M_CTRL>>`[src]

`pub fn acbuf_pass_enable(&mut self) -> ACBUF_PASS_ENABLE_W<'_>`[src]

Bit 22 - Bypass enable of XO AC buffer enable in pll and top level.

`pub fn enable_pll_usb_out(&mut self) -> ENABLE_PLL_USB_OUT_W<'_>`[src]

Bit 23 - Enable High speed Crystal oscillator output to USB HS PLL.

`pub fn enable_system_clk_out(&mut self) -> ENABLE_SYSTEM_CLK_OUT_W<'_>`[src]

Bit 24 - Enable XO 32 MHz output to CPU system.

`impl W<u32, Reg<u32, _BOD_DCDC_INT_CTRL>>`[src]

`pub fn bodvbat_int_enable(&mut self) -> BODVBAT_INT_ENABLE_W<'_>`[src]

Bit 0 - BOD VBAT interrupt control.

`pub fn bodvbat_int_clear(&mut self) -> BODVBAT_INT_CLEAR_W<'_>`[src]

Bit 1 - BOD VBAT interrupt clear.1: Clear the interrupt. Self-cleared bit.

`pub fn bodcore_int_enable(&mut self) -> BODCORE_INT_ENABLE_W<'_>`[src]

Bit 2 - BOD CORE interrupt control.

`pub fn bodcore_int_clear(&mut self) -> BODCORE_INT_CLEAR_W<'_>`[src]

Bit 3 - BOD CORE interrupt clear.1: Clear the interrupt. Self-cleared bit.

`pub fn dcdc_int_enable(&mut self) -> DCDC_INT_ENABLE_W<'_>`[src]

Bit 4 - DCDC interrupt control.

`pub fn dcdc_int_clear(&mut self) -> DCDC_INT_CLEAR_W<'_>`[src]

Bit 5 - DCDC interrupt clear.1: Clear the interrupt. Self-cleared bit.

`impl W<u32, Reg<u32, _RINGO0_CTRL>>`[src]

`pub fn sl(&mut self) -> SL_W<'_>`[src]

Bit 0 - Select short or long ringo (for all ringos types).

`pub fn fs(&mut self) -> FS_W<'_>`[src]

Bit 1 - Ringo frequency output divider.

`pub fn swn_swp(&mut self) -> SWN_SWP_W<'_>`[src]

Bits 2:3 - PN-Ringos (P-Transistor and N-Transistor processing) control.

`pub fn pd(&mut self) -> PD_W<'_>`[src]

Bit 4 - Ringo module Power control.

`pub fn e_nd0(&mut self) -> E_ND0_W<'_>`[src]

Bit 5 - First NAND2-based ringo control.

`pub fn e_nd1(&mut self) -> E_ND1_W<'_>`[src]

Bit 6 - Second NAND2-based ringo control.

`pub fn e_nr0(&mut self) -> E_NR0_W<'_>`[src]

Bit 7 - First NOR2-based ringo control.

`pub fn e_nr1(&mut self) -> E_NR1_W<'_>`[src]

Bit 8 - Second NOR2-based ringo control.

`pub fn e_iv0(&mut self) -> E_IV0_W<'_>`[src]

Bit 9 - First Inverter-based ringo control.

`pub fn e_iv1(&mut self) -> E_IV1_W<'_>`[src]

Bit 10 - Second Inverter-based ringo control.

`pub fn e_pn0(&mut self) -> E_PN0_W<'_>`[src]

Bit 11 - First PN (P-Transistor and N-Transistor processing) monitor control.

`pub fn e_pn1(&mut self) -> E_PN1_W<'_>`[src]

Bit 12 - Second PN (P-Transistor and N-Transistor processing) monitor control.

`pub fn divisor(&mut self) -> DIVISOR_W<'_>`[src]

Bits 16:19 - Ringo out Clock divider value. Frequency Output = Frequency input / (DIViSOR+1). (minimum = Frequency input / 16)

`impl W<u32, Reg<u32, _RINGO1_CTRL>>`[src]

`pub fn s(&mut self) -> S_W<'_>`[src]

Bit 0 - Select short or long ringo (for all ringos types).

`pub fn fs(&mut self) -> FS_W<'_>`[src]

Bit 1 - Ringo frequency output divider.

`pub fn pd(&mut self) -> PD_W<'_>`[src]

Bit 2 - Ringo module Power control.

`pub fn e_r24(&mut self) -> E_R24_W<'_>`[src]

Bit 3 - .

`pub fn e_r35(&mut self) -> E_R35_W<'_>`[src]

Bit 4 - .

`pub fn e_m2(&mut self) -> E_M2_W<'_>`[src]

Bit 5 - Metal 2 (M2) monitor control.

`pub fn e_m3(&mut self) -> E_M3_W<'_>`[src]

Bit 6 - Metal 3 (M3) monitor control.

`pub fn e_m4(&mut self) -> E_M4_W<'_>`[src]

Bit 7 - Metal 4 (M4) monitor control.

`pub fn e_m5(&mut self) -> E_M5_W<'_>`[src]

Bit 8 - Metal 5 (M5) monitor control.

`pub fn divisor(&mut self) -> DIVISOR_W<'_>`[src]

Bits 16:19 - Ringo out Clock divider value. Frequency Output = Frequency input / (DIViSOR+1). (minimum = Frequency input / 16)

`impl W<u32, Reg<u32, _RINGO2_CTRL>>`[src]

`pub fn s(&mut self) -> S_W<'_>`[src]

Bit 0 - Select short or long ringo (for all ringos types).

`pub fn fs(&mut self) -> FS_W<'_>`[src]

Bit 1 - Ringo frequency output divider.

`pub fn pd(&mut self) -> PD_W<'_>`[src]

Bit 2 - Ringo module Power control.

`pub fn e_r24(&mut self) -> E_R24_W<'_>`[src]

Bit 3 - .

`pub fn e_r35(&mut self) -> E_R35_W<'_>`[src]

Bit 4 - .

`pub fn e_m2(&mut self) -> E_M2_W<'_>`[src]

Bit 5 - Metal 2 (M2) monitor control.

`pub fn e_m3(&mut self) -> E_M3_W<'_>`[src]

Bit 6 - Metal 3 (M3) monitor control.

`pub fn e_m4(&mut self) -> E_M4_W<'_>`[src]

Bit 7 - Metal 4 (M4) monitor control.

`pub fn e_m5(&mut self) -> E_M5_W<'_>`[src]

Bit 8 - Metal 5 (M5) monitor control.

`pub fn divisor(&mut self) -> DIVISOR_W<'_>`[src]

Bits 16:19 - Ringo out Clock divider value. Frequency Output = Frequency input / (DIViSOR+1). (minimum = Frequency input / 16)

`impl W<u32, Reg<u32, _USBHS_PHY_CTRL>>`[src]

`pub fn usb_vbusvalid_ext(&mut self) -> USB_VBUSVALID_EXT_W<'_>`[src]

Bit 0 - Override value for Vbus if using external detectors.

`pub fn usb_id_ext(&mut self) -> USB_ID_EXT_W<'_>`[src]

Bit 1 - Override value for ID if using external detectors.

`impl W<u32, Reg<u32, _RESETCTRL>>`[src]

`pub fn dpdwakeupresetenable(&mut self) -> DPDWAKEUPRESETENABLE_W<'_>`[src]

Bit 0 - Wake-up from DEEP POWER DOWN reset event (either from wake up I/O or RTC or OS Event Timer).

`pub fn bodvbatresetenable(&mut self) -> BODVBATRESETENABLE_W<'_>`[src]

Bit 1 - BOD VBAT reset enable.

`pub fn swrresetenable(&mut self) -> SWRRESETENABLE_W<'_>`[src]

Bit 3 - Software reset enable.

`impl W<u32, Reg<u32, _BODVBAT>>`[src]

`pub fn triglvl(&mut self) -> TRIGLVL_W<'_>`[src]

Bits 0:4 - BoD trigger level.

`pub fn hyst(&mut self) -> HYST_W<'_>`[src]

Bits 5:6 - BoD Hysteresis control.

`impl W<u32, Reg<u32, _COMP>>`[src]

`pub fn hyst(&mut self) -> HYST_W<'_>`[src]

Bit 1 - Hysteris when hyst = '1'.

`pub fn vrefinput(&mut self) -> VREFINPUT_W<'_>`[src]

Bit 2 - Dedicated control bit to select between internal VREF and VDDA (for the resistive ladder).

`pub fn lowpower(&mut self) -> LOWPOWER_W<'_>`[src]

Bit 3 - Low power mode.

`pub fn pmux(&mut self) -> PMUX_W<'_>`[src]

Bits 4:6 - Control word for P multiplexer:.

`pub fn nmux(&mut self) -> NMUX_W<'_>`[src]

Bits 7:9 - Control word for N multiplexer:.

`pub fn vref(&mut self) -> VREF_W<'_>`[src]

Bits 10:14 - Control reference voltage step, per steps of (VREFINPUT/31).

`pub fn filtercgf_samplemode(&mut self) -> FILTERCGF_SAMPLEMODE_W<'_>`[src]

Bits 16:17 - Control the filtering of the Analog Comparator output.

`pub fn filtercgf_clkdiv(&mut self) -> FILTERCGF_CLKDIV_W<'_>`[src]

Bits 18:20 - Filter Clock divider.

`impl W<u32, Reg<u32, _WAKEIOCAUSE>>`[src]

`pub fn wakeup1(&mut self) -> WAKEUP1_W<'_>`[src]

Bit 1 - Allows to identify Wake up I/O 1 as the wake-up source from Deep Power Down mode.

`pub fn wakeup2(&mut self) -> WAKEUP2_W<'_>`[src]

Bit 2 - Allows to identify Wake up I/O 2 as the wake-up source from Deep Power Down mode.

`pub fn wakeup3(&mut self) -> WAKEUP3_W<'_>`[src]

Bit 3 - Allows to identify Wake up I/O 3 as the wake-up source from Deep Power Down mode.

`impl W<u32, Reg<u32, _STATUSCLK>>`[src]

`pub fn xtal32koscfailure(&mut self) -> XTAL32KOSCFAILURE_W<'_>`[src]

Bit 2 - XTAL32 KHZ oscillator oscillation failure detection indicator.

`impl W<u32, Reg<u32, _AOREG1>>`[src]

`pub fn por(&mut self) -> POR_W<'_>`[src]

Bit 4 - The last chip reset was caused by a Power On Reset.

`pub fn padreset(&mut self) -> PADRESET_W<'_>`[src]

Bit 5 - The last chip reset was caused by a Pin Reset.

`pub fn bodreset(&mut self) -> BODRESET_W<'_>`[src]

Bit 6 - The last chip reset was caused by a Brown Out Detector (BoD), either VBAT BoD or Core Logic BoD.

`pub fn systemreset(&mut self) -> SYSTEMRESET_W<'_>`[src]

Bit 7 - The last chip reset was caused by a System Reset requested by the ARM CPU.

`pub fn wdtreset(&mut self) -> WDTRESET_W<'_>`[src]

Bit 8 - The last chip reset was caused by the Watchdog Timer.

`pub fn swrreset(&mut self) -> SWRRESET_W<'_>`[src]

Bit 9 - The last chip reset was caused by a Software event.

`pub fn dpdreset_wakeupio(&mut self) -> DPDRESET_WAKEUPIO_W<'_>`[src]

Bit 10 - The last chip reset was caused by a Wake-up I/O reset event during a Deep Power-Down mode.

`pub fn dpdreset_rtc(&mut self) -> DPDRESET_RTC_W<'_>`[src]

Bit 11 - The last chip reset was caused by an RTC (either RTC Alarm or RTC wake up) reset event during a Deep Power-Down mode.

`pub fn dpdreset_ostimer(&mut self) -> DPDRESET_OSTIMER_W<'_>`[src]

Bit 12 - The last chip reset was caused by an OS Event Timer reset event during a Deep Power-Down mode.

`pub fn booterrorcounter(&mut self) -> BOOTERRORCOUNTER_W<'_>`[src]

Bits 16:19 - ROM Boot Fatal Error Counter.

`impl W<u32, Reg<u32, _RTCOSC32K>>`[src]

`pub fn sel(&mut self) -> SEL_W<'_>`[src]

Bit 0 - Select the 32K oscillator to be used in Deep Power Down Mode for the RTC (either XTAL32KHz or FRO32KHz) .

`pub fn clk1khzdiv(&mut self) -> CLK1KHZDIV_W<'_>`[src]

Bits 1:3 - Actual division ratio is : 28 + CLK1KHZDIV.

`pub fn clk1khzdivupdatereq(&mut self) -> CLK1KHZDIVUPDATEREQ_W<'_>`[src]

Bit 15 - RTC 1KHz clock Divider status flag.

`pub fn clk1hzdiv(&mut self) -> CLK1HZDIV_W<'_>`[src]

Bits 16:26 - Actual division ratio is : 31744 + CLK1HZDIV.

`pub fn clk1hzdivhalt(&mut self) -> CLK1HZDIVHALT_W<'_>`[src]

Bit 30 - Halts the divider counter.

`pub fn clk1hzdivupdatereq(&mut self) -> CLK1HZDIVUPDATEREQ_W<'_>`[src]

Bit 31 - RTC 1Hz Divider status flag.

`impl W<u32, Reg<u32, _OSTIMER>>`[src]

`pub fn softreset(&mut self) -> SOFTRESET_W<'_>`[src]

Bit 0 - Active high reset.

`pub fn clockenable(&mut self) -> CLOCKENABLE_W<'_>`[src]

Bit 1 - Enable OSTIMER 32 KHz clock.

`pub fn dpdwakeupenable(&mut self) -> DPDWAKEUPENABLE_W<'_>`[src]

Bit 2 - Wake up enable in Deep Power Down mode (To be used in Enable Deep Power Down mode).

`pub fn osc32kpd(&mut self) -> OSC32KPD_W<'_>`[src]

Bit 3 - Oscilator 32KHz (either FRO32KHz or XTAL32KHz according to RTCOSC32K.

`impl W<u32, Reg<u32, _PDRUNCFG0>>`[src]

`pub fn pden_bodvbat(&mut self) -> PDEN_BODVBAT_W<'_>`[src]

Bit 3 - Controls power to VBAT Brown Out Detector (BOD).

`pub fn pden_fro32k(&mut self) -> PDEN_FRO32K_W<'_>`[src]

Bit 6 - Controls power to the Free Running Oscillator (FRO) 32 KHz.

`pub fn pden_xtal32k(&mut self) -> PDEN_XTAL32K_W<'_>`[src]

Bit 7 - Controls power to crystal 32 KHz.

`pub fn pden_xtal32m(&mut self) -> PDEN_XTAL32M_W<'_>`[src]

Bit 8 - Controls power to crystal 32 MHz.

`pub fn pden_pll0(&mut self) -> PDEN_PLL0_W<'_>`[src]

Bit 9 - Controls power to System PLL (also refered as PLL0).

`pub fn pden_pll1(&mut self) -> PDEN_PLL1_W<'_>`[src]

Bit 10 - Controls power to USB PLL (also refered as PLL1).

`pub fn pden_usbfsphy(&mut self) -> PDEN_USBFSPHY_W<'_>`[src]

Bit 11 - Controls power to USB Full Speed phy.

`pub fn pden_usbhsphy(&mut self) -> PDEN_USBHSPHY_W<'_>`[src]

Bit 12 - Controls power to USB High Speed Phy.

`pub fn pden_comp(&mut self) -> PDEN_COMP_W<'_>`[src]

Bit 13 - Controls power to Analog Comparator.

`pub fn pden_ldousbhs(&mut self) -> PDEN_LDOUSBHS_W<'_>`[src]

Bit 18 - Controls power to USB high speed LDO.

`pub fn pden_auxbias(&mut self) -> PDEN_AUXBIAS_W<'_>`[src]

Bit 19 - Controls power to auxiliary biasing (AUXBIAS)

`pub fn pden_ldoxo32m(&mut self) -> PDEN_LDOXO32M_W<'_>`[src]

Bit 20 - Controls power to crystal 32 MHz LDO.

`pub fn pden_rng(&mut self) -> PDEN_RNG_W<'_>`[src]

Bit 22 - Controls power to all True Random Number Genetaor (TRNG) clock sources.

`pub fn pden_pll0_sscg(&mut self) -> PDEN_PLL0_SSCG_W<'_>`[src]

Bit 23 - Controls power to System PLL (PLL0) Spread Spectrum module.

`impl W<u32, Reg<u32, _PDRUNCFGSET0>>`[src]

`pub fn pdruncfgset0(&mut self) -> PDRUNCFGSET0_W<'_>`[src]

Bits 0:31 - Writing ones to this register sets the corresponding bit or bits in the PDRUNCFG0 register, if they are implemented.

`impl W<u32, Reg<u32, _PDRUNCFGCLR0>>`[src]

`pub fn pdruncfgclr0(&mut self) -> PDRUNCFGCLR0_W<'_>`[src]

Bits 0:31 - Writing ones to this register clears the corresponding bit or bits in the PDRUNCFG0 register, if they are implemented.

`impl W<u32, Reg<u32, _UPDATELCKOUT>>`[src]

`pub fn updatelckout(&mut self) -> UPDATELCKOUT_W<'_>`[src]

Bit 0 - All Registers

`impl W<u32, Reg<u32, _FCCTRLSEL>>`[src]

`pub fn sckinsel(&mut self) -> SCKINSEL_W<'_>`[src]

Bits 0:1 - Selects the source for SCK going into this Flexcomm.

`pub fn wsinsel(&mut self) -> WSINSEL_W<'_>`[src]

Bits 8:9 - Selects the source for WS going into this Flexcomm.

`pub fn datainsel(&mut self) -> DATAINSEL_W<'_>`[src]

Bits 16:17 - Selects the source for DATA input to this Flexcomm.

`pub fn dataoutsel(&mut self) -> DATAOUTSEL_W<'_>`[src]

Bits 24:25 - Selects the source for DATA output from this Flexcomm.

`impl W<u32, Reg<u32, _SHAREDCTRLSET>>`[src]

`pub fn sharedscksel(&mut self) -> SHAREDSCKSEL_W<'_>`[src]

Bits 0:2 - Selects the source for SCK of this shared signal set.

`pub fn sharedwssel(&mut self) -> SHAREDWSSEL_W<'_>`[src]

Bits 4:6 - Selects the source for WS of this shared signal set.

`pub fn shareddatasel(&mut self) -> SHAREDDATASEL_W<'_>`[src]

Bits 8:10 - Selects the source for DATA input for this shared signal set.

`pub fn fc0dataouten(&mut self) -> FC0DATAOUTEN_W<'_>`[src]

Bit 16 - Controls FC0 contribution to SHAREDDATAOUT for this shared set.

`pub fn fc1dataouten(&mut self) -> FC1DATAOUTEN_W<'_>`[src]

Bit 17 - Controls FC1 contribution to SHAREDDATAOUT for this shared set.

`pub fn fc2dataouten(&mut self) -> FC2DATAOUTEN_W<'_>`[src]

Bit 18 - Controls FC2 contribution to SHAREDDATAOUT for this shared set.

`pub fn fc4dataouten(&mut self) -> FC4DATAOUTEN_W<'_>`[src]

Bit 20 - Controls FC4 contribution to SHAREDDATAOUT for this shared set.

`pub fn fc5dataouten(&mut self) -> FC5DATAOUTEN_W<'_>`[src]

Bit 21 - Controls FC5 contribution to SHAREDDATAOUT for this shared set.

`pub fn fc6dataouten(&mut self) -> FC6DATAOUTEN_W<'_>`[src]

Bit 22 - Controls FC6 contribution to SHAREDDATAOUT for this shared set.

`pub fn fc7dataouten(&mut self) -> FC7DATAOUTEN_W<'_>`[src]

Bit 23 - Controls FC7 contribution to SHAREDDATAOUT for this shared set.

`impl W<u32, Reg<u32, _CTRL>>`[src]

`pub fn swreset(&mut self) -> SWRESET_W<'_>`[src]

Bit 0 - Software reset control

`pub fn alarm1hz(&mut self) -> ALARM1HZ_W<'_>`[src]

Bit 2 - RTC 1 Hz timer alarm flag status.

`pub fn wake1khz(&mut self) -> WAKE1KHZ_W<'_>`[src]

Bit 3 - RTC 1 kHz timer wake-up flag status.

`pub fn alarmdpd_en(&mut self) -> ALARMDPD_EN_W<'_>`[src]

Bit 4 - RTC 1 Hz timer alarm enable for Deep power-down.

`pub fn wakedpd_en(&mut self) -> WAKEDPD_EN_W<'_>`[src]

Bit 5 - RTC 1 kHz timer wake-up enable for Deep power-down.

`pub fn rtc1khz_en(&mut self) -> RTC1KHZ_EN_W<'_>`[src]

Bit 6 - RTC 1 kHz clock enable. This bit can be set to 0 to conserve power if the 1 kHz timer is not used. This bit has no effect when the RTC is disabled (bit 7 of this register is 0).

`pub fn rtc_en(&mut self) -> RTC_EN_W<'_>`[src]

Bit 7 - RTC enable.

`pub fn rtc_osc_pd(&mut self) -> RTC_OSC_PD_W<'_>`[src]

Bit 8 - RTC oscillator power-down control.

`pub fn rtc_osc_bypass(&mut self) -> RTC_OSC_BYPASS_W<'_>`[src]

Bit 9 - RTC oscillator bypass control.

`pub fn rtc_subsec_ena(&mut self) -> RTC_SUBSEC_ENA_W<'_>`[src]

Bit 10 - RTC Sub-second counter control.

`impl W<u32, Reg<u32, _MATCH>>`[src]

`pub fn matval(&mut self) -> MATVAL_W<'_>`[src]

Bits 0:31 - Contains the match value against which the 1 Hz RTC timer will be compared to set the alarm flag RTC_ALARM and generate an alarm interrupt/wake-up if enabled.

`impl W<u32, Reg<u32, _COUNT>>`[src]

`pub fn val(&mut self) -> VAL_W<'_>`[src]

Bits 0:31 - A read reflects the current value of the main, 1 Hz RTC timer. A write loads a new initial value into the timer. The RTC counter will count up continuously at a 1 Hz rate once the RTC Software Reset is removed (by clearing bit 0 of the CTRL register). Only write to this register when the RTC_EN bit in the RTC CTRL Register is 0. The counter increments one second after the RTC_EN bit is set.

`impl W<u32, Reg<u32, _WAKE>>`[src]

`pub fn val(&mut self) -> VAL_W<'_>`[src]

Bits 0:15 - A read reflects the current value of the high-resolution/wake-up timer. A write pre-loads a start count value into the wake-up timer and initializes a count-down sequence. Do not write to this register while counting is in progress.

`impl W<u32, Reg<u32, _GPREG>>`[src]

`pub fn gpdata(&mut self) -> GPDATA_W<'_>`[src]

Bits 0:31 - Data retained during Deep power-down mode or loss of main power as long as VBAT is supplied.

`impl W<u32, Reg<u32, _MATCHN_L>>`[src]

`pub fn matchn_value(&mut self) -> MATCHN_VALUE_W<'_>`[src]

Bits 0:31 - The value written to the MATCH (L/H) register pair is compared against the central EVTIMER. When a match occurs, an interrupt request is generated if enabled. A separate pair of MATCH registers are implemented for each CPU. Each CPU reads its own local value at the same pair of addresses.

`impl W<u32, Reg<u32, _MATCHN_H>>`[src]

`pub fn matchn_value(&mut self) -> MATCHN_VALUE_W<'_>`[src]

Bits 0:9 - The value written to the MATCH (L/H) register pair is compared against the central EVTIMER. When a match occurs, an interrupt request is generated if enabled. A separate pair of MATCH registers are implemented for each CPU. Each CPU reads its own local value at the same pair of addresses.

`impl W<u32, Reg<u32, _OSEVENT_CTRL>>`[src]

`pub fn ostimer_intrflag(&mut self) -> OSTIMER_INTRFLAG_W<'_>`[src]

Bit 0 - This bit is set when a match occurs between the central 64-bit EVTIMER and the value programmed in the Match-register pair for the associated CPU This bit is cleared by writing a '1'. Writes to clear this bit are asynchronous. This should be done before a new match value is written into the MATCH_L/H registers

`pub fn ostimer_intena(&mut self) -> OSTIMER_INTENA_W<'_>`[src]

Bit 1 - When this bit is '1' an interrupt/wakeup request to the Domainn processor will be asserted when the OSTIMER_INTR flag is set. When this bit is '0', interrupt/wakeup requests due to the OSTIMER_INTR flag are blocked.A separate OSEVENT_CTRL register is implemented for each CPU. Each CPU reads its own local value at the same address.

`impl W<u32, Reg<u32, _CMD>>`[src]

`pub fn cmd(&mut self) -> CMD_W<'_>`[src]

Bits 0:31 - command register.

`impl W<u32, Reg<u32, _EVENT>>`[src]

`pub fn rst(&mut self) -> RST_W<'_>`[src]

Bit 0 - When bit is set, the controller and flash are reset.

`pub fn wakeup(&mut self) -> WAKEUP_W<'_>`[src]

Bit 1 - When bit is set, the controller wakes up from whatever low power or powerdown mode was active.

`pub fn abort(&mut self) -> ABORT_W<'_>`[src]

Bit 2 - When bit is set, a running program/erase command is aborted.

`impl W<u32, Reg<u32, _STARTA>>`[src]

`pub fn starta(&mut self) -> STARTA_W<'_>`[src]

Bits 0:17 - Address / Start address for commands that take an address (range) as a parameter.

`impl W<u32, Reg<u32, _STOPA>>`[src]

`pub fn stopa(&mut self) -> STOPA_W<'_>`[src]

Bits 0:17 - Stop address for commands that take an address range as a parameter (the word specified by STOPA is included in the address range).

`impl W<u32, Reg<u32, _DATAW>>`[src]

`pub fn dataw(&mut self) -> DATAW_W<'_>`[src]

Bits 0:31 - no description available

`impl W<u32, Reg<u32, _INT_CLR_ENABLE>>`[src]

`pub fn fail(&mut self) -> FAIL_W<'_>`[src]

Bit 0 - When a CLR_ENABLE bit is written to 1, the corresponding INT_ENABLE bit is cleared.

`pub fn err(&mut self) -> ERR_W<'_>`[src]

Bit 1 - When a CLR_ENABLE bit is written to 1, the corresponding INT_ENABLE bit is cleared.

`pub fn done(&mut self) -> DONE_W<'_>`[src]

Bit 2 - When a CLR_ENABLE bit is written to 1, the corresponding INT_ENABLE bit is cleared.

`pub fn ecc_err(&mut self) -> ECC_ERR_W<'_>`[src]

Bit 3 - When a CLR_ENABLE bit is written to 1, the corresponding INT_ENABLE bit is cleared.

`impl W<u32, Reg<u32, _INT_SET_ENABLE>>`[src]

`pub fn fail(&mut self) -> FAIL_W<'_>`[src]

Bit 0 - When a SET_ENABLE bit is written to 1, the corresponding INT_ENABLE bit is set.

`pub fn err(&mut self) -> ERR_W<'_>`[src]

Bit 1 - When a SET_ENABLE bit is written to 1, the corresponding INT_ENABLE bit is set.

`pub fn done(&mut self) -> DONE_W<'_>`[src]

Bit 2 - When a SET_ENABLE bit is written to 1, the corresponding INT_ENABLE bit is set.

`pub fn ecc_err(&mut self) -> ECC_ERR_W<'_>`[src]

Bit 3 - When a SET_ENABLE bit is written to 1, the corresponding INT_ENABLE bit is set.

`impl W<u32, Reg<u32, _INT_CLR_STATUS>>`[src]

`pub fn fail(&mut self) -> FAIL_W<'_>`[src]

Bit 0 - When a CLR_STATUS bit is written to 1, the corresponding INT_STATUS bit is cleared.

`pub fn err(&mut self) -> ERR_W<'_>`[src]

Bit 1 - When a CLR_STATUS bit is written to 1, the corresponding INT_STATUS bit is cleared.

`pub fn done(&mut self) -> DONE_W<'_>`[src]

Bit 2 - When a CLR_STATUS bit is written to 1, the corresponding INT_STATUS bit is cleared.

`pub fn ecc_err(&mut self) -> ECC_ERR_W<'_>`[src]

Bit 3 - When a CLR_STATUS bit is written to 1, the corresponding INT_STATUS bit is cleared.

`impl W<u32, Reg<u32, _INT_SET_STATUS>>`[src]

`pub fn fail(&mut self) -> FAIL_W<'_>`[src]

Bit 0 - When a SET_STATUS bit is written to 1, the corresponding INT_STATUS bit is set.

`pub fn err(&mut self) -> ERR_W<'_>`[src]

Bit 1 - When a SET_STATUS bit is written to 1, the corresponding INT_STATUS bit is set.

`pub fn done(&mut self) -> DONE_W<'_>`[src]

Bit 2 - When a SET_STATUS bit is written to 1, the corresponding INT_STATUS bit is set.

`pub fn ecc_err(&mut self) -> ECC_ERR_W<'_>`[src]

Bit 3 - When a SET_STATUS bit is written to 1, the corresponding INT_STATUS bit is set.

`impl W<u32, Reg<u32, _ENC_ENABLE>>`[src]

`pub fn en(&mut self) -> EN_W<'_>`[src]

Bit 0 - Encryption Enable.

`impl W<u32, Reg<u32, _MASK_LSB>>`[src]

`pub fn maskval(&mut self) -> MASKVAL_W<'_>`[src]

Bits 0:31 - Value of the 32 Least Significant Bits of the 64-bit data mask.

`impl W<u32, Reg<u32, _MASK_MSB>>`[src]

`pub fn maskval(&mut self) -> MASKVAL_W<'_>`[src]

Bits 0:31 - Value of the 32 Most Significant Bits of the 64-bit data mask.

`impl W<u32, Reg<u32, _LOCK>>`[src]

`pub fn lockreg0(&mut self) -> LOCKREG0_W<'_>`[src]

Bit 0 - Lock Region 0 registers.

`pub fn lockreg1(&mut self) -> LOCKREG1_W<'_>`[src]

Bit 1 - Lock Region 1 registers.

`pub fn lockreg2(&mut self) -> LOCKREG2_W<'_>`[src]

Bit 2 - Lock Region 2 registers.

`pub fn lockmask(&mut self) -> LOCKMASK_W<'_>`[src]

Bit 8 - Lock the Mask registers.

`impl W<u32, Reg<u32, _IV_LSB0>>`[src]

`pub fn ivval(&mut self) -> IVVAL_W<'_>`[src]

Bits 0:31 - Initial Vector value for the 32 Least Significant Bits of the 64-bit Initial Vector.

`impl W<u32, Reg<u32, _IV_MSB0>>`[src]

`pub fn ivval(&mut self) -> IVVAL_W<'_>`[src]

Bits 0:31 - Initial Vector value for the 32 Most Significant Bits of the 64-bit Initial Vector.

`impl W<u32, Reg<u32, _BASE_ADDR0>>`[src]

`pub fn addr_prg(&mut self) -> ADDR_PRG_W<'_>`[src]

Bits 18:19 - Programmable portion of the base address of region 0.

`impl W<u32, Reg<u32, _SR_ENABLE0>>`[src]

`pub fn en(&mut self) -> EN_W<'_>`[src]

Bits 0:31 - Each bit in this field enables an 8KB subregion for encryption at offset 8KB*bitnum of region 0.

`impl W<u32, Reg<u32, _IV_LSB1>>`[src]

`pub fn ivval(&mut self) -> IVVAL_W<'_>`[src]

Bits 0:31 - Initial Vector value for the 32 Least Significant Bits of the 64-bit Initial Vector.

`impl W<u32, Reg<u32, _IV_MSB1>>`[src]

`pub fn ivval(&mut self) -> IVVAL_W<'_>`[src]

Bits 0:31 - Initial Vector value for the 32 Most Significant Bits of the 64-bit Initial Vector.

`impl W<u32, Reg<u32, _BASE_ADDR1>>`[src]

`pub fn addr_prg(&mut self) -> ADDR_PRG_W<'_>`[src]

Bits 18:19 - Programmable portion of the base address of region 1.

`impl W<u32, Reg<u32, _SR_ENABLE1>>`[src]

`pub fn en(&mut self) -> EN_W<'_>`[src]

Bits 0:31 - Each bit in this field enables an 8KB subregion for encryption at offset 8KB*bitnum of region 1.

`impl W<u32, Reg<u32, _IV_LSB2>>`[src]

`pub fn ivval(&mut self) -> IVVAL_W<'_>`[src]

Bits 0:31 - Initial Vector value for the 32 Least Significant Bits of the 64-bit Initial Vector.

`impl W<u32, Reg<u32, _IV_MSB2>>`[src]

`pub fn ivval(&mut self) -> IVVAL_W<'_>`[src]

Bits 0:31 - Initial Vector value for the 32 Most Significant Bits of the 64-bit Initial Vector.

`impl W<u32, Reg<u32, _BASE_ADDR2>>`[src]

`pub fn addr_prg(&mut self) -> ADDR_PRG_W<'_>`[src]

Bits 18:19 - Programmable portion of the base address of region 2.

`impl W<u32, Reg<u32, _SR_ENABLE2>>`[src]

`pub fn en(&mut self) -> EN_W<'_>`[src]

Bits 0:31 - Each bit in this field enables an 8KB subregion for encryption at offset 8KB*bitnum of region 2.

`impl W<u32, Reg<u32, _PWD>>`[src]

`pub fn txpwdfs(&mut self) -> TXPWDFS_W<'_>`[src]

Bit 10 - Note that this bit will be auto cleared if there is USB wakeup event while ENAUTOCLR_PHY_PWD bit of CTRL is enabled

`pub fn txpwdibias(&mut self) -> TXPWDIBIAS_W<'_>`[src]

Bit 11 - Note that this bit will be auto cleared if there is USB wakeup event while ENAUTOCLR_PHY_PWD bit of CTRL is enabled

`pub fn txpwdv2i(&mut self) -> TXPWDV2I_W<'_>`[src]

Bit 12 - Note that this bit will be auto cleared if there is USB wakeup event while ENAUTOCLR_PHY_PWD bit of CTRL is enabled

`pub fn rxpwdenv(&mut self) -> RXPWDENV_W<'_>`[src]

Bit 17 - Note that this bit will be auto cleared if there is USB wakeup event while ENAUTOCLR_PHY_PWD bit of CTRL is enabled

`pub fn rxpwd1pt1(&mut self) -> RXPWD1PT1_W<'_>`[src]

Bit 18 - Note that this bit will be auto cleared if there is USB wakeup event while ENAUTOCLR_PHY_PWD bit of CTRL is enabled

`pub fn rxpwddiff(&mut self) -> RXPWDDIFF_W<'_>`[src]

Bit 19 - Note that this bit will be auto cleared if there is USB wakeup event while ENAUTOCLR_PHY_PWD bit of CTRL is enabled

`pub fn rxpwdrx(&mut self) -> RXPWDRX_W<'_>`[src]

Bit 20 - This bit will be auto cleared if there is USB wakeup event while ENAUTOCLR_PHY_PWD bit of CTRL is enabled

`impl W<u32, Reg<u32, _PWD_SET>>`[src]

`pub fn txpwdfs(&mut self) -> TXPWDFS_W<'_>`[src]

Bit 10 - Note that this bit will be auto cleared if there is USB wakeup event while ENAUTOCLR_PHY_PWD bit of CTRL is enabled

`pub fn txpwdibias(&mut self) -> TXPWDIBIAS_W<'_>`[src]

Bit 11 - Note that this bit will be auto cleared if there is USB wakeup event while ENAUTOCLR_PHY_PWD bit of CTRL is enabled

`pub fn txpwdv2i(&mut self) -> TXPWDV2I_W<'_>`[src]

Bit 12 - Note that this bit will be auto cleared if there is USB wakeup event while ENAUTOCLR_PHY_PWD bit of CTRL is enabled

`pub fn rxpwdenv(&mut self) -> RXPWDENV_W<'_>`[src]

Bit 17 - Note that this bit will be auto cleared if there is USB wakeup event while ENAUTOCLR_PHY_PWD bit of CTRL is enabled

`pub fn rxpwd1pt1(&mut self) -> RXPWD1PT1_W<'_>`[src]

Bit 18 - Note that this bit will be auto cleared if there is USB wakeup event while ENAUTOCLR_PHY_PWD bit of CTRL is enabled

`pub fn rxpwddiff(&mut self) -> RXPWDDIFF_W<'_>`[src]

Bit 19 - Note that this bit will be auto cleared if there is USB wakeup event while ENAUTOCLR_PHY_PWD bit of CTRL is enabled

`pub fn rxpwdrx(&mut self) -> RXPWDRX_W<'_>`[src]

Bit 20 - This bit will be auto cleared if there is USB wakeup event while ENAUTOCLR_PHY_PWD bit of CTRL is enabled

`impl W<u32, Reg<u32, _PWD_CLR>>`[src]

`pub fn txpwdfs(&mut self) -> TXPWDFS_W<'_>`[src]

Bit 10 - Note that this bit will be auto cleared if there is USB wakeup event while ENAUTOCLR_PHY_PWD bit of CTRL is enabled

`pub fn txpwdibias(&mut self) -> TXPWDIBIAS_W<'_>`[src]

Bit 11 - Note that this bit will be auto cleared if there is USB wakeup event while ENAUTOCLR_PHY_PWD bit of CTRL is enabled

`pub fn txpwdv2i(&mut self) -> TXPWDV2I_W<'_>`[src]

Bit 12 - Note that this bit will be auto cleared if there is USB wakeup event while ENAUTOCLR_PHY_PWD bit of CTRL is enabled

`pub fn rxpwdenv(&mut self) -> RXPWDENV_W<'_>`[src]

Bit 17 - Note that this bit will be auto cleared if there is USB wakeup event while ENAUTOCLR_PHY_PWD bit of CTRL is enabled

`pub fn rxpwd1pt1(&mut self) -> RXPWD1PT1_W<'_>`[src]

Bit 18 - Note that this bit will be auto cleared if there is USB wakeup event while ENAUTOCLR_PHY_PWD bit of CTRL is enabled

`pub fn rxpwddiff(&mut self) -> RXPWDDIFF_W<'_>`[src]

Bit 19 - Note that this bit will be auto cleared if there is USB wakeup event while ENAUTOCLR_PHY_PWD bit of CTRL is enabled

`pub fn rxpwdrx(&mut self) -> RXPWDRX_W<'_>`[src]

Bit 20 - This bit will be auto cleared if there is USB wakeup event while ENAUTOCLR_PHY_PWD bit of CTRL is enabled

`impl W<u32, Reg<u32, _PWD_TOG>>`[src]

`pub fn txpwdfs(&mut self) -> TXPWDFS_W<'_>`[src]

Bit 10 - Note that this bit will be auto cleared if there is USB wakeup event while ENAUTOCLR_PHY_PWD bit of CTRL is enabled

`pub fn txpwdibias(&mut self) -> TXPWDIBIAS_W<'_>`[src]

Bit 11 - Note that this bit will be auto cleared if there is USB wakeup event while ENAUTOCLR_PHY_PWD bit of CTRL is enabled

`pub fn txpwdv2i(&mut self) -> TXPWDV2I_W<'_>`[src]

Bit 12 - Note that this bit will be auto cleared if there is USB wakeup event while ENAUTOCLR_PHY_PWD bit of CTRL is enabled

`pub fn rxpwdenv(&mut self) -> RXPWDENV_W<'_>`[src]

Bit 17 - Note that this bit will be auto cleared if there is USB wakeup event while ENAUTOCLR_PHY_PWD bit of CTRL is enabled

`pub fn rxpwd1pt1(&mut self) -> RXPWD1PT1_W<'_>`[src]

Bit 18 - Note that this bit will be auto cleared if there is USB wakeup event while ENAUTOCLR_PHY_PWD bit of CTRL is enabled

`pub fn rxpwddiff(&mut self) -> RXPWDDIFF_W<'_>`[src]

Bit 19 - Note that this bit will be auto cleared if there is USB wakeup event while ENAUTOCLR_PHY_PWD bit of CTRL is enabled

`pub fn rxpwdrx(&mut self) -> RXPWDRX_W<'_>`[src]

Bit 20 - This bit will be auto cleared if there is USB wakeup event while ENAUTOCLR_PHY_PWD bit of CTRL is enabled

`impl W<u32, Reg<u32, _TX>>`[src]

`pub fn d_cal(&mut self) -> D_CAL_W<'_>`[src]

Bits 0:3 - Decode to trim the nominal 17

`pub fn txcal45dm(&mut self) -> TXCAL45DM_W<'_>`[src]

Bits 8:11 - Decode to trim the nominal 45ohm series termination resistance to the USB_DM output pin

`pub fn txencal45dn(&mut self) -> TXENCAL45DN_W<'_>`[src]

Bit 13 - Enable resistance calibration on DN.

`pub fn txcal45dp(&mut self) -> TXCAL45DP_W<'_>`[src]

Bits 16:19 - Decode to trim the nominal 45ohm series termination resistance to the USB_DP output pin

`pub fn txencal45dp(&mut self) -> TXENCAL45DP_W<'_>`[src]

Bit 21 - Enable resistance calibration on DP.

`impl W<u32, Reg<u32, _TX_SET>>`[src]

`pub fn d_cal(&mut self) -> D_CAL_W<'_>`[src]

Bits 0:3 - Decode to trim the nominal 17

`pub fn txcal45dm(&mut self) -> TXCAL45DM_W<'_>`[src]

Bits 8:11 - Decode to trim the nominal 45ohm series termination resistance to the USB_DM output pin

`pub fn txencal45dn(&mut self) -> TXENCAL45DN_W<'_>`[src]

Bit 13 - Enable resistance calibration on DN.

`pub fn txcal45dp(&mut self) -> TXCAL45DP_W<'_>`[src]

Bits 16:19 - Decode to trim the nominal 45ohm series termination resistance to the USB_DP output pin

`pub fn txencal45dp(&mut self) -> TXENCAL45DP_W<'_>`[src]

Bit 21 - Enable resistance calibration on DP.

`impl W<u32, Reg<u32, _TX_CLR>>`[src]

`pub fn d_cal(&mut self) -> D_CAL_W<'_>`[src]

Bits 0:3 - Decode to trim the nominal 17

`pub fn txcal45dm(&mut self) -> TXCAL45DM_W<'_>`[src]

Bits 8:11 - Decode to trim the nominal 45ohm series termination resistance to the USB_DM output pin

`pub fn txencal45dn(&mut self) -> TXENCAL45DN_W<'_>`[src]

Bit 13 - Enable resistance calibration on DN.

`pub fn txcal45dp(&mut self) -> TXCAL45DP_W<'_>`[src]

Bits 16:19 - Decode to trim the nominal 45ohm series termination resistance to the USB_DP output pin

`pub fn txencal45dp(&mut self) -> TXENCAL45DP_W<'_>`[src]

Bit 21 - Enable resistance calibration on DP.

`impl W<u32, Reg<u32, _TX_TOG>>`[src]

`pub fn d_cal(&mut self) -> D_CAL_W<'_>`[src]

Bits 0:3 - Decode to trim the nominal 17

`pub fn txcal45dm(&mut self) -> TXCAL45DM_W<'_>`[src]

Bits 8:11 - Decode to trim the nominal 45ohm series termination resistance to the USB_DM output pin

`pub fn txencal45dn(&mut self) -> TXENCAL45DN_W<'_>`[src]

Bit 13 - Enable resistance calibration on DN.

`pub fn txcal45dp(&mut self) -> TXCAL45DP_W<'_>`[src]

Bits 16:19 - Decode to trim the nominal 45ohm series termination resistance to the USB_DP output pin

`pub fn txencal45dp(&mut self) -> TXENCAL45DP_W<'_>`[src]

Bit 21 - Enable resistance calibration on DP.

`impl W<u32, Reg<u32, _RX>>`[src]

`pub fn envadj(&mut self) -> ENVADJ_W<'_>`[src]

Bits 0:2 - The ENVADJ field adjusts the trip point for the envelope detector

`pub fn disconadj(&mut self) -> DISCONADJ_W<'_>`[src]

Bits 4:6 - The DISCONADJ field adjusts the trip point for the disconnect detector.

`pub fn rxdbypass(&mut self) -> RXDBYPASS_W<'_>`[src]

Bit 22 - This test mode is intended for lab use only, replace FS differential receiver with DP single ended receiver

`impl W<u32, Reg<u32, _RX_SET>>`[src]

`pub fn envadj(&mut self) -> ENVADJ_W<'_>`[src]

Bits 0:2 - The ENVADJ field adjusts the trip point for the envelope detector

`pub fn disconadj(&mut self) -> DISCONADJ_W<'_>`[src]

Bits 4:6 - The DISCONADJ field adjusts the trip point for the disconnect detector.

`pub fn rxdbypass(&mut self) -> RXDBYPASS_W<'_>`[src]

Bit 22 - This test mode is intended for lab use only, replace FS differential receiver with DP single ended receiver

`impl W<u32, Reg<u32, _RX_CLR>>`[src]

`pub fn envadj(&mut self) -> ENVADJ_W<'_>`[src]

Bits 0:2 - The ENVADJ field adjusts the trip point for the envelope detector

`pub fn disconadj(&mut self) -> DISCONADJ_W<'_>`[src]

Bits 4:6 - The DISCONADJ field adjusts the trip point for the disconnect detector.

`pub fn rxdbypass(&mut self) -> RXDBYPASS_W<'_>`[src]

Bit 22 - This test mode is intended for lab use only, replace FS differential receiver with DP single ended receiver

`impl W<u32, Reg<u32, _RX_TOG>>`[src]

`pub fn envadj(&mut self) -> ENVADJ_W<'_>`[src]

Bits 0:2 - The ENVADJ field adjusts the trip point for the envelope detector

`pub fn disconadj(&mut self) -> DISCONADJ_W<'_>`[src]

Bits 4:6 - The DISCONADJ field adjusts the trip point for the disconnect detector.

`pub fn rxdbypass(&mut self) -> RXDBYPASS_W<'_>`[src]

Bit 22 - This test mode is intended for lab use only, replace FS differential receiver with DP single ended receiver

`impl W<u32, Reg<u32, _CTRL>>`[src]

`pub fn enhostdiscondetect(&mut self) -> ENHOSTDISCONDETECT_W<'_>`[src]

Bit 1 - For host mode, enables high-speed disconnect detector

`pub fn enirqhostdiscon(&mut self) -> ENIRQHOSTDISCON_W<'_>`[src]

Bit 2 - Enable IRQ for Host disconnect: Enables interrupt for detection of disconnection to Device when in high-speed host mode

`pub fn hostdiscondetect_irq(&mut self) -> HOSTDISCONDETECT_IRQ_W<'_>`[src]

Bit 3 - Indicates that the device has disconnected in High-Speed mode

`pub fn endevplugindet(&mut self) -> ENDEVPLUGINDET_W<'_>`[src]

Bit 4 - Enables non-standard resistive plugged-in detection This bit field controls connection of nominal 200kohm resistors to both the USB_DP and USB_DM pins as one method of detecting when a USB cable is attached in device mode

`pub fn devplugin_polarity(&mut self) -> DEVPLUGIN_POLARITY_W<'_>`[src]

Bit 5 - Device plugin polarity: For device mode, if this bit is cleared to 0, then it trips the interrupt if the device is plugged in

`pub fn resumeirqsticky(&mut self) -> RESUMEIRQSTICKY_W<'_>`[src]

Bit 8 - Resume IRQ: Set to 1 will make RESUME_IRQ bit a sticky bit until software clear it

`pub fn enirqresumedetect(&mut self) -> ENIRQRESUMEDETECT_W<'_>`[src]

Bit 9 - Enable IRQ Resume detect: Enables interrupt for detection of a non-J state on the USB line

`pub fn resume_irq(&mut self) -> RESUME_IRQ_W<'_>`[src]

Bit 10 - Resume IRQ: Indicates that the host is sending a wake-up after suspend

`pub fn devplugin_irq(&mut self) -> DEVPLUGIN_IRQ_W<'_>`[src]

Bit 12 - Indicates that the device is connected

`pub fn enutmilevel2(&mut self) -> ENUTMILEVEL2_W<'_>`[src]

Bit 14 - Enables UTMI+ Level 2 operation for the USB HS PHY

`pub fn enutmilevel3(&mut self) -> ENUTMILEVEL3_W<'_>`[src]

Bit 15 - Enables UTMI+ Level 3 operation for the USB HS PHY

`pub fn enirqwakeup(&mut self) -> ENIRQWAKEUP_W<'_>`[src]

Bit 16 - Enable wake-up IRQ: Enables interrupt for the wake-up events.

`pub fn wakeup_irq(&mut self) -> WAKEUP_IRQ_W<'_>`[src]

Bit 17 - Wake-up IRQ: Indicates that there is a wak-eup event

`pub fn autoresume_en(&mut self) -> AUTORESUME_EN_W<'_>`[src]

Bit 18 - Enable the auto resume feature, when set, HW will use 32KHz clock to send Resume to respond to the device remote wakeup(for host mode only)

`pub fn enautoclr_clkgate(&mut self) -> ENAUTOCLR_CLKGATE_W<'_>`[src]

Bit 19 - Enables the feature to auto-clear the CLKGATE bit if there is wakeup event while USB is suspended

`pub fn enautoclr_phy_pwd(&mut self) -> ENAUTOCLR_PHY_PWD_W<'_>`[src]

Bit 20 - Enables the feature to auto-clear the PWD register bits in PWD if there is wakeup event while USB is suspended

`pub fn endpdmchg_wkup(&mut self) -> ENDPDMCHG_WKUP_W<'_>`[src]

Bit 21 - Enable DP DM change wake-up: Not for customer use

`pub fn envbuschg_wkup(&mut self) -> ENVBUSCHG_WKUP_W<'_>`[src]

Bit 23 - Enable VBUS change wake-up: Enables the feature to wake-up USB if VBUS is toggled when USB is suspended

`pub fn enautoclr_usbclkgate(&mut self) -> ENAUTOCLR_USBCLKGATE_W<'_>`[src]

Bit 25 - Enable auto-clear USB Clock gate: Enables the feature to auto-clear the USB0_CLKGATE/USB1_CLKGATE register bit in HW_DIGCTL_CTRL if there is wake-up event on USB0/USB1 while USB0/USB1 is suspended

`pub fn enautoset_usbclks(&mut self) -> ENAUTOSET_USBCLKS_W<'_>`[src]

Bit 26 - Enable auto-set of USB clocks: Enables the feature to auto-clear the EN_USB_CLKS register bits in HW_CLKCTRL_PLL1CTRL0/HW_CLKCTRL_P LL1CTRL1 if there is wake-up event on USB0/USB1 while USB0/USB1 is suspended

`pub fn host_force_ls_se0(&mut self) -> HOST_FORCE_LS_SE0_W<'_>`[src]

Bit 28 - Forces the next FS packet that is transmitted to have a EOP with low-speed timing

`pub fn utmi_suspendm(&mut self) -> UTMI_SUSPENDM_W<'_>`[src]

Bit 29 - Used by the PHY to indicate a powered-down state

`pub fn clkgate(&mut self) -> CLKGATE_W<'_>`[src]

Bit 30 - Gate UTMI Clocks

`pub fn sftrst(&mut self) -> SFTRST_W<'_>`[src]

Bit 31 - Writing a 1 to this bit will soft-reset the PWD, TX, RX, and CTRL registers

`impl W<u32, Reg<u32, _CTRL_SET>>`[src]

`pub fn enhostdiscondetect(&mut self) -> ENHOSTDISCONDETECT_W<'_>`[src]

Bit 1 - For host mode, enables high-speed disconnect detector

`pub fn enirqhostdiscon(&mut self) -> ENIRQHOSTDISCON_W<'_>`[src]

Bit 2 - Enable IRQ for Host disconnect: Enables interrupt for detection of disconnection to Device when in high-speed host mode

`pub fn hostdiscondetect_irq(&mut self) -> HOSTDISCONDETECT_IRQ_W<'_>`[src]

Bit 3 - Indicates that the device has disconnected in High-Speed mode

`pub fn endevplugindet(&mut self) -> ENDEVPLUGINDET_W<'_>`[src]

Bit 4 - Enables non-standard resistive plugged-in detection This bit field controls connection of nominal 200kohm resistors to both the USB_DP and USB_DM pins as one method of detecting when a USB cable is attached in device mode

`pub fn devplugin_polarity(&mut self) -> DEVPLUGIN_POLARITY_W<'_>`[src]

Bit 5 - Device plugin polarity: For device mode, if this bit is cleared to 0, then it trips the interrupt if the device is plugged in

`pub fn resumeirqsticky(&mut self) -> RESUMEIRQSTICKY_W<'_>`[src]

Bit 8 - Resume IRQ: Set to 1 will make RESUME_IRQ bit a sticky bit until software clear it

`pub fn enirqresumedetect(&mut self) -> ENIRQRESUMEDETECT_W<'_>`[src]

Bit 9 - Enable IRQ Resume detect: Enables interrupt for detection of a non-J state on the USB line

`pub fn resume_irq(&mut self) -> RESUME_IRQ_W<'_>`[src]

Bit 10 - Resume IRQ: Indicates that the host is sending a wake-up after suspend

`pub fn devplugin_irq(&mut self) -> DEVPLUGIN_IRQ_W<'_>`[src]

Bit 12 - Indicates that the device is connected

`pub fn enutmilevel2(&mut self) -> ENUTMILEVEL2_W<'_>`[src]

Bit 14 - Enables UTMI+ Level 2 operation for the USB HS PHY

`pub fn enutmilevel3(&mut self) -> ENUTMILEVEL3_W<'_>`[src]

Bit 15 - Enables UTMI+ Level 3 operation for the USB HS PHY

`pub fn enirqwakeup(&mut self) -> ENIRQWAKEUP_W<'_>`[src]

Bit 16 - Enable wake-up IRQ: Enables interrupt for the wake-up events.

`pub fn wakeup_irq(&mut self) -> WAKEUP_IRQ_W<'_>`[src]

Bit 17 - Wake-up IRQ: Indicates that there is a wak-eup event

`pub fn autoresume_en(&mut self) -> AUTORESUME_EN_W<'_>`[src]

Bit 18 - Enable the auto resume feature, when set, HW will use 32KHz clock to send Resume to respond to the device remote wakeup(for host mode only)

`pub fn enautoclr_clkgate(&mut self) -> ENAUTOCLR_CLKGATE_W<'_>`[src]

Bit 19 - Enables the feature to auto-clear the CLKGATE bit if there is wakeup event while USB is suspended

`pub fn enautoclr_phy_pwd(&mut self) -> ENAUTOCLR_PHY_PWD_W<'_>`[src]

Bit 20 - Enables the feature to auto-clear the PWD register bits in PWD if there is wakeup event while USB is suspended

`pub fn endpdmchg_wkup(&mut self) -> ENDPDMCHG_WKUP_W<'_>`[src]

Bit 21 - Enable DP DM change wake-up: Not for customer use

`pub fn envbuschg_wkup(&mut self) -> ENVBUSCHG_WKUP_W<'_>`[src]

Bit 23 - Enable VBUS change wake-up: Enables the feature to wake-up USB if VBUS is toggled when USB is suspended

`pub fn enautoclr_usbclkgate(&mut self) -> ENAUTOCLR_USBCLKGATE_W<'_>`[src]

Bit 25 - Enable auto-clear USB Clock gate: Enables the feature to auto-clear the USB0_CLKGATE/USB1_CLKGATE register bit in HW_DIGCTL_CTRL if there is wake-up event on USB0/USB1 while USB0/USB1 is suspended

`pub fn enautoset_usbclks(&mut self) -> ENAUTOSET_USBCLKS_W<'_>`[src]

Bit 26 - Enable auto-set of USB clocks: Enables the feature to auto-clear the EN_USB_CLKS register bits in HW_CLKCTRL_PLL1CTRL0/HW_CLKCTRL_P LL1CTRL1 if there is wake-up event on USB0/USB1 while USB0/USB1 is suspended

`pub fn host_force_ls_se0(&mut self) -> HOST_FORCE_LS_SE0_W<'_>`[src]

Bit 28 - Forces the next FS packet that is transmitted to have a EOP with low-speed timing

`pub fn clkgate(&mut self) -> CLKGATE_W<'_>`[src]

Bit 30 - Gate UTMI Clocks

`pub fn sftrst(&mut self) -> SFTRST_W<'_>`[src]

Bit 31 - Writing a 1 to this bit will soft-reset the PWD, TX, RX, and CTRL registers

`impl W<u32, Reg<u32, _CTRL_CLR>>`[src]

`pub fn enhostdiscondetect(&mut self) -> ENHOSTDISCONDETECT_W<'_>`[src]

Bit 1 - For host mode, enables high-speed disconnect detector

`pub fn enirqhostdiscon(&mut self) -> ENIRQHOSTDISCON_W<'_>`[src]

Bit 2 - Enable IRQ for Host disconnect: Enables interrupt for detection of disconnection to Device when in high-speed host mode

`pub fn hostdiscondetect_irq(&mut self) -> HOSTDISCONDETECT_IRQ_W<'_>`[src]

Bit 3 - Indicates that the device has disconnected in High-Speed mode

`pub fn endevplugindet(&mut self) -> ENDEVPLUGINDET_W<'_>`[src]

Bit 4 - Enables non-standard resistive plugged-in detection This bit field controls connection of nominal 200kohm resistors to both the USB_DP and USB_DM pins as one method of detecting when a USB cable is attached in device mode

`pub fn devplugin_polarity(&mut self) -> DEVPLUGIN_POLARITY_W<'_>`[src]

Bit 5 - Device plugin polarity: For device mode, if this bit is cleared to 0, then it trips the interrupt if the device is plugged in

`pub fn resumeirqsticky(&mut self) -> RESUMEIRQSTICKY_W<'_>`[src]

Bit 8 - Resume IRQ: Set to 1 will make RESUME_IRQ bit a sticky bit until software clear it

`pub fn enirqresumedetect(&mut self) -> ENIRQRESUMEDETECT_W<'_>`[src]

Bit 9 - Enable IRQ Resume detect: Enables interrupt for detection of a non-J state on the USB line

`pub fn resume_irq(&mut self) -> RESUME_IRQ_W<'_>`[src]

Bit 10 - Resume IRQ: Indicates that the host is sending a wake-up after suspend

`pub fn devplugin_irq(&mut self) -> DEVPLUGIN_IRQ_W<'_>`[src]

Bit 12 - Indicates that the device is connected

`pub fn enutmilevel2(&mut self) -> ENUTMILEVEL2_W<'_>`[src]

Bit 14 - Enables UTMI+ Level 2 operation for the USB HS PHY

`pub fn enutmilevel3(&mut self) -> ENUTMILEVEL3_W<'_>`[src]

Bit 15 - Enables UTMI+ Level 3 operation for the USB HS PHY

`pub fn enirqwakeup(&mut self) -> ENIRQWAKEUP_W<'_>`[src]

Bit 16 - Enable wake-up IRQ: Enables interrupt for the wake-up events.

`pub fn wakeup_irq(&mut self) -> WAKEUP_IRQ_W<'_>`[src]

Bit 17 - Wake-up IRQ: Indicates that there is a wak-eup event

`pub fn autoresume_en(&mut self) -> AUTORESUME_EN_W<'_>`[src]

Bit 18 - Enable the auto resume feature, when set, HW will use 32KHz clock to send Resume to respond to the device remote wakeup(for host mode only)

`pub fn enautoclr_clkgate(&mut self) -> ENAUTOCLR_CLKGATE_W<'_>`[src]

Bit 19 - Enables the feature to auto-clear the CLKGATE bit if there is wakeup event while USB is suspended

`pub fn enautoclr_phy_pwd(&mut self) -> ENAUTOCLR_PHY_PWD_W<'_>`[src]

Bit 20 - Enables the feature to auto-clear the PWD register bits in PWD if there is wakeup event while USB is suspended

`pub fn endpdmchg_wkup(&mut self) -> ENDPDMCHG_WKUP_W<'_>`[src]

Bit 21 - Enable DP DM change wake-up: Not for customer use

`pub fn envbuschg_wkup(&mut self) -> ENVBUSCHG_WKUP_W<'_>`[src]

Bit 23 - Enable VBUS change wake-up: Enables the feature to wake-up USB if VBUS is toggled when USB is suspended

`pub fn enautoclr_usbclkgate(&mut self) -> ENAUTOCLR_USBCLKGATE_W<'_>`[src]

Bit 25 - Enable auto-clear USB Clock gate: Enables the feature to auto-clear the USB0_CLKGATE/USB1_CLKGATE register bit in HW_DIGCTL_CTRL if there is wake-up event on USB0/USB1 while USB0/USB1 is suspended

`pub fn enautoset_usbclks(&mut self) -> ENAUTOSET_USBCLKS_W<'_>`[src]

Bit 26 - Enable auto-set of USB clocks: Enables the feature to auto-clear the EN_USB_CLKS register bits in HW_CLKCTRL_PLL1CTRL0/HW_CLKCTRL_P LL1CTRL1 if there is wake-up event on USB0/USB1 while USB0/USB1 is suspended

`pub fn host_force_ls_se0(&mut self) -> HOST_FORCE_LS_SE0_W<'_>`[src]

Bit 28 - Forces the next FS packet that is transmitted to have a EOP with low-speed timing

`pub fn utmi_suspendm(&mut self) -> UTMI_SUSPENDM_W<'_>`[src]

Bit 29 - Used by the PHY to indicate a powered-down state

`pub fn clkgate(&mut self) -> CLKGATE_W<'_>`[src]

Bit 30 - Gate UTMI Clocks

`pub fn sftrst(&mut self) -> SFTRST_W<'_>`[src]

Bit 31 - Writing a 1 to this bit will soft-reset the PWD, TX, RX, and CTRL registers

`impl W<u32, Reg<u32, _CTRL_TOG>>`[src]

`pub fn enhostdiscondetect(&mut self) -> ENHOSTDISCONDETECT_W<'_>`[src]

Bit 1 - For host mode, enables high-speed disconnect detector

`pub fn enirqhostdiscon(&mut self) -> ENIRQHOSTDISCON_W<'_>`[src]

Bit 2 - Enable IRQ for Host disconnect: Enables interrupt for detection of disconnection to Device when in high-speed host mode

`pub fn hostdiscondetect_irq(&mut self) -> HOSTDISCONDETECT_IRQ_W<'_>`[src]

Bit 3 - Indicates that the device has disconnected in High-Speed mode

`pub fn endevplugindet(&mut self) -> ENDEVPLUGINDET_W<'_>`[src]

Bit 4 - Enables non-standard resistive plugged-in detection This bit field controls connection of nominal 200kohm resistors to both the USB_DP and USB_DM pins as one method of detecting when a USB cable is attached in device mode

`pub fn devplugin_polarity(&mut self) -> DEVPLUGIN_POLARITY_W<'_>`[src]

Bit 5 - Device plugin polarity: For device mode, if this bit is cleared to 0, then it trips the interrupt if the device is plugged in

`pub fn resumeirqsticky(&mut self) -> RESUMEIRQSTICKY_W<'_>`[src]

Bit 8 - Resume IRQ: Set to 1 will make RESUME_IRQ bit a sticky bit until software clear it

`pub fn enirqresumedetect(&mut self) -> ENIRQRESUMEDETECT_W<'_>`[src]

Bit 9 - Enable IRQ Resume detect: Enables interrupt for detection of a non-J state on the USB line

`pub fn resume_irq(&mut self) -> RESUME_IRQ_W<'_>`[src]

Bit 10 - Resume IRQ: Indicates that the host is sending a wake-up after suspend

`pub fn devplugin_irq(&mut self) -> DEVPLUGIN_IRQ_W<'_>`[src]

Bit 12 - Indicates that the device is connected

`pub fn enutmilevel2(&mut self) -> ENUTMILEVEL2_W<'_>`[src]

Bit 14 - Enables UTMI+ Level 2 operation for the USB HS PHY

`pub fn enutmilevel3(&mut self) -> ENUTMILEVEL3_W<'_>`[src]

Bit 15 - Enables UTMI+ Level 3 operation for the USB HS PHY

`pub fn enirqwakeup(&mut self) -> ENIRQWAKEUP_W<'_>`[src]

Bit 16 - Enable wake-up IRQ: Enables interrupt for the wake-up events.

`pub fn wakeup_irq(&mut self) -> WAKEUP_IRQ_W<'_>`[src]

Bit 17 - Wake-up IRQ: Indicates that there is a wak-eup event

`pub fn autoresume_en(&mut self) -> AUTORESUME_EN_W<'_>`[src]

Bit 18 - Enable the auto resume feature, when set, HW will use 32KHz clock to send Resume to respond to the device remote wakeup(for host mode only)

`pub fn enautoclr_clkgate(&mut self) -> ENAUTOCLR_CLKGATE_W<'_>`[src]

Bit 19 - Enables the feature to auto-clear the CLKGATE bit if there is wakeup event while USB is suspended

`pub fn enautoclr_phy_pwd(&mut self) -> ENAUTOCLR_PHY_PWD_W<'_>`[src]

Bit 20 - Enables the feature to auto-clear the PWD register bits in PWD if there is wakeup event while USB is suspended

`pub fn endpdmchg_wkup(&mut self) -> ENDPDMCHG_WKUP_W<'_>`[src]

Bit 21 - Enable DP DM change wake-up: Not for customer use

`pub fn envbuschg_wkup(&mut self) -> ENVBUSCHG_WKUP_W<'_>`[src]

Bit 23 - Enable VBUS change wake-up: Enables the feature to wake-up USB if VBUS is toggled when USB is suspended

`pub fn enautoclr_usbclkgate(&mut self) -> ENAUTOCLR_USBCLKGATE_W<'_>`[src]

Bit 25 - Enable auto-clear USB Clock gate: Enables the feature to auto-clear the USB0_CLKGATE/USB1_CLKGATE register bit in HW_DIGCTL_CTRL if there is wake-up event on USB0/USB1 while USB0/USB1 is suspended

`pub fn enautoset_usbclks(&mut self) -> ENAUTOSET_USBCLKS_W<'_>`[src]

Bit 26 - Enable auto-set of USB clocks: Enables the feature to auto-clear the EN_USB_CLKS register bits in HW_CLKCTRL_PLL1CTRL0/HW_CLKCTRL_P LL1CTRL1 if there is wake-up event on USB0/USB1 while USB0/USB1 is suspended

`pub fn host_force_ls_se0(&mut self) -> HOST_FORCE_LS_SE0_W<'_>`[src]

Bit 28 - Forces the next FS packet that is transmitted to have a EOP with low-speed timing

`pub fn utmi_suspendm(&mut self) -> UTMI_SUSPENDM_W<'_>`[src]

Bit 29 - Used by the PHY to indicate a powered-down state

`pub fn clkgate(&mut self) -> CLKGATE_W<'_>`[src]

Bit 30 - Gate UTMI Clocks

`pub fn sftrst(&mut self) -> SFTRST_W<'_>`[src]

Bit 31 - Writing a 1 to this bit will soft-reset the PWD, TX, RX, and CTRL registers

`impl W<u32, Reg<u32, _PLL_SIC>>`[src]

`pub fn pll_en_usb_clks(&mut self) -> PLL_EN_USB_CLKS_W<'_>`[src]

Bit 6 - Enables the USB clock from PLL to USB PHY

`pub fn pll_power(&mut self) -> PLL_POWER_W<'_>`[src]

Bit 12 - Power up the USB PLL

`pub fn pll_enable(&mut self) -> PLL_ENABLE_W<'_>`[src]

Bit 13 - Enables the clock output from the USB PLL

`pub fn refbias_pwd_sel(&mut self) -> REFBIAS_PWD_SEL_W<'_>`[src]

Bit 19 - Reference bias power down select.

`pub fn refbias_pwd(&mut self) -> REFBIAS_PWD_W<'_>`[src]

Bit 20 - Power down the reference bias This bit is only used when REFBIAS_PWD_SEL is set to 1.

`pub fn pll_reg_enable(&mut self) -> PLL_REG_ENABLE_W<'_>`[src]

Bit 21 - This field controls the USB PLL regulator, set to enable the regulator

`pub fn pll_div_sel(&mut self) -> PLL_DIV_SEL_W<'_>`[src]

Bits 22:24 - This field controls the USB PLL feedback loop divider

`pub fn pll_prediv(&mut self) -> PLL_PREDIV_W<'_>`[src]

Bit 30 - This is selection between /1 or /2 to expand the range of ref input clock.

`impl W<u32, Reg<u32, _PLL_SIC_SET>>`[src]

`pub fn pll_en_usb_clks(&mut self) -> PLL_EN_USB_CLKS_W<'_>`[src]

Bit 6 - Enables the USB clock from PLL to USB PHY

`pub fn pll_power(&mut self) -> PLL_POWER_W<'_>`[src]

Bit 12 - Power up the USB PLL

`pub fn pll_enable(&mut self) -> PLL_ENABLE_W<'_>`[src]

Bit 13 - Enables the clock output from the USB PLL

`pub fn refbias_pwd_sel(&mut self) -> REFBIAS_PWD_SEL_W<'_>`[src]

Bit 19 - Reference bias power down select.

`pub fn refbias_pwd(&mut self) -> REFBIAS_PWD_W<'_>`[src]

Bit 20 - Power down the reference bias This bit is only used when REFBIAS_PWD_SEL is set to 1.

`pub fn pll_reg_enable(&mut self) -> PLL_REG_ENABLE_W<'_>`[src]

Bit 21 - This field controls the USB PLL regulator, set to enable the regulator

`pub fn pll_div_sel(&mut self) -> PLL_DIV_SEL_W<'_>`[src]

Bits 22:24 - This field controls the USB PLL feedback loop divider

`pub fn pll_prediv(&mut self) -> PLL_PREDIV_W<'_>`[src]

Bit 30 - This is selection between /1 or /2 to expand the range of ref input clock.

`impl W<u32, Reg<u32, _PLL_SIC_CLR>>`[src]

`pub fn pll_en_usb_clks(&mut self) -> PLL_EN_USB_CLKS_W<'_>`[src]

Bit 6 - Enables the USB clock from PLL to USB PHY

`pub fn pll_power(&mut self) -> PLL_POWER_W<'_>`[src]

Bit 12 - Power up the USB PLL

`pub fn pll_enable(&mut self) -> PLL_ENABLE_W<'_>`[src]

Bit 13 - Enables the clock output from the USB PLL

`pub fn refbias_pwd_sel(&mut self) -> REFBIAS_PWD_SEL_W<'_>`[src]

Bit 19 - Reference bias power down select.

`pub fn refbias_pwd(&mut self) -> REFBIAS_PWD_W<'_>`[src]

Bit 20 - Power down the reference bias This bit is only used when REFBIAS_PWD_SEL is set to 1.

`pub fn pll_reg_enable(&mut self) -> PLL_REG_ENABLE_W<'_>`[src]

Bit 21 - This field controls the USB PLL regulator, set to enable the regulator

`pub fn pll_div_sel(&mut self) -> PLL_DIV_SEL_W<'_>`[src]

Bits 22:24 - This field controls the USB PLL feedback loop divider

`pub fn pll_prediv(&mut self) -> PLL_PREDIV_W<'_>`[src]

Bit 30 - This is selection between /1 or /2 to expand the range of ref input clock.

`impl W<u32, Reg<u32, _PLL_SIC_TOG>>`[src]

`pub fn pll_en_usb_clks(&mut self) -> PLL_EN_USB_CLKS_W<'_>`[src]

Bit 6 - Enables the USB clock from PLL to USB PHY

`pub fn pll_power(&mut self) -> PLL_POWER_W<'_>`[src]

Bit 12 - Power up the USB PLL

`pub fn pll_enable(&mut self) -> PLL_ENABLE_W<'_>`[src]

Bit 13 - Enables the clock output from the USB PLL

`pub fn refbias_pwd_sel(&mut self) -> REFBIAS_PWD_SEL_W<'_>`[src]

Bit 19 - Reference bias power down select.

`pub fn refbias_pwd(&mut self) -> REFBIAS_PWD_W<'_>`[src]

Bit 20 - Power down the reference bias This bit is only used when REFBIAS_PWD_SEL is set to 1.

`pub fn pll_reg_enable(&mut self) -> PLL_REG_ENABLE_W<'_>`[src]

Bit 21 - This field controls the USB PLL regulator, set to enable the regulator

`pub fn pll_div_sel(&mut self) -> PLL_DIV_SEL_W<'_>`[src]

Bits 22:24 - This field controls the USB PLL feedback loop divider

`pub fn pll_prediv(&mut self) -> PLL_PREDIV_W<'_>`[src]

Bit 30 - This is selection between /1 or /2 to expand the range of ref input clock.

`impl W<u32, Reg<u32, _USB1_VBUS_DETECT>>`[src]

`pub fn vbusvalid_thresh(&mut self) -> VBUSVALID_THRESH_W<'_>`[src]

Bits 0:2 - Sets the threshold for the VBUSVALID comparator

`pub fn vbus_override_en(&mut self) -> VBUS_OVERRIDE_EN_W<'_>`[src]

Bit 3 - VBUS detect signal override enable

`pub fn sessend_override(&mut self) -> SESSEND_OVERRIDE_W<'_>`[src]

Bit 4 - Override value for SESSEND The bit field provides the value for USB1_VBUS_DET_STAT[0] if USB_VBUS_DETECT[3] is set to value 1'b1

`pub fn bvalid_override(&mut self) -> BVALID_OVERRIDE_W<'_>`[src]

Bit 5 - Override value for B-Device Session Valid The bit field provides the value for USB1_VBUS_DET_STAT[1] if USB_VBUS_DETECT[3] is set to value 1'b1

`pub fn avalid_override(&mut self) -> AVALID_OVERRIDE_W<'_>`[src]

Bit 6 - Override value for A-Device Session Valid The bit field provides the value for USB1_VBUS_DET_STAT[2] if USB_VBUS_DETECT[3] is set to value 1'b1

`pub fn vbusvalid_override(&mut self) -> VBUSVALID_OVERRIDE_W<'_>`[src]

Bit 7 - Override value for VBUS_VALID signal sent to USB controller The bit field provides the value for VBUS_VALID reported to the USB controller if the value of USB1_VBUS_DETECT[3] is set to 1'b1

`pub fn vbusvalid_sel(&mut self) -> VBUSVALID_SEL_W<'_>`[src]

Bit 8 - Selects the source of the VBUS_VALID signal reported to the USB controller This is one of the bit fields that selects the source of the VBUS_VALID signal reported to the USB controller

`pub fn vbus_source_sel(&mut self) -> VBUS_SOURCE_SEL_W<'_>`[src]

Bits 9:10 - Selects the source of the VBUS_VALID signal reported to the USB controller This is one of the bit fields that selects the source of the VBUS_VALID signal reported to the USB controller

`pub fn id_override_en(&mut self) -> ID_OVERRIDE_EN_W<'_>`[src]

Bit 11 - Enable ID override using the register field. This bit is only used if EXT_ID_OVERRIDE_EN = 1'b0.

`pub fn id_override(&mut self) -> ID_OVERRIDE_W<'_>`[src]

Bit 12 - ID override value.

`pub fn ext_id_override_en(&mut self) -> EXT_ID_OVERRIDE_EN_W<'_>`[src]

Bit 13 - Enable ID override using the pinmuxed value:

`pub fn ext_vbus_override_en(&mut self) -> EXT_VBUS_OVERRIDE_EN_W<'_>`[src]

Bit 14 - Enable VBUS override using the pinmuxed value.

`pub fn vbusvalid_to_sessvalid(&mut self) -> VBUSVALID_TO_SESSVALID_W<'_>`[src]

Bit 18 - Selects the comparator used for VBUS_VALID This bit field controls the comparator used to report the VBUS_VALID results in USB1_VBUS_DETECT[3] between the VBUS_VALID comparator and the Session Valid comparator

`pub fn vbusvalid_5vdetect(&mut self) -> VBUSVALID_5VDETECT_W<'_>`[src]

Bit 19 - no description available

`pub fn pwrup_cmps(&mut self) -> PWRUP_CMPS_W<'_>`[src]

Bits 20:22 - Enables the VBUS_VALID comparator: Powers up the comparator used for the VBUS_VALID detector

`pub fn discharge_vbus(&mut self) -> DISCHARGE_VBUS_W<'_>`[src]

Bit 26 - Controls VBUS discharge resistor This bit field controls a nominal 22kohm resistor between the USB1_VBUS pin and ground

`impl W<u32, Reg<u32, _USB1_VBUS_DETECT_SET>>`[src]

`pub fn vbusvalid_thresh(&mut self) -> VBUSVALID_THRESH_W<'_>`[src]

Bits 0:2 - Sets the threshold for the VBUSVALID comparator

`pub fn vbus_override_en(&mut self) -> VBUS_OVERRIDE_EN_W<'_>`[src]

Bit 3 - VBUS detect signal override enable

`pub fn sessend_override(&mut self) -> SESSEND_OVERRIDE_W<'_>`[src]

Bit 4 - Override value for SESSEND The bit field provides the value for USB1_VBUS_DET_STAT[0] if USB_VBUS_DETECT[3] is set to value 1'b1

`pub fn bvalid_override(&mut self) -> BVALID_OVERRIDE_W<'_>`[src]

Bit 5 - Override value for B-Device Session Valid The bit field provides the value for USB1_VBUS_DET_STAT[1] if USB_VBUS_DETECT[3] is set to value 1'b1

`pub fn avalid_override(&mut self) -> AVALID_OVERRIDE_W<'_>`[src]

Bit 6 - Override value for A-Device Session Valid The bit field provides the value for USB1_VBUS_DET_STAT[2] if USB_VBUS_DETECT[3] is set to value 1'b1

`pub fn vbusvalid_override(&mut self) -> VBUSVALID_OVERRIDE_W<'_>`[src]

Bit 7 - Override value for VBUS_VALID signal sent to USB controller The bit field provides the value for VBUS_VALID reported to the USB controller if the value of USB1_VBUS_DETECT[3] is set to 1'b1

`pub fn vbusvalid_sel(&mut self) -> VBUSVALID_SEL_W<'_>`[src]

Bit 8 - Selects the source of the VBUS_VALID signal reported to the USB controller This is one of the bit fields that selects the source of the VBUS_VALID signal reported to the USB controller

`pub fn vbus_source_sel(&mut self) -> VBUS_SOURCE_SEL_W<'_>`[src]

Bits 9:10 - Selects the source of the VBUS_VALID signal reported to the USB controller This is one of the bit fields that selects the source of the VBUS_VALID signal reported to the USB controller

`pub fn id_override_en(&mut self) -> ID_OVERRIDE_EN_W<'_>`[src]

Bit 11 - Enable ID override using the register field. This bit is only used if EXT_ID_OVERRIDE_EN = 1'b0.

`pub fn id_override(&mut self) -> ID_OVERRIDE_W<'_>`[src]

Bit 12 - ID override value.

`pub fn ext_id_override_en(&mut self) -> EXT_ID_OVERRIDE_EN_W<'_>`[src]

Bit 13 - Enable ID override using the pinmuxed value:

`pub fn ext_vbus_override_en(&mut self) -> EXT_VBUS_OVERRIDE_EN_W<'_>`[src]

Bit 14 - Enable VBUS override using the pinmuxed value.

`pub fn vbusvalid_to_sessvalid(&mut self) -> VBUSVALID_TO_SESSVALID_W<'_>`[src]

Bit 18 - Selects the comparator used for VBUS_VALID This bit field controls the comparator used to report the VBUS_VALID results in USB1_VBUS_DETECT[3] between the VBUS_VALID comparator and the Session Valid comparator

`pub fn vbusvalid_5vdetect(&mut self) -> VBUSVALID_5VDETECT_W<'_>`[src]

Bit 19 - no description available

`pub fn pwrup_cmps(&mut self) -> PWRUP_CMPS_W<'_>`[src]

Bits 20:22 - Enables the VBUS_VALID comparator: Powers up the comparator used for the VBUS_VALID detector

`pub fn discharge_vbus(&mut self) -> DISCHARGE_VBUS_W<'_>`[src]

Bit 26 - Controls VBUS discharge resistor This bit field controls a nominal 22kohm resistor between the USB1_VBUS pin and ground

`impl W<u32, Reg<u32, _USB1_VBUS_DETECT_CLR>>`[src]

`pub fn vbusvalid_thresh(&mut self) -> VBUSVALID_THRESH_W<'_>`[src]

Bits 0:2 - Sets the threshold for the VBUSVALID comparator

`pub fn vbus_override_en(&mut self) -> VBUS_OVERRIDE_EN_W<'_>`[src]

Bit 3 - VBUS detect signal override enable

`pub fn sessend_override(&mut self) -> SESSEND_OVERRIDE_W<'_>`[src]

Bit 4 - Override value for SESSEND The bit field provides the value for USB1_VBUS_DET_STAT[0] if USB_VBUS_DETECT[3] is set to value 1'b1

`pub fn bvalid_override(&mut self) -> BVALID_OVERRIDE_W<'_>`[src]

Bit 5 - Override value for B-Device Session Valid The bit field provides the value for USB1_VBUS_DET_STAT[1] if USB_VBUS_DETECT[3] is set to value 1'b1

`pub fn avalid_override(&mut self) -> AVALID_OVERRIDE_W<'_>`[src]

Bit 6 - Override value for A-Device Session Valid The bit field provides the value for USB1_VBUS_DET_STAT[2] if USB_VBUS_DETECT[3] is set to value 1'b1

`pub fn vbusvalid_override(&mut self) -> VBUSVALID_OVERRIDE_W<'_>`[src]

Bit 7 - Override value for VBUS_VALID signal sent to USB controller The bit field provides the value for VBUS_VALID reported to the USB controller if the value of USB1_VBUS_DETECT[3] is set to 1'b1

`pub fn vbusvalid_sel(&mut self) -> VBUSVALID_SEL_W<'_>`[src]

Bit 8 - Selects the source of the VBUS_VALID signal reported to the USB controller This is one of the bit fields that selects the source of the VBUS_VALID signal reported to the USB controller

`pub fn vbus_source_sel(&mut self) -> VBUS_SOURCE_SEL_W<'_>`[src]

Bits 9:10 - Selects the source of the VBUS_VALID signal reported to the USB controller This is one of the bit fields that selects the source of the VBUS_VALID signal reported to the USB controller

`pub fn id_override_en(&mut self) -> ID_OVERRIDE_EN_W<'_>`[src]

Bit 11 - Enable ID override using the register field. This bit is only used if EXT_ID_OVERRIDE_EN = 1'b0.

`pub fn id_override(&mut self) -> ID_OVERRIDE_W<'_>`[src]

Bit 12 - ID override value.

`pub fn ext_id_override_en(&mut self) -> EXT_ID_OVERRIDE_EN_W<'_>`[src]

Bit 13 - Enable ID override using the pinmuxed value:

`pub fn ext_vbus_override_en(&mut self) -> EXT_VBUS_OVERRIDE_EN_W<'_>`[src]

Bit 14 - Enable VBUS override using the pin muxed value.

`pub fn vbusvalid_to_sessvalid(&mut self) -> VBUSVALID_TO_SESSVALID_W<'_>`[src]

Bit 18 - Selects the comparator used for VBUS_VALID This bit field controls the comparator used to report the VBUS_VALID results in USB1_VBUS_DETECT[3] between the VBUS_VALID comparator and the Session Valid comparator

`pub fn vbusvalid_5vdetect(&mut self) -> VBUSVALID_5VDETECT_W<'_>`[src]

Bit 19 - no description available

`pub fn pwrup_cmps(&mut self) -> PWRUP_CMPS_W<'_>`[src]

Bits 20:22 - Enables the VBUS_VALID comparator: Powers up the comparator used for the VBUS_VALID detector

`pub fn discharge_vbus(&mut self) -> DISCHARGE_VBUS_W<'_>`[src]

Bit 26 - Controls VBUS discharge resistor This bit field controls a nominal 22kohm resistor between the USB1_VBUS pin and ground

`impl W<u32, Reg<u32, _USB1_VBUS_DETECT_TOG>>`[src]

`pub fn vbusvalid_thresh(&mut self) -> VBUSVALID_THRESH_W<'_>`[src]

Bits 0:2 - Sets the threshold for the VBUSVALID comparator

`pub fn vbus_override_en(&mut self) -> VBUS_OVERRIDE_EN_W<'_>`[src]

Bit 3 - VBUS detect signal override enable

`pub fn sessend_override(&mut self) -> SESSEND_OVERRIDE_W<'_>`[src]

Bit 4 - Override value for SESSEND The bit field provides the value for USB1_VBUS_DET_STAT[0] if USB_VBUS_DETECT[3] is set to value 1'b1

`pub fn bvalid_override(&mut self) -> BVALID_OVERRIDE_W<'_>`[src]

Bit 5 - Override value for B-Device Session Valid The bit field provides the value for USB1_VBUS_DET_STAT[1] if USB_VBUS_DETECT[3] is set to value 1'b1

`pub fn avalid_override(&mut self) -> AVALID_OVERRIDE_W<'_>`[src]

Bit 6 - Override value for A-Device Session Valid The bit field provides the value for USB1_VBUS_DET_STAT[2] if USB_VBUS_DETECT[3] is set to value 1'b1

`pub fn vbusvalid_override(&mut self) -> VBUSVALID_OVERRIDE_W<'_>`[src]

Bit 7 - Override value for VBUS_VALID signal sent to USB controller The bit field provides the value for VBUS_VALID reported to the USB controller if the value of USB1_VBUS_DETECT[3] is set to 1'b1

`pub fn vbusvalid_sel(&mut self) -> VBUSVALID_SEL_W<'_>`[src]

Bit 8 - Selects the source of the VBUS_VALID signal reported to the USB controller This is one of the bit fields that selects the source of the VBUS_VALID signal reported to the USB controller

`pub fn vbus_source_sel(&mut self) -> VBUS_SOURCE_SEL_W<'_>`[src]

Bits 9:10 - Selects the source of the VBUS_VALID signal reported to the USB controller This is one of the bit fields that selects the source of the VBUS_VALID signal reported to the USB controller

`pub fn id_override_en(&mut self) -> ID_OVERRIDE_EN_W<'_>`[src]

Bit 11 - Enable ID override using the register field. This bit is only used if EXT_ID_OVERRIDE_EN = 1'b0.

`pub fn id_override(&mut self) -> ID_OVERRIDE_W<'_>`[src]

Bit 12 - ID override value.

`pub fn ext_id_override_en(&mut self) -> EXT_ID_OVERRIDE_EN_W<'_>`[src]

Bit 13 - Enable ID override using the pin muxed value.

`pub fn ext_vbus_override_en(&mut self) -> EXT_VBUS_OVERRIDE_EN_W<'_>`[src]

Bit 14 - Enable VBUS override using the pin muxed value.

`pub fn vbusvalid_to_sessvalid(&mut self) -> VBUSVALID_TO_SESSVALID_W<'_>`[src]

Bit 18 - Selects the comparator used for VBUS_VALID This bit field controls the comparator used to report the VBUS_VALID results in USB1_VBUS_DETECT[3] between the VBUS_VALID comparator and the Session Valid comparator

`pub fn vbusvalid_5vdetect(&mut self) -> VBUSVALID_5VDETECT_W<'_>`[src]

Bit 19 - no description available

`pub fn pwrup_cmps(&mut self) -> PWRUP_CMPS_W<'_>`[src]

Bits 20:22 - Enables the VBUS_VALID comparator Powers up the comparator used for the VBUS_VALID detector

`pub fn discharge_vbus(&mut self) -> DISCHARGE_VBUS_W<'_>`[src]

Bit 26 - Controls VBUS discharge resistor This bit field controls a nominal 22kohm resistor between the USB1_VBUS pin and ground

`impl W<u32, Reg<u32, _ANACTRL>>`[src]

`pub fn lvi_en(&mut self) -> LVI_EN_W<'_>`[src]

Bit 1 - Vow voltage detector enable bit.

`pub fn pfd_clk_sel(&mut self) -> PFD_CLK_SEL_W<'_>`[src]

Bits 2:3 - For normal USB operation, this bit field must remain at value 2'b00.

`pub fn dev_pulldown(&mut self) -> DEV_PULLDOWN_W<'_>`[src]

Bit 10 - Setting this field to 1'b1 will enable the 15kohm pulldown resistors on both USB_DP and USB_DM pins

`impl W<u32, Reg<u32, _ANACTRL_SET>>`[src]

`pub fn lvi_en(&mut self) -> LVI_EN_W<'_>`[src]

Bit 1 - Vow voltage detector enable bit.

`pub fn pfd_clk_sel(&mut self) -> PFD_CLK_SEL_W<'_>`[src]

Bits 2:3 - For normal USB operation, this bit field must remain at value 2'b00.

`pub fn dev_pulldown(&mut self) -> DEV_PULLDOWN_W<'_>`[src]

Bit 10 - Setting this field to 1'b1 will enable the 15kohm pulldown resistors on both USB_DP and USB_DM pins

`impl W<u32, Reg<u32, _ANACTRL_CLR>>`[src]

`pub fn lvi_en(&mut self) -> LVI_EN_W<'_>`[src]

Bit 1 - Vow voltage detector enable bit.

`pub fn pfd_clk_sel(&mut self) -> PFD_CLK_SEL_W<'_>`[src]

Bits 2:3 - For normal USB operation, this bit field must remain at value 2'b00.

`pub fn dev_pulldown(&mut self) -> DEV_PULLDOWN_W<'_>`[src]

Bit 10 - Setting this field to 1'b1 will enable the 15kohm pulldown resistors on both USB_DP and USB_DM pins

`impl W<u32, Reg<u32, _ANACTRL_TOG>>`[src]

`pub fn lvi_en(&mut self) -> LVI_EN_W<'_>`[src]

Bit 1 - Vow voltage detector enable bit.

`pub fn pfd_clk_sel(&mut self) -> PFD_CLK_SEL_W<'_>`[src]

Bits 2:3 - For normal USB operation, this bit field must remain at value 2'b00.

`pub fn dev_pulldown(&mut self) -> DEV_PULLDOWN_W<'_>`[src]

Bit 10 - Setting this field to 1'b1 will enable the 15kohm pulldown resistors on both USB_DP and USB_DM pins

`impl W<u32, Reg<u32, _COUNTER_CFG>>`[src]

`pub fn mode(&mut self) -> MODE_W<'_>`[src]

Bits 0:1 - 00: disabled 01: update once.

`pub fn clock_sel(&mut self) -> CLOCK_SEL_W<'_>`[src]

Bits 2:4 - Selects the internal clock on which to compute statistics.

`pub fn shift4x(&mut self) -> SHIFT4X_W<'_>`[src]

Bits 5:7 - To be used to add precision to clock_ratio and determine 'entropy refill'.

`impl W<u32, Reg<u32, _ONLINE_TEST_CFG>>`[src]

`pub fn activate(&mut self) -> ACTIVATE_W<'_>`[src]

Bit 0 - 0: disabled 1: activated Update rythm for VAL depends on COUNTER_CFG if data_sel is set to COUNTER.

`pub fn data_sel(&mut self) -> DATA_SEL_W<'_>`[src]

Bits 1:2 - Selects source on which to apply online test: 00: LSB of COUNTER: raw data from one or all sources of entropy 01: MSB of COUNTER: raw data from one or all sources of entropy 10: RANDOM_NUMBER 11: ENCRYPTED_NUMBER 'activate' should be set to 'disabled' before changing this field.

`impl W<u32, Reg<u32, _CTRL>>`[src]

`pub fn zeroize(&mut self) -> ZEROIZE_W<'_>`[src]

Bit 0 - Begin Zeroize operation for PUF and go to Error state

`pub fn enroll(&mut self) -> ENROLL_W<'_>`[src]

Bit 1 - Begin Enroll operation

`pub fn start(&mut self) -> START_W<'_>`[src]

Bit 2 - Begin Start operation

`pub fn generatekey(&mut self) -> GENERATEKEY_W<'_>`[src]

Bit 3 - Begin Set Intrinsic Key operation

`pub fn setkey(&mut self) -> SETKEY_W<'_>`[src]

Bit 4 - Begin Set User Key operation

`pub fn getkey(&mut self) -> GETKEY_W<'_>`[src]

Bit 6 - Begin Get Key operation

`impl W<u32, Reg<u32, _KEYINDEX>>`[src]

`pub fn keyidx(&mut self) -> KEYIDX_W<'_>`[src]

Bits 0:3 - Key index for Set Key operations

`impl W<u32, Reg<u32, _KEYSIZE>>`[src]

`pub fn keysize(&mut self) -> KEYSIZE_W<'_>`[src]

Bits 0:5 - Key size for Set Key operations

`impl W<u32, Reg<u32, _KEYINPUT>>`[src]

`pub fn keyin(&mut self) -> KEYIN_W<'_>`[src]

Bits 0:31 - Key input data

`impl W<u32, Reg<u32, _CODEINPUT>>`[src]

`pub fn codein(&mut self) -> CODEIN_W<'_>`[src]

Bits 0:31 - AC/KC input data

`impl W<u32, Reg<u32, _IFSTAT>>`[src]

`pub fn error(&mut self) -> ERROR_W<'_>`[src]

Bit 0 - Indicates that an APB error has occurred,Writing logic1 clears the if_error bit

`impl W<u32, Reg<u32, _INTEN>>`[src]

`pub fn readyen(&mut self) -> READYEN_W<'_>`[src]

Bit 0 - Enable corresponding interrupt. Note that bit numbers match those assigned in QK_SR (Quiddikey Status Register)

`pub fn succesen(&mut self) -> SUCCESEN_W<'_>`[src]

Bit 1 - Enable corresponding interrupt. Note that bit numbers match those assigned in QK_SR (Quiddikey Status Register)

`pub fn erroren(&mut self) -> ERROREN_W<'_>`[src]

Bit 2 - Enable corresponding interrupt. Note that bit numbers match those assigned in QK_SR (Quiddikey Status Register)

`pub fn keyinreqen(&mut self) -> KEYINREQEN_W<'_>`[src]

Bit 4 - Enable corresponding interrupt. Note that bit numbers match those assigned in QK_SR (Quiddikey Status Register)

`pub fn keyoutavailen(&mut self) -> KEYOUTAVAILEN_W<'_>`[src]

Bit 5 - Enable corresponding interrupt. Note that bit numbers match those assigned in QK_SR (Quiddikey Status Register)

`pub fn codeinreqen(&mut self) -> CODEINREQEN_W<'_>`[src]

Bit 6 - Enable corresponding interrupt. Note that bit numbers match those assigned in QK_SR (Quiddikey Status Register)

`pub fn codeoutavailen(&mut self) -> CODEOUTAVAILEN_W<'_>`[src]

Bit 7 - Enable corresponding interrupt. Note that bit numbers match those assigned in QK_SR (Quiddikey Status Register)

`impl W<u32, Reg<u32, _INTSTAT>>`[src]

`pub fn ready(&mut self) -> READY_W<'_>`[src]

Bit 0 - Triggers on falling edge of busy, write 1 to clear

`pub fn success(&mut self) -> SUCCESS_W<'_>`[src]

Bit 1 - Level sensitive interrupt, cleared when interrupt source clears

`pub fn error(&mut self) -> ERROR_W<'_>`[src]

Bit 2 - Level sensitive interrupt, cleared when interrupt source clears

`pub fn keyinreq(&mut self) -> KEYINREQ_W<'_>`[src]

Bit 4 - Level sensitive interrupt, cleared when interrupt source clears

`pub fn keyoutavail(&mut self) -> KEYOUTAVAIL_W<'_>`[src]

Bit 5 - Level sensitive interrupt, cleared when interrupt source clears

`pub fn codeinreq(&mut self) -> CODEINREQ_W<'_>`[src]

Bit 6 - Level sensitive interrupt, cleared when interrupt source clears

`pub fn codeoutavail(&mut self) -> CODEOUTAVAIL_W<'_>`[src]

Bit 7 - Level sensitive interrupt, cleared when interrupt source clears

`impl W<u32, Reg<u32, _PWRCTRL>>`[src]

`pub fn ramon(&mut self) -> RAMON_W<'_>`[src]

Bit 0 - Power on the PUF RAM.

`pub fn ramstat(&mut self) -> RAMSTAT_W<'_>`[src]

Bit 1 - PUF RAM status.

`impl W<u32, Reg<u32, _CFG>>`[src]

`pub fn blockenroll_setkey(&mut self) -> BLOCKENROLL_SETKEY_W<'_>`[src]

Bit 0 - Block enroll operation. Write 1 to set, cleared on reset.

`pub fn blockkeyoutput(&mut self) -> BLOCKKEYOUTPUT_W<'_>`[src]

Bit 1 - Block set key operation. Write 1 to set, cleared on reset.

`impl W<u32, Reg<u32, _KEYLOCK>>`[src]

`pub fn key0(&mut self) -> KEY0_W<'_>`[src]

Bits 0:1 - "10:Write access to KEY0MASK, KEYENABLE.KEY0 and KEYRESET.KEY0 is allowed. 00, 01, 11:Write access to KEY0MASK, KEYENABLE.KEY0 and KEYRESET.KEY0 is NOT allowed. Important Note : Once this field is written with a value different from '10', its value can no longer be modified until un Power On Reset occurs."

`pub fn key1(&mut self) -> KEY1_W<'_>`[src]

Bits 2:3 - "10:Write access to KEY1MASK, KEYENABLE.KEY1 and KEYRESET.KEY1 is allowed. 00, 01, 11:Write access to KEY1MASK, KEYENABLE.KEY1 and KEYRESET.KEY1 is NOT allowed. Important Note : Once this field is written with a value different from '10', its value can no longer be modified until un Power On Reset occurs."

`pub fn key2(&mut self) -> KEY2_W<'_>`[src]

Bits 4:5 - "10:Write access to KEY2MASK, KEYENABLE.KEY2 and KEYRESET.KEY2 is allowed. 00, 01, 11:Write access to KEY2MASK, KEYENABLE.KEY2 and KEYRESET.KEY2 is NOT allowed. Important Note : Once this field is written with a value different from '10', its value can no longer be modified until un Power On Reset occurs."

`pub fn key3(&mut self) -> KEY3_W<'_>`[src]

Bits 6:7 - "10:Write access to KEY3MASK, KEYENABLE.KEY3 and KEYRESET.KEY3 is allowed. 00, 01, 11:Write access to KEY3MASK, KEYENABLE.KEY3 and KEYRESET.KEY3 is NOT allowed. Important Note : Once this field is written with a value different from '10', its value can no longer be modified until un Power On Reset occurs."

`impl W<u32, Reg<u32, _KEYENABLE>>`[src]

`pub fn key0(&mut self) -> KEY0_W<'_>`[src]

Bits 0:1 - "10: Data coming out from PUF Index 0 interface are shifted in KEY0 register. 00, 01, 11 : Data coming out from PUF Index 0 interface are NOT shifted in KEY0 register."

`pub fn key1(&mut self) -> KEY1_W<'_>`[src]

Bits 2:3 - "10: Data coming out from PUF Index 0 interface are shifted in KEY1 register. 00, 01, 11 : Data coming out from PUF Index 0 interface are NOT shifted in KEY1 register."

`pub fn key2(&mut self) -> KEY2_W<'_>`[src]

Bits 4:5 - "10: Data coming out from PUF Index 0 interface are shifted in KEY2 register. 00, 01, 11 : Data coming out from PUF Index 0 interface are NOT shifted in KEY2 register."

`pub fn key3(&mut self) -> KEY3_W<'_>`[src]

Bits 6:7 - "10: Data coming out from PUF Index 0 interface are shifted in KEY3 register. 00, 01, 11 : Data coming out from PUF Index 0 interface are NOT shifted in KEY3 register."

`pub fn key(&mut self) -> KEY_W<'_>`[src]

Bits 0:7 - Key destination for PUF key.

`impl W<u32, Reg<u32, _KEYRESET>>`[src]

`pub fn key0(&mut self) -> KEY0_W<'_>`[src]

Bits 0:1 - 10: Reset KEY0 shift register. Self clearing. Must be done before loading any new key.

`pub fn key1(&mut self) -> KEY1_W<'_>`[src]

Bits 2:3 - 10: Reset KEY1 shift register. Self clearing. Must be done before loading any new key.

`pub fn key2(&mut self) -> KEY2_W<'_>`[src]

Bits 4:5 - 10: Reset KEY2 shift register. Self clearing. Must be done before loading any new key.

`pub fn key3(&mut self) -> KEY3_W<'_>`[src]

Bits 6:7 - 10: Reset KEY3 shift register. Self clearing. Must be done before loading any new key.

`impl W<u32, Reg<u32, _IDXBLK_L>>`[src]

`pub fn idx1(&mut self) -> IDX1_W<'_>`[src]

Bits 2:3 - Use to block PUF index 1

`pub fn idx2(&mut self) -> IDX2_W<'_>`[src]

Bits 4:5 - Use to block PUF index 2

`pub fn idx3(&mut self) -> IDX3_W<'_>`[src]

Bits 6:7 - Use to block PUF index 3

`pub fn idx4(&mut self) -> IDX4_W<'_>`[src]

Bits 8:9 - Use to block PUF index 4

`pub fn idx5(&mut self) -> IDX5_W<'_>`[src]

Bits 10:11 - Use to block PUF index 5

`pub fn idx6(&mut self) -> IDX6_W<'_>`[src]

Bits 12:13 - Use to block PUF index 6

`pub fn idx7(&mut self) -> IDX7_W<'_>`[src]

Bits 14:15 - Use to block PUF index 7

`pub fn lock_idx(&mut self) -> LOCK_IDX_W<'_>`[src]

Bits 30:31 - Lock 0 to 7 PUF key indexes

`impl W<u32, Reg<u32, _IDXBLK_H_DP>>`[src]

`pub fn idx8(&mut self) -> IDX8_W<'_>`[src]

Bits 0:1 - Use to block PUF index 8

`pub fn idx9(&mut self) -> IDX9_W<'_>`[src]

Bits 2:3 - Use to block PUF index 9

`pub fn idx10(&mut self) -> IDX10_W<'_>`[src]

Bits 4:5 - Use to block PUF index 10

`pub fn idx11(&mut self) -> IDX11_W<'_>`[src]

Bits 6:7 - Use to block PUF index 11

`pub fn idx12(&mut self) -> IDX12_W<'_>`[src]

Bits 8:9 - Use to block PUF index 12

`pub fn idx13(&mut self) -> IDX13_W<'_>`[src]

Bits 10:11 - Use to block PUF index 13

`pub fn idx14(&mut self) -> IDX14_W<'_>`[src]

Bits 12:13 - Use to block PUF index 14

`pub fn idx15(&mut self) -> IDX15_W<'_>`[src]

Bits 14:15 - Use to block PUF index 15

`impl W<u32, Reg<u32, _KEYMASK>>`[src]

`pub fn keymask(&mut self) -> KEYMASK_W<'_>`[src]

Bits 0:31 - no description available

`impl W<u32, Reg<u32, _IDXBLK_H>>`[src]

`pub fn idx8(&mut self) -> IDX8_W<'_>`[src]

Bits 0:1 - Use to block PUF index 8

`pub fn idx9(&mut self) -> IDX9_W<'_>`[src]

Bits 2:3 - Use to block PUF index 9

`pub fn idx10(&mut self) -> IDX10_W<'_>`[src]

Bits 4:5 - Use to block PUF index 10

`pub fn idx11(&mut self) -> IDX11_W<'_>`[src]

Bits 6:7 - Use to block PUF index 11

`pub fn idx12(&mut self) -> IDX12_W<'_>`[src]

Bits 8:9 - Use to block PUF index 12

`pub fn idx13(&mut self) -> IDX13_W<'_>`[src]

Bits 10:11 - Use to block PUF index 13

`pub fn idx14(&mut self) -> IDX14_W<'_>`[src]

Bits 12:13 - Use to block PUF index 14

`pub fn idx15(&mut self) -> IDX15_W<'_>`[src]

Bits 14:15 - Use to block PUF index 15

`pub fn lock_idx(&mut self) -> LOCK_IDX_W<'_>`[src]

Bits 30:31 - Lock 8 to 15 PUF key indexes

`impl W<u32, Reg<u32, _IDXBLK_L_DP>>`[src]

`pub fn idx1(&mut self) -> IDX1_W<'_>`[src]

Bits 2:3 - Use to block PUF index 1

`pub fn idx2(&mut self) -> IDX2_W<'_>`[src]

Bits 4:5 - Use to block PUF index 2

`pub fn idx3(&mut self) -> IDX3_W<'_>`[src]

Bits 6:7 - Use to block PUF index 3

`pub fn idx4(&mut self) -> IDX4_W<'_>`[src]

Bits 8:9 - Use to block PUF index 4

`pub fn idx5(&mut self) -> IDX5_W<'_>`[src]

Bits 10:11 - Use to block PUF index 5

`pub fn idx6(&mut self) -> IDX6_W<'_>`[src]

Bits 12:13 - Use to block PUF index 6

`pub fn idx7(&mut self) -> IDX7_W<'_>`[src]

Bits 14:15 - Use to block PUF index 7

`impl W<u32, Reg<u32, _LUT_INP_MUX>>`[src]

`pub fn lutn_inpx(&mut self) -> LUTN_INPX_W<'_>`[src]

Bits 0:5 - Selects the input source to be connected to LUT0 input0. For each LUT, the slot associated with the output from LUTn itself is tied low.

`impl W<u32, Reg<u32, _LUT_TRUTH>>`[src]

`pub fn lutn_truth(&mut self) -> LUTN_TRUTH_W<'_>`[src]

Bits 0:31 - Specifies the Truth Table contents for LUT0..

`impl W<u32, Reg<u32, _WAKEINT_CTRL>>`[src]

`pub fn mask(&mut self) -> MASK_W<'_>`[src]

Bits 0:7 - Interrupt mask (which of the 8 PLU Outputs contribute to interrupt)

`pub fn filter_mode(&mut self) -> FILTER_MODE_W<'_>`[src]

Bits 8:9 - control input of the PLU, add filtering for glitch.

`pub fn filter_clksel(&mut self) -> FILTER_CLKSEL_W<'_>`[src]

Bits 10:11 - hclk is divided by 2**filter_clksel.

`pub fn latch_enable(&mut self) -> LATCH_ENABLE_W<'_>`[src]

Bit 12 - latch the interrupt , then can be cleared with next bit INTR_CLEAR

`pub fn intr_clear(&mut self) -> INTR_CLEAR_W<'_>`[src]

Bit 13 - Write to clear wakeint_latched

`impl W<u32, Reg<u32, _OUTPUT_MUX>>`[src]

`pub fn outputn(&mut self) -> OUTPUTN_W<'_>`[src]

Bits 0:4 - Selects the source to be connected to PLU Output 0.

`impl W<u32, Reg<u32, _CFG>>`[src]

`pub fn periphreqen(&mut self) -> PERIPHREQEN_W<'_>`[src]

Bit 0 - Peripheral request Enable. If a DMA channel is used to perform a memory-to-memory move, any peripheral DMA request associated with that channel can be disabled to prevent any interaction between the peripheral and the DMA controller.

`pub fn hwtrigen(&mut self) -> HWTRIGEN_W<'_>`[src]

Bit 1 - Hardware Triggering Enable for this channel.

`pub fn trigpol(&mut self) -> TRIGPOL_W<'_>`[src]

Bit 4 - Trigger Polarity. Selects the polarity of a hardware trigger for this channel.

`pub fn trigtype(&mut self) -> TRIGTYPE_W<'_>`[src]

Bit 5 - Trigger Type. Selects hardware trigger as edge triggered or level triggered.

`pub fn trigburst(&mut self) -> TRIGBURST_W<'_>`[src]

Bit 6 - Trigger Burst. Selects whether hardware triggers cause a single or burst transfer.

`pub fn burstpower(&mut self) -> BURSTPOWER_W<'_>`[src]

Bits 8:11 - Burst Power is used in two ways. It always selects the address wrap size when SRCBURSTWRAP and/or DSTBURSTWRAP modes are selected (see descriptions elsewhere in this register). When the TRIGBURST field elsewhere in this register = 1, Burst Power selects how many transfers are performed for each DMA trigger. This can be used, for example, with peripherals that contain a FIFO that can initiate a DMA operation when the FIFO reaches a certain level. 0000: Burst size = 1 (20). 0001: Burst size = 2 (21). 0010: Burst size = 4 (22). 1010: Burst size = 1024 (210). This corresponds to the maximum supported transfer count. others: not supported. The total transfer length as defined in the XFERCOUNT bits in the XFERCFG register must be an even multiple of the burst size.

`pub fn srcburstwrap(&mut self) -> SRCBURSTWRAP_W<'_>`[src]

Bit 14 - Source Burst Wrap. When enabled, the source data address for the DMA is 'wrapped', meaning that the source address range for each burst will be the same. As an example, this could be used to read several sequential registers from a peripheral for each DMA burst, reading the same registers again for each burst.

`pub fn dstburstwrap(&mut self) -> DSTBURSTWRAP_W<'_>`[src]

Bit 15 - Destination Burst Wrap. When enabled, the destination data address for the DMA is 'wrapped', meaning that the destination address range for each burst will be the same. As an example, this could be used to write several sequential registers to a peripheral for each DMA burst, writing the same registers again for each burst.

`pub fn chpriority(&mut self) -> CHPRIORITY_W<'_>`[src]

Bits 16:18 - Priority of this channel when multiple DMA requests are pending. Eight priority levels are supported: 0x0 = highest priority. 0x7 = lowest priority.

`impl W<u32, Reg<u32, _XFERCFG>>`[src]

`pub fn cfgvalid(&mut self) -> CFGVALID_W<'_>`[src]

Bit 0 - Configuration Valid flag. This bit indicates whether the current channel descriptor is valid and can potentially be acted upon, if all other activation criteria are fulfilled.

`pub fn reload(&mut self) -> RELOAD_W<'_>`[src]

Bit 1 - Indicates whether the channel's control structure will be reloaded when the current descriptor is exhausted. Reloading allows ping-pong and linked transfers.

`pub fn swtrig(&mut self) -> SWTRIG_W<'_>`[src]

Bit 2 - Software Trigger.

`pub fn clrtrig(&mut self) -> CLRTRIG_W<'_>`[src]

Bit 3 - Clear Trigger.

`pub fn setinta(&mut self) -> SETINTA_W<'_>`[src]

Bit 4 - Set Interrupt flag A for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention, interrupt A may be used when only one interrupt flag is needed.

`pub fn setintb(&mut self) -> SETINTB_W<'_>`[src]

Bit 5 - Set Interrupt flag B for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention, interrupt A may be used when only one interrupt flag is needed.

`pub fn width(&mut self) -> WIDTH_W<'_>`[src]

Bits 8:9 - Transfer width used for this DMA channel.

`pub fn srcinc(&mut self) -> SRCINC_W<'_>`[src]

Bits 12:13 - Determines whether the source address is incremented for each DMA transfer.

`pub fn dstinc(&mut self) -> DSTINC_W<'_>`[src]

Bits 14:15 - Determines whether the destination address is incremented for each DMA transfer.

`pub fn xfercount(&mut self) -> XFERCOUNT_W<'_>`[src]

Bits 16:25 - Total number of transfers to be performed, minus 1 encoded. The number of bytes transferred is: (XFERCOUNT + 1) x data width (as defined by the WIDTH field). The DMA controller uses this bit field during transfer to count down. Hence, it cannot be used by software to read back the size of the transfer, for instance, in an interrupt handler. 0x0 = a total of 1 transfer will be performed. 0x1 = a total of 2 transfers will be performed. 0x3FF = a total of 1,024 transfers will be performed.

`impl W<u32, Reg<u32, _CTRL>>`[src]

`pub fn enable(&mut self) -> ENABLE_W<'_>`[src]

Bit 0 - DMA controller master enable.

`impl W<u32, Reg<u32, _SRAMBASE>>`[src]

`pub fn offset(&mut self) -> OFFSET_W<'_>`[src]

Bits 9:31 - Address bits 31:9 of the beginning of the DMA descriptor table. For 18 channels, the table must begin on a 512 byte boundary.

`impl W<u32, Reg<u32, _ENABLESET0>>`[src]

`pub fn ena(&mut self) -> ENA_W<'_>`[src]

Bits 0:31 - Enable for DMA channels. Bit n enables or disables DMA channel n. The number of bits = number of DMA channels in this device. Other bits are reserved. 0 = disabled. 1 = enabled.

`impl W<u32, Reg<u32, _ENABLECLR0>>`[src]

`pub fn clr(&mut self) -> CLR_W<'_>`[src]

Bits 0:31 - Writing ones to this register clears the corresponding bits in ENABLESET0. Bit n clears the channel enable bit n. The number of bits = number of DMA channels in this device. Other bits are reserved.

`impl W<u32, Reg<u32, _ERRINT0>>`[src]

`pub fn err(&mut self) -> ERR_W<'_>`[src]

Bits 0:31 - Error Interrupt flag for DMA channel n. Bit n corresponds to DMA channel n. The number of bits = number of DMA channels in this device. Other bits are reserved. 0 = error interrupt is not active. 1 = error interrupt is active.

`impl W<u32, Reg<u32, _INTENSET0>>`[src]

`pub fn inten(&mut self) -> INTEN_W<'_>`[src]

Bits 0:31 - Interrupt Enable read and set for DMA channel n. Bit n corresponds to DMA channel n. The number of bits = number of DMA channels in this device. Other bits are reserved. 0 = interrupt for DMA channel is disabled. 1 = interrupt for DMA channel is enabled.

`impl W<u32, Reg<u32, _INTENCLR0>>`[src]

`pub fn clr(&mut self) -> CLR_W<'_>`[src]

Bits 0:31 - Writing ones to this register clears corresponding bits in the INTENSET0. Bit n corresponds to DMA channel n. The number of bits = number of DMA channels in this device. Other bits are reserved.

`impl W<u32, Reg<u32, _INTA0>>`[src]

`pub fn ia(&mut self) -> IA_W<'_>`[src]

Bits 0:31 - Interrupt A status for DMA channel n. Bit n corresponds to DMA channel n. The number of bits = number of DMA channels in this device. Other bits are reserved. 0 = the DMA channel interrupt A is not active. 1 = the DMA channel interrupt A is active.

`impl W<u32, Reg<u32, _INTB0>>`[src]

`pub fn ib(&mut self) -> IB_W<'_>`[src]

Bits 0:31 - Interrupt B status for DMA channel n. Bit n corresponds to DMA channel n. The number of bits = number of DMA channels in this device. Other bits are reserved. 0 = the DMA channel interrupt B is not active. 1 = the DMA channel interrupt B is active.

`impl W<u32, Reg<u32, _SETVALID0>>`[src]

`pub fn sv(&mut self) -> SV_W<'_>`[src]

Bits 0:31 - SETVALID control for DMA channel n. Bit n corresponds to DMA channel n. The number of bits = number of DMA channels in this device. Other bits are reserved. 0 = no effect. 1 = sets the VALIDPENDING control bit for DMA channel n

`impl W<u32, Reg<u32, _SETTRIG0>>`[src]

`pub fn trig(&mut self) -> TRIG_W<'_>`[src]

Bits 0:31 - Set Trigger control bit for DMA channel 0. Bit n corresponds to DMA channel n. The number of bits = number of DMA channels in this device. Other bits are reserved. 0 = no effect. 1 = sets the TRIG bit for DMA channel n.

`impl W<u32, Reg<u32, _ABORT0>>`[src]

`pub fn abortctrl(&mut self) -> ABORTCTRL_W<'_>`[src]

Bits 0:31 - Abort control for DMA channel 0. Bit n corresponds to DMA channel n. 0 = no effect. 1 = aborts DMA operations on channel n.

`impl W<u32, Reg<u32, _EV_STATE>>`[src]

`pub fn statemskn(&mut self) -> STATEMSKN_W<'_>`[src]

Bits 0:15 - If bit m is one, event n happens in state m of the counter selected by the HEVENT bit (n = event number, m = state number; state 0 = bit 0, state 1= bit 1, etc.). The number of bits = number of states in this SCT.

`impl W<u32, Reg<u32, _EV_CTRL>>`[src]

`pub fn matchsel(&mut self) -> MATCHSEL_W<'_>`[src]

Bits 0:3 - Selects the Match register associated with this event (if any). A match can occur only when the counter selected by the HEVENT bit is running.

`pub fn hevent(&mut self) -> HEVENT_W<'_>`[src]

Bit 4 - Select L/H counter. Do not set this bit if UNIFY = 1.

`pub fn outsel(&mut self) -> OUTSEL_W<'_>`[src]

Bit 5 - Input/output select

`pub fn iosel(&mut self) -> IOSEL_W<'_>`[src]

Bits 6:9 - Selects the input or output signal number associated with this event (if any). Do not select an input in this register if CKMODE is 1x. In this case the clock input is an implicit ingredient of every event.

`pub fn iocond(&mut self) -> IOCOND_W<'_>`[src]

Bits 10:11 - Selects the I/O condition for event n. (The detection of edges on outputs lag the conditions that switch the outputs by one SCT clock). In order to guarantee proper edge/state detection, an input must have a minimum pulse width of at least one SCT clock period .

`pub fn combmode(&mut self) -> COMBMODE_W<'_>`[src]

Bits 12:13 - Selects how the specified match and I/O condition are used and combined.

`pub fn stateld(&mut self) -> STATELD_W<'_>`[src]

Bit 14 - This bit controls how the STATEV value modifies the state selected by HEVENT when this event is the highest-numbered event occurring for that state.

`pub fn statev(&mut self) -> STATEV_W<'_>`[src]

Bits 15:19 - This value is loaded into or added to the state selected by HEVENT, depending on STATELD, when this event is the highest-numbered event occurring for that state. If STATELD and STATEV are both zero, there is no change to the STATE value.

`pub fn matchmem(&mut self) -> MATCHMEM_W<'_>`[src]

Bit 20 - If this bit is one and the COMBMODE field specifies a match component to the triggering of this event, then a match is considered to be active whenever the counter value is GREATER THAN OR EQUAL TO the value specified in the match register when counting up, LESS THEN OR EQUAL TO the match value when counting down. If this bit is zero, a match is only be active during the cycle when the counter is equal to the match value.

`pub fn direction(&mut self) -> DIRECTION_W<'_>`[src]

Bits 21:22 - Direction qualifier for event generation. This field only applies when the counters are operating in BIDIR mode. If BIDIR = 0, the SCT ignores this field. Value 0x3 is reserved.

`impl W<u32, Reg<u32, _OUT_SET>>`[src]

`pub fn set(&mut self) -> SET_W<'_>`[src]

Bits 0:15 - A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) output 0 = bit 0, output 1 = bit 1, etc. The number of bits = number of events in this SCT. When the counter is used in bi-directional mode, it is possible to reverse the action specified by the output set and clear registers when counting down, See the OUTPUTCTRL register.

`impl W<u32, Reg<u32, _OUT_CLR>>`[src]

`pub fn clr(&mut self) -> CLR_W<'_>`[src]

Bits 0:15 - A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1, etc. The number of bits = number of events in this SCT. When the counter is used in bi-directional mode, it is possible to reverse the action specified by the output set and clear registers when counting down, See the OUTPUTCTRL register.

`impl W<u32, Reg<u32, _CONFIG>>`[src]

`pub fn unify(&mut self) -> UNIFY_W<'_>`[src]

Bit 0 - SCT operation

`pub fn clkmode(&mut self) -> CLKMODE_W<'_>`[src]

Bits 1:2 - SCT clock mode

`pub fn cksel(&mut self) -> CKSEL_W<'_>`[src]

Bits 3:6 - SCT clock select. The specific functionality of the designated input/edge is dependent on the CLKMODE bit selection in this register.

`pub fn noreload_l(&mut self) -> NORELOAD_L_W<'_>`[src]

Bit 7 - A 1 in this bit prevents the lower match registers from being reloaded from their respective reload registers. Setting this bit eliminates the need to write to the reload registers MATCHREL if the match values are fixed. Software can write to set or clear this bit at any time. This bit applies to both the higher and lower registers when the UNIFY bit is set.

`pub fn noreload_h(&mut self) -> NORELOAD_H_W<'_>`[src]

Bit 8 - A 1 in this bit prevents the higher match registers from being reloaded from their respective reload registers. Setting this bit eliminates the need to write to the reload registers MATCHREL if the match values are fixed. Software can write to set or clear this bit at any time. This bit is not used when the UNIFY bit is set.

`pub fn insync(&mut self) -> INSYNC_W<'_>`[src]

Bits 9:12 - Synchronization for input N (bit 9 = input 0, bit 10 = input 1,, bit 12 = input 3); all other bits are reserved. A 1 in one of these bits subjects the corresponding input to synchronization to the SCT clock, before it is used to create an event. If an input is known to already be synchronous to the SCT clock, this bit may be set to 0 for faster input response. (Note: The SCT clock is the system clock for CKMODEs 0-2. It is the selected, asynchronous SCT input clock for CKMODE3). Note that the INSYNC field only affects inputs used for event generation. It does not apply to the clock input specified in the CKSEL field.

`pub fn autolimit_l(&mut self) -> AUTOLIMIT_L_W<'_>`[src]

Bit 17 - A one in this bit causes a match on match register 0 to be treated as a de-facto LIMIT condition without the need to define an associated event. As with any LIMIT event, this automatic limit causes the counter to be cleared to zero in unidirectional mode or to change the direction of count in bi-directional mode. Software can write to set or clear this bit at any time. This bit applies to both the higher and lower registers when the UNIFY bit is set.

`pub fn autolimit_h(&mut self) -> AUTOLIMIT_H_W<'_>`[src]

Bit 18 - A one in this bit will cause a match on match register 0 to be treated as a de-facto LIMIT condition without the need to define an associated event. As with any LIMIT event, this automatic limit causes the counter to be cleared to zero in unidirectional mode or to change the direction of count in bi-directional mode. Software can write to set or clear this bit at any time. This bit is not used when the UNIFY bit is set.

`impl W<u32, Reg<u32, _CTRL>>`[src]

`pub fn down_l(&mut self) -> DOWN_L_W<'_>`[src]

Bit 0 - This bit is 1 when the L or unified counter is counting down. Hardware sets this bit when the counter is counting up, counter limit occurs, and BIDIR = 1.Hardware clears this bit when the counter is counting down and a limit condition occurs or when the counter reaches 0.

`pub fn stop_l(&mut self) -> STOP_L_W<'_>`[src]

Bit 1 - When this bit is 1 and HALT is 0, the L or unified counter does not run, but I/O events related to the counter can occur. If a designated start event occurs, this bit is cleared and counting resumes.

`pub fn halt_l(&mut self) -> HALT_L_W<'_>`[src]

Bit 2 - When this bit is 1, the L or unified counter does not run and no events can occur. A reset sets this bit. When the HALT_L bit is one, the STOP_L bit is cleared. It is possible to remove the halt condition while keeping the SCT in the stop condition (not running) with a single write to this register to simultaneously clear the HALT bit and set the STOP bit. Once set, only software can clear this bit to restore counter operation. This bit is set on reset.

`pub fn clrctr_l(&mut self) -> CLRCTR_L_W<'_>`[src]

Bit 3 - Writing a 1 to this bit clears the L or unified counter. This bit always reads as 0.

`pub fn bidir_l(&mut self) -> BIDIR_L_W<'_>`[src]

Bit 4 - L or unified counter direction select

`pub fn pre_l(&mut self) -> PRE_L_W<'_>`[src]

Bits 5:12 - Specifies the factor by which the SCT clock is prescaled to produce the L or unified counter clock. The counter clock is clocked at the rate of the SCT clock divided by PRE_L+1. Clear the counter (by writing a 1 to the CLRCTR bit) whenever changing the PRE value.

`pub fn down_h(&mut self) -> DOWN_H_W<'_>`[src]

Bit 16 - This bit is 1 when the H counter is counting down. Hardware sets this bit when the counter is counting, a counter limit condition occurs, and BIDIR is 1. Hardware clears this bit when the counter is counting down and a limit condition occurs or when the counter reaches 0.

`pub fn stop_h(&mut self) -> STOP_H_W<'_>`[src]

Bit 17 - When this bit is 1 and HALT is 0, the H counter does not, run but I/O events related to the counter can occur. If such an event matches the mask in the Start register, this bit is cleared and counting resumes.

`pub fn halt_h(&mut self) -> HALT_H_W<'_>`[src]

Bit 18 - When this bit is 1, the H counter does not run and no events can occur. A reset sets this bit. When the HALT_H bit is one, the STOP_H bit is cleared. It is possible to remove the halt condition while keeping the SCT in the stop condition (not running) with a single write to this register to simultaneously clear the HALT bit and set the STOP bit. Once set, this bit can only be cleared by software to restore counter operation. This bit is set on reset.

`pub fn clrctr_h(&mut self) -> CLRCTR_H_W<'_>`[src]

Bit 19 - Writing a 1 to this bit clears the H counter. This bit always reads as 0.

`pub fn bidir_h(&mut self) -> BIDIR_H_W<'_>`[src]

Bit 20 - Direction select

`pub fn pre_h(&mut self) -> PRE_H_W<'_>`[src]

Bits 21:28 - Specifies the factor by which the SCT clock is prescaled to produce the H counter clock. The counter clock is clocked at the rate of the SCT clock divided by PRELH+1. Clear the counter (by writing a 1 to the CLRCTR bit) whenever changing the PRE value.

`impl W<u32, Reg<u32, _LIMIT>>`[src]

`pub fn limmsk_l(&mut self) -> LIMMSK_L_W<'_>`[src]

Bits 0:15 - If bit n is one, event n is used as a counter limit for the L or unified counter (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of events in this SCT.

`pub fn limmsk_h(&mut self) -> LIMMSK_H_W<'_>`[src]

Bits 16:31 - If bit n is one, event n is used as a counter limit for the H counter (event 0 = bit 16, event 1 = bit 17, etc.). The number of bits = number of events in this SCT.

`impl W<u32, Reg<u32, _HALT>>`[src]

`pub fn haltmsk_l(&mut self) -> HALTMSK_L_W<'_>`[src]

Bits 0:15 - If bit n is one, event n sets the HALT_L bit in the CTRL register (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of events in this SCT.

`pub fn haltmsk_h(&mut self) -> HALTMSK_H_W<'_>`[src]

Bits 16:31 - If bit n is one, event n sets the HALT_H bit in the CTRL register (event 0 = bit 16, event 1 = bit 17, etc.). The number of bits = number of events in this SCT.

`impl W<u32, Reg<u32, _STOP>>`[src]

`pub fn stopmsk_l(&mut self) -> STOPMSK_L_W<'_>`[src]

Bits 0:15 - If bit n is one, event n sets the STOP_L bit in the CTRL register (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of events in this SCT.

`pub fn stopmsk_h(&mut self) -> STOPMSK_H_W<'_>`[src]

Bits 16:31 - If bit n is one, event n sets the STOP_H bit in the CTRL register (event 0 = bit 16, event 1 = bit 17, etc.). The number of bits = number of events in this SCT.

`impl W<u32, Reg<u32, _START>>`[src]

`pub fn startmsk_l(&mut self) -> STARTMSK_L_W<'_>`[src]

Bits 0:15 - If bit n is one, event n clears the STOP_L bit in the CTRL register (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of events in this SCT.

`pub fn startmsk_h(&mut self) -> STARTMSK_H_W<'_>`[src]

Bits 16:31 - If bit n is one, event n clears the STOP_H bit in the CTRL register (event 0 = bit 16, event 1 = bit 17, etc.). The number of bits = number of events in this SCT.

`impl W<u32, Reg<u32, _COUNT>>`[src]

`pub fn ctr_l(&mut self) -> CTR_L_W<'_>`[src]

Bits 0:15 - When UNIFY = 0, read or write the 16-bit L counter value. When UNIFY = 1, read or write the lower 16 bits of the 32-bit unified counter.

`pub fn ctr_h(&mut self) -> CTR_H_W<'_>`[src]

Bits 16:31 - When UNIFY = 0, read or write the 16-bit H counter value. When UNIFY = 1, read or write the upper 16 bits of the 32-bit unified counter.

`impl W<u32, Reg<u32, _STATE>>`[src]

`pub fn state_l(&mut self) -> STATE_L_W<'_>`[src]

Bits 0:4 - State variable.

`pub fn state_h(&mut self) -> STATE_H_W<'_>`[src]

Bits 16:20 - State variable.

`impl W<u32, Reg<u32, _REGMODE>>`[src]

`pub fn regmod_l(&mut self) -> REGMOD_L_W<'_>`[src]

Bits 0:15 - Each bit controls one match/capture register (register 0 = bit 0, register 1 = bit 1, etc.). The number of bits = number of match/captures in this SCT. 0 = register operates as match register. 1 = register operates as capture register.

`pub fn regmod_h(&mut self) -> REGMOD_H_W<'_>`[src]

Bits 16:31 - Each bit controls one match/capture register (register 0 = bit 16, register 1 = bit 17, etc.). The number of bits = number of match/captures in this SCT. 0 = register operates as match registers. 1 = register operates as capture registers.

`impl W<u32, Reg<u32, _OUTPUT>>`[src]

`pub fn out(&mut self) -> OUT_W<'_>`[src]

Bits 0:15 - Writing a 1 to bit n forces the corresponding output HIGH. Writing a 0 forces the corresponding output LOW (output 0 = bit 0, output 1 = bit 1, etc.). The number of bits = number of outputs in this SCT.

`impl W<u32, Reg<u32, _OUTPUTDIRCTRL>>`[src]

`pub fn setclr0(&mut self) -> SETCLR0_W<'_>`[src]

Bits 0:1 - Set/clear operation on output 0. Value 0x3 is reserved. Do not program this value.

`pub fn setclr1(&mut self) -> SETCLR1_W<'_>`[src]

Bits 2:3 - Set/clear operation on output 1. Value 0x3 is reserved. Do not program this value.

`pub fn setclr2(&mut self) -> SETCLR2_W<'_>`[src]

Bits 4:5 - Set/clear operation on output 2. Value 0x3 is reserved. Do not program this value.

`pub fn setclr3(&mut self) -> SETCLR3_W<'_>`[src]

Bits 6:7 - Set/clear operation on output 3. Value 0x3 is reserved. Do not program this value.

`pub fn setclr4(&mut self) -> SETCLR4_W<'_>`[src]

Bits 8:9 - Set/clear operation on output 4. Value 0x3 is reserved. Do not program this value.

`pub fn setclr5(&mut self) -> SETCLR5_W<'_>`[src]

Bits 10:11 - Set/clear operation on output 5. Value 0x3 is reserved. Do not program this value.

`pub fn setclr6(&mut self) -> SETCLR6_W<'_>`[src]

Bits 12:13 - Set/clear operation on output 6. Value 0x3 is reserved. Do not program this value.

`pub fn setclr7(&mut self) -> SETCLR7_W<'_>`[src]

Bits 14:15 - Set/clear operation on output 7. Value 0x3 is reserved. Do not program this value.

`pub fn setclr8(&mut self) -> SETCLR8_W<'_>`[src]

Bits 16:17 - Set/clear operation on output 8. Value 0x3 is reserved. Do not program this value.

`pub fn setclr9(&mut self) -> SETCLR9_W<'_>`[src]

Bits 18:19 - Set/clear operation on output 9. Value 0x3 is reserved. Do not program this value.

`pub fn setclr10(&mut self) -> SETCLR10_W<'_>`[src]

Bits 20:21 - Set/clear operation on output 10. Value 0x3 is reserved. Do not program this value.

`pub fn setclr11(&mut self) -> SETCLR11_W<'_>`[src]

Bits 22:23 - Set/clear operation on output 11. Value 0x3 is reserved. Do not program this value.

`pub fn setclr12(&mut self) -> SETCLR12_W<'_>`[src]

Bits 24:25 - Set/clear operation on output 12. Value 0x3 is reserved. Do not program this value.

`pub fn setclr13(&mut self) -> SETCLR13_W<'_>`[src]

Bits 26:27 - Set/clear operation on output 13. Value 0x3 is reserved. Do not program this value.

`pub fn setclr14(&mut self) -> SETCLR14_W<'_>`[src]

Bits 28:29 - Set/clear operation on output 14. Value 0x3 is reserved. Do not program this value.

`pub fn setclr15(&mut self) -> SETCLR15_W<'_>`[src]

Bits 30:31 - Set/clear operation on output 15. Value 0x3 is reserved. Do not program this value.

`impl W<u32, Reg<u32, _RES>>`[src]

`pub fn o0res(&mut self) -> O0RES_W<'_>`[src]

Bits 0:1 - Effect of simultaneous set and clear on output 0.

`pub fn o1res(&mut self) -> O1RES_W<'_>`[src]

Bits 2:3 - Effect of simultaneous set and clear on output 1.

`pub fn o2res(&mut self) -> O2RES_W<'_>`[src]

Bits 4:5 - Effect of simultaneous set and clear on output 2.

`pub fn o3res(&mut self) -> O3RES_W<'_>`[src]

Bits 6:7 - Effect of simultaneous set and clear on output 3.

`pub fn o4res(&mut self) -> O4RES_W<'_>`[src]

Bits 8:9 - Effect of simultaneous set and clear on output 4.

`pub fn o5res(&mut self) -> O5RES_W<'_>`[src]

Bits 10:11 - Effect of simultaneous set and clear on output 5.

`pub fn o6res(&mut self) -> O6RES_W<'_>`[src]

Bits 12:13 - Effect of simultaneous set and clear on output 6.

`pub fn o7res(&mut self) -> O7RES_W<'_>`[src]

Bits 14:15 - Effect of simultaneous set and clear on output 7.

`pub fn o8res(&mut self) -> O8RES_W<'_>`[src]

Bits 16:17 - Effect of simultaneous set and clear on output 8.

`pub fn o9res(&mut self) -> O9RES_W<'_>`[src]

Bits 18:19 - Effect of simultaneous set and clear on output 9.

`pub fn o10res(&mut self) -> O10RES_W<'_>`[src]

Bits 20:21 - Effect of simultaneous set and clear on output 10.

`pub fn o11res(&mut self) -> O11RES_W<'_>`[src]

Bits 22:23 - Effect of simultaneous set and clear on output 11.

`pub fn o12res(&mut self) -> O12RES_W<'_>`[src]

Bits 24:25 - Effect of simultaneous set and clear on output 12.

`pub fn o13res(&mut self) -> O13RES_W<'_>`[src]

Bits 26:27 - Effect of simultaneous set and clear on output 13.

`pub fn o14res(&mut self) -> O14RES_W<'_>`[src]

Bits 28:29 - Effect of simultaneous set and clear on output 14.

`pub fn o15res(&mut self) -> O15RES_W<'_>`[src]

Bits 30:31 - Effect of simultaneous set and clear on output 15.

`impl W<u32, Reg<u32, _DMAREQ0>>`[src]

`pub fn dev_0(&mut self) -> DEV_0_W<'_>`[src]

Bits 0:15 - If bit n is one, event n triggers DMA request 0 (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of events in this SCT.

`pub fn drl0(&mut self) -> DRL0_W<'_>`[src]

Bit 30 - A 1 in this bit triggers DMA request 0 when it loads the MATCH_L/Unified registers from the RELOAD_L/Unified registers.

`pub fn drq0(&mut self) -> DRQ0_W<'_>`[src]

Bit 31 - This read-only bit indicates the state of DMA Request 0. Note that if the related DMA channel is enabled and properly set up, it is unlikely that software will see this flag, it will be cleared rapidly by the DMA service. The flag remaining set could point to an issue with DMA setup.

`impl W<u32, Reg<u32, _DMAREQ1>>`[src]

`pub fn dev_1(&mut self) -> DEV_1_W<'_>`[src]

Bits 0:15 - If bit n is one, event n triggers DMA request 1 (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of events in this SCT.

`pub fn drl1(&mut self) -> DRL1_W<'_>`[src]

Bit 30 - A 1 in this bit triggers DMA request 1 when it loads the Match L/Unified registers from the Reload L/Unified registers.

`pub fn drq1(&mut self) -> DRQ1_W<'_>`[src]

Bit 31 - This read-only bit indicates the state of DMA Request 1. Note that if the related DMA channel is enabled and properly set up, it is unlikely that software will see this flag, it will be cleared rapidly by the DMA service. The flag remaining set could point to an issue with DMA setup.

`impl W<u32, Reg<u32, _EVEN>>`[src]

`pub fn ien(&mut self) -> IEN_W<'_>`[src]

Bits 0:15 - The SCT requests an interrupt when bit n of this register and the event flag register are both one (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of events in this SCT.

`impl W<u32, Reg<u32, _EVFLAG>>`[src]

`pub fn flag(&mut self) -> FLAG_W<'_>`[src]

Bits 0:15 - Bit n is one if event n has occurred since reset or a 1 was last written to this bit (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of events in this SCT.

`impl W<u32, Reg<u32, _CONEN>>`[src]

`pub fn ncen(&mut self) -> NCEN_W<'_>`[src]

Bits 0:15 - The SCT requests an interrupt when bit n of this register and the SCT conflict flag register are both one (output 0 = bit 0, output 1 = bit 1, etc.). The number of bits = number of outputs in this SCT.

`impl W<u32, Reg<u32, _CONFLAG>>`[src]

`pub fn ncflag(&mut self) -> NCFLAG_W<'_>`[src]

Bits 0:15 - Bit n is one if a no-change conflict event occurred on output n since reset or a 1 was last written to this bit (output 0 = bit 0, output 1 = bit 1, etc.). The number of bits = number of outputs in this SCT.

`pub fn buserrl(&mut self) -> BUSERRL_W<'_>`[src]

Bit 30 - The most recent bus error from this SCT involved writing CTR L/Unified, STATE L/Unified, MATCH L/Unified, or the Output register when the L/U counter was not halted. A word write to certain L and H registers can be half successful and half unsuccessful.

`pub fn buserrh(&mut self) -> BUSERRH_W<'_>`[src]

Bit 31 - The most recent bus error from this SCT involved writing CTR H, STATE H, MATCH H, or the Output register when the H counter was not halted.

`impl W<u32, Reg<u32, _CAP0>>`[src]

`pub fn capn_l(&mut self) -> CAPN_L_W<'_>`[src]

Bits 0:15 - When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the lower 16 bits of the 32-bit value at which this register was last captured.

`pub fn capn_h(&mut self) -> CAPN_H_W<'_>`[src]

Bits 16:31 - When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the upper 16 bits of the 32-bit value at which this register was last captured.

`impl W<u32, Reg<u32, _MATCH0>>`[src]

`pub fn matchn_l(&mut self) -> MATCHN_L_W<'_>`[src]

Bits 0:15 - When UNIFY = 0, read or write the 16-bit value to be compared to the L counter. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be compared to the unified counter.

`pub fn matchn_h(&mut self) -> MATCHN_H_W<'_>`[src]

Bits 16:31 - When UNIFY = 0, read or write the 16-bit value to be compared to the H counter. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be compared to the unified counter.

`impl W<u32, Reg<u32, _CAP1>>`[src]

`pub fn capn_l(&mut self) -> CAPN_L_W<'_>`[src]

Bits 0:15 - When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the lower 16 bits of the 32-bit value at which this register was last captured.

`pub fn capn_h(&mut self) -> CAPN_H_W<'_>`[src]

Bits 16:31 - When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the upper 16 bits of the 32-bit value at which this register was last captured.

`impl W<u32, Reg<u32, _MATCH1>>`[src]

`pub fn matchn_l(&mut self) -> MATCHN_L_W<'_>`[src]

Bits 0:15 - When UNIFY = 0, read or write the 16-bit value to be compared to the L counter. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be compared to the unified counter.

`pub fn matchn_h(&mut self) -> MATCHN_H_W<'_>`[src]

Bits 16:31 - When UNIFY = 0, read or write the 16-bit value to be compared to the H counter. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be compared to the unified counter.

`impl W<u32, Reg<u32, _CAP2>>`[src]

`pub fn capn_l(&mut self) -> CAPN_L_W<'_>`[src]

Bits 0:15 - When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the lower 16 bits of the 32-bit value at which this register was last captured.

`pub fn capn_h(&mut self) -> CAPN_H_W<'_>`[src]

Bits 16:31 - When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the upper 16 bits of the 32-bit value at which this register was last captured.

`impl W<u32, Reg<u32, _MATCH2>>`[src]

`pub fn matchn_l(&mut self) -> MATCHN_L_W<'_>`[src]

Bits 0:15 - When UNIFY = 0, read or write the 16-bit value to be compared to the L counter. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be compared to the unified counter.

`pub fn matchn_h(&mut self) -> MATCHN_H_W<'_>`[src]

Bits 16:31 - When UNIFY = 0, read or write the 16-bit value to be compared to the H counter. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be compared to the unified counter.

`impl W<u32, Reg<u32, _CAP3>>`[src]

`pub fn capn_l(&mut self) -> CAPN_L_W<'_>`[src]

Bits 0:15 - When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the lower 16 bits of the 32-bit value at which this register was last captured.

`pub fn capn_h(&mut self) -> CAPN_H_W<'_>`[src]

Bits 16:31 - When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the upper 16 bits of the 32-bit value at which this register was last captured.

`impl W<u32, Reg<u32, _MATCH3>>`[src]

`pub fn matchn_l(&mut self) -> MATCHN_L_W<'_>`[src]

Bits 0:15 - When UNIFY = 0, read or write the 16-bit value to be compared to the L counter. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be compared to the unified counter.

`pub fn matchn_h(&mut self) -> MATCHN_H_W<'_>`[src]

Bits 16:31 - When UNIFY = 0, read or write the 16-bit value to be compared to the H counter. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be compared to the unified counter.

`impl W<u32, Reg<u32, _CAP4>>`[src]

`pub fn capn_l(&mut self) -> CAPN_L_W<'_>`[src]

Bits 0:15 - When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the lower 16 bits of the 32-bit value at which this register was last captured.

`pub fn capn_h(&mut self) -> CAPN_H_W<'_>`[src]

Bits 16:31 - When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the upper 16 bits of the 32-bit value at which this register was last captured.

`impl W<u32, Reg<u32, _MATCH4>>`[src]

`pub fn matchn_l(&mut self) -> MATCHN_L_W<'_>`[src]

Bits 0:15 - When UNIFY = 0, read or write the 16-bit value to be compared to the L counter. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be compared to the unified counter.

`pub fn matchn_h(&mut self) -> MATCHN_H_W<'_>`[src]

Bits 16:31 - When UNIFY = 0, read or write the 16-bit value to be compared to the H counter. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be compared to the unified counter.

`impl W<u32, Reg<u32, _CAP5>>`[src]

`pub fn capn_l(&mut self) -> CAPN_L_W<'_>`[src]

Bits 0:15 - When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the lower 16 bits of the 32-bit value at which this register was last captured.

`pub fn capn_h(&mut self) -> CAPN_H_W<'_>`[src]

Bits 16:31 - When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the upper 16 bits of the 32-bit value at which this register was last captured.

`impl W<u32, Reg<u32, _MATCH5>>`[src]

`pub fn matchn_l(&mut self) -> MATCHN_L_W<'_>`[src]

Bits 0:15 - When UNIFY = 0, read or write the 16-bit value to be compared to the L counter. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be compared to the unified counter.

`pub fn matchn_h(&mut self) -> MATCHN_H_W<'_>`[src]

Bits 16:31 - When UNIFY = 0, read or write the 16-bit value to be compared to the H counter. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be compared to the unified counter.

`impl W<u32, Reg<u32, _CAP6>>`[src]

`pub fn capn_l(&mut self) -> CAPN_L_W<'_>`[src]

Bits 0:15 - When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the lower 16 bits of the 32-bit value at which this register was last captured.

`pub fn capn_h(&mut self) -> CAPN_H_W<'_>`[src]

Bits 16:31 - When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the upper 16 bits of the 32-bit value at which this register was last captured.

`impl W<u32, Reg<u32, _MATCH6>>`[src]

`pub fn matchn_l(&mut self) -> MATCHN_L_W<'_>`[src]

Bits 0:15 - When UNIFY = 0, read or write the 16-bit value to be compared to the L counter. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be compared to the unified counter.

`pub fn matchn_h(&mut self) -> MATCHN_H_W<'_>`[src]

Bits 16:31 - When UNIFY = 0, read or write the 16-bit value to be compared to the H counter. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be compared to the unified counter.

`impl W<u32, Reg<u32, _CAP7>>`[src]

`pub fn capn_l(&mut self) -> CAPN_L_W<'_>`[src]

Bits 0:15 - When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the lower 16 bits of the 32-bit value at which this register was last captured.

`pub fn capn_h(&mut self) -> CAPN_H_W<'_>`[src]

Bits 16:31 - When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the upper 16 bits of the 32-bit value at which this register was last captured.

`impl W<u32, Reg<u32, _MATCH7>>`[src]

`pub fn matchn_l(&mut self) -> MATCHN_L_W<'_>`[src]

Bits 0:15 - When UNIFY = 0, read or write the 16-bit value to be compared to the L counter. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be compared to the unified counter.

`pub fn matchn_h(&mut self) -> MATCHN_H_W<'_>`[src]

Bits 16:31 - When UNIFY = 0, read or write the 16-bit value to be compared to the H counter. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be compared to the unified counter.

`impl W<u32, Reg<u32, _CAP8>>`[src]

`pub fn capn_l(&mut self) -> CAPN_L_W<'_>`[src]

Bits 0:15 - When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the lower 16 bits of the 32-bit value at which this register was last captured.

`pub fn capn_h(&mut self) -> CAPN_H_W<'_>`[src]

Bits 16:31 - When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the upper 16 bits of the 32-bit value at which this register was last captured.

`impl W<u32, Reg<u32, _MATCH8>>`[src]

`pub fn matchn_l(&mut self) -> MATCHN_L_W<'_>`[src]

Bits 0:15 - When UNIFY = 0, read or write the 16-bit value to be compared to the L counter. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be compared to the unified counter.

`pub fn matchn_h(&mut self) -> MATCHN_H_W<'_>`[src]

Bits 16:31 - When UNIFY = 0, read or write the 16-bit value to be compared to the H counter. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be compared to the unified counter.

`impl W<u32, Reg<u32, _CAP9>>`[src]

`pub fn capn_l(&mut self) -> CAPN_L_W<'_>`[src]

Bits 0:15 - When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the lower 16 bits of the 32-bit value at which this register was last captured.

`pub fn capn_h(&mut self) -> CAPN_H_W<'_>`[src]

Bits 16:31 - When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the upper 16 bits of the 32-bit value at which this register was last captured.

`impl W<u32, Reg<u32, _MATCH9>>`[src]

`pub fn matchn_l(&mut self) -> MATCHN_L_W<'_>`[src]

Bits 0:15 - When UNIFY = 0, read or write the 16-bit value to be compared to the L counter. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be compared to the unified counter.

`pub fn matchn_h(&mut self) -> MATCHN_H_W<'_>`[src]

Bits 16:31 - When UNIFY = 0, read or write the 16-bit value to be compared to the H counter. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be compared to the unified counter.

`impl W<u32, Reg<u32, _CAP10>>`[src]

`pub fn capn_l(&mut self) -> CAPN_L_W<'_>`[src]

Bits 0:15 - When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the lower 16 bits of the 32-bit value at which this register was last captured.

`pub fn capn_h(&mut self) -> CAPN_H_W<'_>`[src]

Bits 16:31 - When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the upper 16 bits of the 32-bit value at which this register was last captured.

`impl W<u32, Reg<u32, _MATCH10>>`[src]

`pub fn matchn_l(&mut self) -> MATCHN_L_W<'_>`[src]

Bits 0:15 - When UNIFY = 0, read or write the 16-bit value to be compared to the L counter. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be compared to the unified counter.

`pub fn matchn_h(&mut self) -> MATCHN_H_W<'_>`[src]

Bits 16:31 - When UNIFY = 0, read or write the 16-bit value to be compared to the H counter. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be compared to the unified counter.

`impl W<u32, Reg<u32, _CAP11>>`[src]

`pub fn capn_l(&mut self) -> CAPN_L_W<'_>`[src]

Bits 0:15 - When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the lower 16 bits of the 32-bit value at which this register was last captured.

`pub fn capn_h(&mut self) -> CAPN_H_W<'_>`[src]

Bits 16:31 - When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the upper 16 bits of the 32-bit value at which this register was last captured.

`impl W<u32, Reg<u32, _MATCH11>>`[src]

`pub fn matchn_l(&mut self) -> MATCHN_L_W<'_>`[src]

Bits 0:15 - When UNIFY = 0, read or write the 16-bit value to be compared to the L counter. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be compared to the unified counter.

`pub fn matchn_h(&mut self) -> MATCHN_H_W<'_>`[src]

Bits 16:31 - When UNIFY = 0, read or write the 16-bit value to be compared to the H counter. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be compared to the unified counter.

`impl W<u32, Reg<u32, _CAP12>>`[src]

`pub fn capn_l(&mut self) -> CAPN_L_W<'_>`[src]

Bits 0:15 - When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the lower 16 bits of the 32-bit value at which this register was last captured.

`pub fn capn_h(&mut self) -> CAPN_H_W<'_>`[src]

Bits 16:31 - When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the upper 16 bits of the 32-bit value at which this register was last captured.

`impl W<u32, Reg<u32, _MATCH12>>`[src]

`pub fn matchn_l(&mut self) -> MATCHN_L_W<'_>`[src]

Bits 0:15 - When UNIFY = 0, read or write the 16-bit value to be compared to the L counter. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be compared to the unified counter.

`pub fn matchn_h(&mut self) -> MATCHN_H_W<'_>`[src]

Bits 16:31 - When UNIFY = 0, read or write the 16-bit value to be compared to the H counter. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be compared to the unified counter.

`impl W<u32, Reg<u32, _CAP13>>`[src]

`pub fn capn_l(&mut self) -> CAPN_L_W<'_>`[src]

Bits 0:15 - When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the lower 16 bits of the 32-bit value at which this register was last captured.

`pub fn capn_h(&mut self) -> CAPN_H_W<'_>`[src]

Bits 16:31 - When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the upper 16 bits of the 32-bit value at which this register was last captured.

`impl W<u32, Reg<u32, _MATCH13>>`[src]

`pub fn matchn_l(&mut self) -> MATCHN_L_W<'_>`[src]

Bits 0:15 - When UNIFY = 0, read or write the 16-bit value to be compared to the L counter. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be compared to the unified counter.

`pub fn matchn_h(&mut self) -> MATCHN_H_W<'_>`[src]

Bits 16:31 - When UNIFY = 0, read or write the 16-bit value to be compared to the H counter. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be compared to the unified counter.

`impl W<u32, Reg<u32, _CAP14>>`[src]

`pub fn capn_l(&mut self) -> CAPN_L_W<'_>`[src]

Bits 0:15 - When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the lower 16 bits of the 32-bit value at which this register was last captured.

`pub fn capn_h(&mut self) -> CAPN_H_W<'_>`[src]

Bits 16:31 - When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the upper 16 bits of the 32-bit value at which this register was last captured.

`impl W<u32, Reg<u32, _MATCH14>>`[src]

`pub fn matchn_l(&mut self) -> MATCHN_L_W<'_>`[src]

Bits 0:15 - When UNIFY = 0, read or write the 16-bit value to be compared to the L counter. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be compared to the unified counter.

`pub fn matchn_h(&mut self) -> MATCHN_H_W<'_>`[src]

Bits 16:31 - When UNIFY = 0, read or write the 16-bit value to be compared to the H counter. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be compared to the unified counter.

`impl W<u32, Reg<u32, _CAP15>>`[src]

`pub fn capn_l(&mut self) -> CAPN_L_W<'_>`[src]

Bits 0:15 - When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the lower 16 bits of the 32-bit value at which this register was last captured.

`pub fn capn_h(&mut self) -> CAPN_H_W<'_>`[src]

Bits 16:31 - When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the upper 16 bits of the 32-bit value at which this register was last captured.

`impl W<u32, Reg<u32, _MATCH15>>`[src]

`pub fn matchn_l(&mut self) -> MATCHN_L_W<'_>`[src]

Bits 0:15 - When UNIFY = 0, read or write the 16-bit value to be compared to the L counter. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be compared to the unified counter.

`pub fn matchn_h(&mut self) -> MATCHN_H_W<'_>`[src]

Bits 16:31 - When UNIFY = 0, read or write the 16-bit value to be compared to the H counter. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be compared to the unified counter.

`impl W<u32, Reg<u32, _CAPCTRL0>>`[src]

`pub fn capconn_l(&mut self) -> CAPCONN_L_W<'_>`[src]

Bits 0:15 - If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of match/captures in this SCT.

`pub fn capconn_h(&mut self) -> CAPCONN_H_W<'_>`[src]

Bits 16:31 - If bit m is one, event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16, event 1 = bit 17, etc.). The number of bits = number of match/captures in this SCT.

`impl W<u32, Reg<u32, _MATCHREL0>>`[src]

`pub fn reloadn_l(&mut self) -> RELOADN_L_W<'_>`[src]

Bits 0:15 - When UNIFY = 0, specifies the 16-bit value to be loaded into the MATCHn_L register. When UNIFY = 1, specifies the lower 16 bits of the 32-bit value to be loaded into the MATCHn register.

`pub fn reloadn_h(&mut self) -> RELOADN_H_W<'_>`[src]

Bits 16:31 - When UNIFY = 0, specifies the 16-bit to be loaded into the MATCHn_H register. When UNIFY = 1, specifies the upper 16 bits of the 32-bit value to be loaded into the MATCHn register.

`impl W<u32, Reg<u32, _CAPCTRL1>>`[src]

`pub fn capconn_l(&mut self) -> CAPCONN_L_W<'_>`[src]

Bits 0:15 - If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of match/captures in this SCT.

`pub fn capconn_h(&mut self) -> CAPCONN_H_W<'_>`[src]

Bits 16:31 - If bit m is one, event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16, event 1 = bit 17, etc.). The number of bits = number of match/captures in this SCT.

`impl W<u32, Reg<u32, _MATCHREL1>>`[src]

`pub fn reloadn_l(&mut self) -> RELOADN_L_W<'_>`[src]

Bits 0:15 - When UNIFY = 0, specifies the 16-bit value to be loaded into the MATCHn_L register. When UNIFY = 1, specifies the lower 16 bits of the 32-bit value to be loaded into the MATCHn register.

`pub fn reloadn_h(&mut self) -> RELOADN_H_W<'_>`[src]

Bits 16:31 - When UNIFY = 0, specifies the 16-bit to be loaded into the MATCHn_H register. When UNIFY = 1, specifies the upper 16 bits of the 32-bit value to be loaded into the MATCHn register.

`impl W<u32, Reg<u32, _CAPCTRL2>>`[src]

`pub fn capconn_l(&mut self) -> CAPCONN_L_W<'_>`[src]

Bits 0:15 - If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of match/captures in this SCT.

`pub fn capconn_h(&mut self) -> CAPCONN_H_W<'_>`[src]

Bits 16:31 - If bit m is one, event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16, event 1 = bit 17, etc.). The number of bits = number of match/captures in this SCT.

`impl W<u32, Reg<u32, _MATCHREL2>>`[src]

`pub fn reloadn_l(&mut self) -> RELOADN_L_W<'_>`[src]

Bits 0:15 - When UNIFY = 0, specifies the 16-bit value to be loaded into the MATCHn_L register. When UNIFY = 1, specifies the lower 16 bits of the 32-bit value to be loaded into the MATCHn register.

`pub fn reloadn_h(&mut self) -> RELOADN_H_W<'_>`[src]

Bits 16:31 - When UNIFY = 0, specifies the 16-bit to be loaded into the MATCHn_H register. When UNIFY = 1, specifies the upper 16 bits of the 32-bit value to be loaded into the MATCHn register.

`impl W<u32, Reg<u32, _CAPCTRL3>>`[src]

`pub fn capconn_l(&mut self) -> CAPCONN_L_W<'_>`[src]

Bits 0:15 - If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of match/captures in this SCT.

`pub fn capconn_h(&mut self) -> CAPCONN_H_W<'_>`[src]

Bits 16:31 - If bit m is one, event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16, event 1 = bit 17, etc.). The number of bits = number of match/captures in this SCT.

`impl W<u32, Reg<u32, _MATCHREL3>>`[src]

`pub fn reloadn_l(&mut self) -> RELOADN_L_W<'_>`[src]

Bits 0:15 - When UNIFY = 0, specifies the 16-bit value to be loaded into the MATCHn_L register. When UNIFY = 1, specifies the lower 16 bits of the 32-bit value to be loaded into the MATCHn register.

`pub fn reloadn_h(&mut self) -> RELOADN_H_W<'_>`[src]

Bits 16:31 - When UNIFY = 0, specifies the 16-bit to be loaded into the MATCHn_H register. When UNIFY = 1, specifies the upper 16 bits of the 32-bit value to be loaded into the MATCHn register.

`impl W<u32, Reg<u32, _CAPCTRL4>>`[src]

`pub fn capconn_l(&mut self) -> CAPCONN_L_W<'_>`[src]

Bits 0:15 - If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of match/captures in this SCT.

`pub fn capconn_h(&mut self) -> CAPCONN_H_W<'_>`[src]

Bits 16:31 - If bit m is one, event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16, event 1 = bit 17, etc.). The number of bits = number of match/captures in this SCT.

`impl W<u32, Reg<u32, _MATCHREL4>>`[src]

`pub fn reloadn_l(&mut self) -> RELOADN_L_W<'_>`[src]

Bits 0:15 - When UNIFY = 0, specifies the 16-bit value to be loaded into the MATCHn_L register. When UNIFY = 1, specifies the lower 16 bits of the 32-bit value to be loaded into the MATCHn register.

`pub fn reloadn_h(&mut self) -> RELOADN_H_W<'_>`[src]

Bits 16:31 - When UNIFY = 0, specifies the 16-bit to be loaded into the MATCHn_H register. When UNIFY = 1, specifies the upper 16 bits of the 32-bit value to be loaded into the MATCHn register.

`impl W<u32, Reg<u32, _CAPCTRL5>>`[src]

`pub fn capconn_l(&mut self) -> CAPCONN_L_W<'_>`[src]

Bits 0:15 - If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of match/captures in this SCT.

`pub fn capconn_h(&mut self) -> CAPCONN_H_W<'_>`[src]

Bits 16:31 - If bit m is one, event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16, event 1 = bit 17, etc.). The number of bits = number of match/captures in this SCT.

`impl W<u32, Reg<u32, _MATCHREL5>>`[src]

`pub fn reloadn_l(&mut self) -> RELOADN_L_W<'_>`[src]

Bits 0:15 - When UNIFY = 0, specifies the 16-bit value to be loaded into the MATCHn_L register. When UNIFY = 1, specifies the lower 16 bits of the 32-bit value to be loaded into the MATCHn register.

`pub fn reloadn_h(&mut self) -> RELOADN_H_W<'_>`[src]

Bits 16:31 - When UNIFY = 0, specifies the 16-bit to be loaded into the MATCHn_H register. When UNIFY = 1, specifies the upper 16 bits of the 32-bit value to be loaded into the MATCHn register.

`impl W<u32, Reg<u32, _CAPCTRL6>>`[src]

`pub fn capconn_l(&mut self) -> CAPCONN_L_W<'_>`[src]

Bits 0:15 - If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of match/captures in this SCT.

`pub fn capconn_h(&mut self) -> CAPCONN_H_W<'_>`[src]

Bits 16:31 - If bit m is one, event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16, event 1 = bit 17, etc.). The number of bits = number of match/captures in this SCT.

`impl W<u32, Reg<u32, _MATCHREL6>>`[src]

`pub fn reloadn_l(&mut self) -> RELOADN_L_W<'_>`[src]

Bits 0:15 - When UNIFY = 0, specifies the 16-bit value to be loaded into the MATCHn_L register. When UNIFY = 1, specifies the lower 16 bits of the 32-bit value to be loaded into the MATCHn register.

`pub fn reloadn_h(&mut self) -> RELOADN_H_W<'_>`[src]

Bits 16:31 - When UNIFY = 0, specifies the 16-bit to be loaded into the MATCHn_H register. When UNIFY = 1, specifies the upper 16 bits of the 32-bit value to be loaded into the MATCHn register.

`impl W<u32, Reg<u32, _CAPCTRL7>>`[src]

`pub fn capconn_l(&mut self) -> CAPCONN_L_W<'_>`[src]

Bits 0:15 - If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of match/captures in this SCT.

`pub fn capconn_h(&mut self) -> CAPCONN_H_W<'_>`[src]

Bits 16:31 - If bit m is one, event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16, event 1 = bit 17, etc.). The number of bits = number of match/captures in this SCT.

`impl W<u32, Reg<u32, _MATCHREL7>>`[src]

`pub fn reloadn_l(&mut self) -> RELOADN_L_W<'_>`[src]

Bits 0:15 - When UNIFY = 0, specifies the 16-bit value to be loaded into the MATCHn_L register. When UNIFY = 1, specifies the lower 16 bits of the 32-bit value to be loaded into the MATCHn register.

`pub fn reloadn_h(&mut self) -> RELOADN_H_W<'_>`[src]

Bits 16:31 - When UNIFY = 0, specifies the 16-bit to be loaded into the MATCHn_H register. When UNIFY = 1, specifies the upper 16 bits of the 32-bit value to be loaded into the MATCHn register.

`impl W<u32, Reg<u32, _CAPCTRL8>>`[src]

`pub fn capconn_l(&mut self) -> CAPCONN_L_W<'_>`[src]

Bits 0:15 - If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of match/captures in this SCT.

`pub fn capconn_h(&mut self) -> CAPCONN_H_W<'_>`[src]

Bits 16:31 - If bit m is one, event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16, event 1 = bit 17, etc.). The number of bits = number of match/captures in this SCT.

`impl W<u32, Reg<u32, _MATCHREL8>>`[src]

`pub fn reloadn_l(&mut self) -> RELOADN_L_W<'_>`[src]

Bits 0:15 - When UNIFY = 0, specifies the 16-bit value to be loaded into the MATCHn_L register. When UNIFY = 1, specifies the lower 16 bits of the 32-bit value to be loaded into the MATCHn register.

`pub fn reloadn_h(&mut self) -> RELOADN_H_W<'_>`[src]

Bits 16:31 - When UNIFY = 0, specifies the 16-bit to be loaded into the MATCHn_H register. When UNIFY = 1, specifies the upper 16 bits of the 32-bit value to be loaded into the MATCHn register.

`impl W<u32, Reg<u32, _CAPCTRL9>>`[src]

`pub fn capconn_l(&mut self) -> CAPCONN_L_W<'_>`[src]

Bits 0:15 - If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of match/captures in this SCT.

`pub fn capconn_h(&mut self) -> CAPCONN_H_W<'_>`[src]

Bits 16:31 - If bit m is one, event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16, event 1 = bit 17, etc.). The number of bits = number of match/captures in this SCT.

`impl W<u32, Reg<u32, _MATCHREL9>>`[src]

`pub fn reloadn_l(&mut self) -> RELOADN_L_W<'_>`[src]

Bits 0:15 - When UNIFY = 0, specifies the 16-bit value to be loaded into the MATCHn_L register. When UNIFY = 1, specifies the lower 16 bits of the 32-bit value to be loaded into the MATCHn register.

`pub fn reloadn_h(&mut self) -> RELOADN_H_W<'_>`[src]

Bits 16:31 - When UNIFY = 0, specifies the 16-bit to be loaded into the MATCHn_H register. When UNIFY = 1, specifies the upper 16 bits of the 32-bit value to be loaded into the MATCHn register.

`impl W<u32, Reg<u32, _CAPCTRL10>>`[src]

`pub fn capconn_l(&mut self) -> CAPCONN_L_W<'_>`[src]

Bits 0:15 - If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of match/captures in this SCT.

`pub fn capconn_h(&mut self) -> CAPCONN_H_W<'_>`[src]

Bits 16:31 - If bit m is one, event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16, event 1 = bit 17, etc.). The number of bits = number of match/captures in this SCT.

`impl W<u32, Reg<u32, _MATCHREL10>>`[src]

`pub fn reloadn_l(&mut self) -> RELOADN_L_W<'_>`[src]

Bits 0:15 - When UNIFY = 0, specifies the 16-bit value to be loaded into the MATCHn_L register. When UNIFY = 1, specifies the lower 16 bits of the 32-bit value to be loaded into the MATCHn register.

`pub fn reloadn_h(&mut self) -> RELOADN_H_W<'_>`[src]

Bits 16:31 - When UNIFY = 0, specifies the 16-bit to be loaded into the MATCHn_H register. When UNIFY = 1, specifies the upper 16 bits of the 32-bit value to be loaded into the MATCHn register.

`impl W<u32, Reg<u32, _CAPCTRL11>>`[src]

`pub fn capconn_l(&mut self) -> CAPCONN_L_W<'_>`[src]

Bits 0:15 - If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of match/captures in this SCT.

`pub fn capconn_h(&mut self) -> CAPCONN_H_W<'_>`[src]

Bits 16:31 - If bit m is one, event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16, event 1 = bit 17, etc.). The number of bits = number of match/captures in this SCT.

`impl W<u32, Reg<u32, _MATCHREL11>>`[src]

`pub fn reloadn_l(&mut self) -> RELOADN_L_W<'_>`[src]

Bits 0:15 - When UNIFY = 0, specifies the 16-bit value to be loaded into the MATCHn_L register. When UNIFY = 1, specifies the lower 16 bits of the 32-bit value to be loaded into the MATCHn register.

`pub fn reloadn_h(&mut self) -> RELOADN_H_W<'_>`[src]

Bits 16:31 - When UNIFY = 0, specifies the 16-bit to be loaded into the MATCHn_H register. When UNIFY = 1, specifies the upper 16 bits of the 32-bit value to be loaded into the MATCHn register.

`impl W<u32, Reg<u32, _CAPCTRL12>>`[src]

`pub fn capconn_l(&mut self) -> CAPCONN_L_W<'_>`[src]

Bits 0:15 - If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of match/captures in this SCT.

`pub fn capconn_h(&mut self) -> CAPCONN_H_W<'_>`[src]

Bits 16:31 - If bit m is one, event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16, event 1 = bit 17, etc.). The number of bits = number of match/captures in this SCT.

`impl W<u32, Reg<u32, _MATCHREL12>>`[src]

`pub fn reloadn_l(&mut self) -> RELOADN_L_W<'_>`[src]

Bits 0:15 - When UNIFY = 0, specifies the 16-bit value to be loaded into the MATCHn_L register. When UNIFY = 1, specifies the lower 16 bits of the 32-bit value to be loaded into the MATCHn register.

`pub fn reloadn_h(&mut self) -> RELOADN_H_W<'_>`[src]

Bits 16:31 - When UNIFY = 0, specifies the 16-bit to be loaded into the MATCHn_H register. When UNIFY = 1, specifies the upper 16 bits of the 32-bit value to be loaded into the MATCHn register.

`impl W<u32, Reg<u32, _CAPCTRL13>>`[src]

`pub fn capconn_l(&mut self) -> CAPCONN_L_W<'_>`[src]

Bits 0:15 - If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of match/captures in this SCT.

`pub fn capconn_h(&mut self) -> CAPCONN_H_W<'_>`[src]

Bits 16:31 - If bit m is one, event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16, event 1 = bit 17, etc.). The number of bits = number of match/captures in this SCT.

`impl W<u32, Reg<u32, _MATCHREL13>>`[src]

`pub fn reloadn_l(&mut self) -> RELOADN_L_W<'_>`[src]

Bits 0:15 - When UNIFY = 0, specifies the 16-bit value to be loaded into the MATCHn_L register. When UNIFY = 1, specifies the lower 16 bits of the 32-bit value to be loaded into the MATCHn register.

`pub fn reloadn_h(&mut self) -> RELOADN_H_W<'_>`[src]

Bits 16:31 - When UNIFY = 0, specifies the 16-bit to be loaded into the MATCHn_H register. When UNIFY = 1, specifies the upper 16 bits of the 32-bit value to be loaded into the MATCHn register.

`impl W<u32, Reg<u32, _CAPCTRL14>>`[src]

`pub fn capconn_l(&mut self) -> CAPCONN_L_W<'_>`[src]

Bits 0:15 - If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of match/captures in this SCT.

`pub fn capconn_h(&mut self) -> CAPCONN_H_W<'_>`[src]

Bits 16:31 - If bit m is one, event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16, event 1 = bit 17, etc.). The number of bits = number of match/captures in this SCT.

`impl W<u32, Reg<u32, _MATCHREL14>>`[src]

`pub fn reloadn_l(&mut self) -> RELOADN_L_W<'_>`[src]

Bits 0:15 - When UNIFY = 0, specifies the 16-bit value to be loaded into the MATCHn_L register. When UNIFY = 1, specifies the lower 16 bits of the 32-bit value to be loaded into the MATCHn register.

`pub fn reloadn_h(&mut self) -> RELOADN_H_W<'_>`[src]

Bits 16:31 - When UNIFY = 0, specifies the 16-bit to be loaded into the MATCHn_H register. When UNIFY = 1, specifies the upper 16 bits of the 32-bit value to be loaded into the MATCHn register.

`impl W<u32, Reg<u32, _CAPCTRL15>>`[src]

`pub fn capconn_l(&mut self) -> CAPCONN_L_W<'_>`[src]

Bits 0:15 - If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of match/captures in this SCT.

`pub fn capconn_h(&mut self) -> CAPCONN_H_W<'_>`[src]

Bits 16:31 - If bit m is one, event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16, event 1 = bit 17, etc.). The number of bits = number of match/captures in this SCT.

`impl W<u32, Reg<u32, _MATCHREL15>>`[src]

`pub fn reloadn_l(&mut self) -> RELOADN_L_W<'_>`[src]

Bits 0:15 - When UNIFY = 0, specifies the 16-bit value to be loaded into the MATCHn_L register. When UNIFY = 1, specifies the lower 16 bits of the 32-bit value to be loaded into the MATCHn register.

`pub fn reloadn_h(&mut self) -> RELOADN_H_W<'_>`[src]

Bits 16:31 - When UNIFY = 0, specifies the 16-bit to be loaded into the MATCHn_H register. When UNIFY = 1, specifies the upper 16 bits of the 32-bit value to be loaded into the MATCHn register.

`impl W<u32, Reg<u32, _PSELID>>`[src]

`pub fn persel(&mut self) -> PERSEL_W<'_>`[src]

Bits 0:2 - Peripheral Select. This field is writable by software.

`pub fn lock(&mut self) -> LOCK_W<'_>`[src]

Bit 3 - Lock the peripheral select. This field is writable by software.

`impl W<u32, Reg<u32, _CFG>>`[src]

`pub fn msten(&mut self) -> MSTEN_W<'_>`[src]

Bit 0 - Master Enable. When disabled, configurations settings for the Master function are not changed, but the Master function is internally reset.

`pub fn slven(&mut self) -> SLVEN_W<'_>`[src]

Bit 1 - Slave Enable. When disabled, configurations settings for the Slave function are not changed, but the Slave function is internally reset.

`pub fn monen(&mut self) -> MONEN_W<'_>`[src]

Bit 2 - Monitor Enable. When disabled, configurations settings for the Monitor function are not changed, but the Monitor function is internally reset.

`pub fn timeouten(&mut self) -> TIMEOUTEN_W<'_>`[src]

Bit 3 - I2C bus Time-out Enable. When disabled, the time-out function is internally reset.

`pub fn monclkstr(&mut self) -> MONCLKSTR_W<'_>`[src]

Bit 4 - Monitor function Clock Stretching.

`pub fn hscapable(&mut self) -> HSCAPABLE_W<'_>`[src]

Bit 5 - High-speed mode Capable enable. Since High Speed mode alters the way I2C pins drive and filter, as well as the timing for certain I2C signalling, enabling High-speed mode applies to all functions: Master, Slave, and Monitor.

`impl W<u32, Reg<u32, _STAT>>`[src]

`pub fn mstarbloss(&mut self) -> MSTARBLOSS_W<'_>`[src]

Bit 4 - Master Arbitration Loss flag. This flag can be cleared by software writing a 1 to this bit. It is also cleared automatically a 1 is written to MSTCONTINUE.

`pub fn mstststperr(&mut self) -> MSTSTSTPERR_W<'_>`[src]

Bit 6 - Master Start/Stop Error flag. This flag can be cleared by software writing a 1 to this bit. It is also cleared automatically a 1 is written to MSTCONTINUE.

`pub fn slvdesel(&mut self) -> SLVDESEL_W<'_>`[src]

Bit 15 - Slave Deselected flag. This flag will cause an interrupt when set if enabled via INTENSET. This flag can be cleared by writing a 1 to this bit.

`pub fn monov(&mut self) -> MONOV_W<'_>`[src]

Bit 17 - Monitor Overflow flag.

`pub fn monidle(&mut self) -> MONIDLE_W<'_>`[src]

Bit 19 - Monitor Idle flag. This flag is set when the Monitor function sees the I2C bus change from active to inactive. This can be used by software to decide when to process data accumulated by the Monitor function. This flag will cause an interrupt when set if enabled via the INTENSET register. The flag can be cleared by writing a 1 to this bit.

`pub fn eventtimeout(&mut self) -> EVENTTIMEOUT_W<'_>`[src]

Bit 24 - Event Time-out Interrupt flag. Indicates when the time between events has been longer than the time specified by the TIMEOUT register. Events include Start, Stop, and clock edges. The flag is cleared by writing a 1 to this bit. No time-out is created when the I2C-bus is idle.

`pub fn scltimeout(&mut self) -> SCLTIMEOUT_W<'_>`[src]

Bit 25 - SCL Time-out Interrupt flag. Indicates when SCL has remained low longer than the time specific by the TIMEOUT register. The flag is cleared by writing a 1 to this bit.

`impl W<u32, Reg<u32, _INTENSET>>`[src]

`pub fn mstpendingen(&mut self) -> MSTPENDINGEN_W<'_>`[src]

Bit 0 - Master Pending interrupt Enable.

`pub fn mstarblossen(&mut self) -> MSTARBLOSSEN_W<'_>`[src]

Bit 4 - Master Arbitration Loss interrupt Enable.

`pub fn mstststperren(&mut self) -> MSTSTSTPERREN_W<'_>`[src]

Bit 6 - Master Start/Stop Error interrupt Enable.

`pub fn slvpendingen(&mut self) -> SLVPENDINGEN_W<'_>`[src]

Bit 8 - Slave Pending interrupt Enable.

`pub fn slvnotstren(&mut self) -> SLVNOTSTREN_W<'_>`[src]

Bit 11 - Slave Not Stretching interrupt Enable.

`pub fn slvdeselen(&mut self) -> SLVDESELEN_W<'_>`[src]

Bit 15 - Slave Deselect interrupt Enable.

`pub fn monrdyen(&mut self) -> MONRDYEN_W<'_>`[src]

Bit 16 - Monitor data Ready interrupt Enable.

`pub fn monoven(&mut self) -> MONOVEN_W<'_>`[src]

Bit 17 - Monitor Overrun interrupt Enable.

`pub fn monidleen(&mut self) -> MONIDLEEN_W<'_>`[src]

Bit 19 - Monitor Idle interrupt Enable.

`pub fn eventtimeouten(&mut self) -> EVENTTIMEOUTEN_W<'_>`[src]

Bit 24 - Event time-out interrupt Enable.

`pub fn scltimeouten(&mut self) -> SCLTIMEOUTEN_W<'_>`[src]

Bit 25 - SCL time-out interrupt Enable.

`impl W<u32, Reg<u32, _INTENCLR>>`[src]

`pub fn mstpendingclr(&mut self) -> MSTPENDINGCLR_W<'_>`[src]

Bit 0 - Master Pending interrupt clear. Writing 1 to this bit clears the corresponding bit in the INTENSET register if implemented.

`pub fn mstarblossclr(&mut self) -> MSTARBLOSSCLR_W<'_>`[src]

Bit 4 - Master Arbitration Loss interrupt clear.

`pub fn mstststperrclr(&mut self) -> MSTSTSTPERRCLR_W<'_>`[src]

Bit 6 - Master Start/Stop Error interrupt clear.

`pub fn slvpendingclr(&mut self) -> SLVPENDINGCLR_W<'_>`[src]

Bit 8 - Slave Pending interrupt clear.

`pub fn slvnotstrclr(&mut self) -> SLVNOTSTRCLR_W<'_>`[src]

Bit 11 - Slave Not Stretching interrupt clear.

`pub fn slvdeselclr(&mut self) -> SLVDESELCLR_W<'_>`[src]

Bit 15 - Slave Deselect interrupt clear.

`pub fn monrdyclr(&mut self) -> MONRDYCLR_W<'_>`[src]

Bit 16 - Monitor data Ready interrupt clear.

`pub fn monovclr(&mut self) -> MONOVCLR_W<'_>`[src]

Bit 17 - Monitor Overrun interrupt clear.

`pub fn monidleclr(&mut self) -> MONIDLECLR_W<'_>`[src]

Bit 19 - Monitor Idle interrupt clear.

`pub fn eventtimeoutclr(&mut self) -> EVENTTIMEOUTCLR_W<'_>`[src]

Bit 24 - Event time-out interrupt clear.

`pub fn scltimeoutclr(&mut self) -> SCLTIMEOUTCLR_W<'_>`[src]

Bit 25 - SCL time-out interrupt clear.

`impl W<u32, Reg<u32, _TIMEOUT>>`[src]

`pub fn tomin(&mut self) -> TOMIN_W<'_>`[src]

Bits 0:3 - Time-out time value, bottom four bits. These are hard-wired to 0xF. This gives a minimum time-out of 16 I2C function clocks and also a time-out resolution of 16 I2C function clocks.

`pub fn to(&mut self) -> TO_W<'_>`[src]

Bits 4:15 - Time-out time value. Specifies the time-out interval value in increments of 16 I 2C function clocks, as defined by the CLKDIV register. To change this value while I2C is in operation, disable all time-outs, write a new value to TIMEOUT, then re-enable time-outs. 0x000 = A time-out will occur after 16 counts of the I2C function clock. 0x001 = A time-out will occur after 32 counts of the I2C function clock. 0xFFF = A time-out will occur after 65,536 counts of the I2C function clock.

`impl W<u32, Reg<u32, _CLKDIV>>`[src]

`pub fn divval(&mut self) -> DIVVAL_W<'_>`[src]

Bits 0:15 - This field controls how the Flexcomm clock (FCLK) is used by the I2C functions that need an internal clock in order to operate. 0x0000 = FCLK is used directly by the I2C. 0x0001 = FCLK is divided by 2 before use. 0x0002 = FCLK is divided by 3 before use. 0xFFFF = FCLK is divided by 65,536 before use.

`impl W<u32, Reg<u32, _MSTCTL>>`[src]

`pub fn mstcontinue(&mut self) -> MSTCONTINUE_W<'_>`[src]

Bit 0 - Master Continue. This bit is write-only.

`pub fn mststart(&mut self) -> MSTSTART_W<'_>`[src]

Bit 1 - Master Start control. This bit is write-only.

`pub fn mststop(&mut self) -> MSTSTOP_W<'_>`[src]

Bit 2 - Master Stop control. This bit is write-only.

`pub fn mstdma(&mut self) -> MSTDMA_W<'_>`[src]

Bit 3 - Master DMA enable. Data operations of the I2C can be performed with DMA. Protocol type operations such as Start, address, Stop, and address match must always be done with software, typically via an interrupt. Address acknowledgement must also be done by software except when the I2C is configured to be HSCAPABLE (and address acknowledgement is handled entirely by hardware) or when Automatic Operation is enabled. When a DMA data transfer is complete, MSTDMA must be cleared prior to beginning the next operation, typically a Start or Stop.This bit is read/write.

`impl W<u32, Reg<u32, _MSTTIME>>`[src]

`pub fn mstscllow(&mut self) -> MSTSCLLOW_W<'_>`[src]

Bits 0:2 - Master SCL Low time. Specifies the minimum low time that will be asserted by this master on SCL. Other devices on the bus (masters or slaves) could lengthen this time. This corresponds to the parameter t LOW in the I2C bus specification. I2C bus specification parameters tBUF and tSU;STA have the same values and are also controlled by MSTSCLLOW.

`pub fn mstsclhigh(&mut self) -> MSTSCLHIGH_W<'_>`[src]

Bits 4:6 - Master SCL High time. Specifies the minimum high time that will be asserted by this master on SCL. Other masters in a multi-master system could shorten this time. This corresponds to the parameter tHIGH in the I2C bus specification. I2C bus specification parameters tSU;STO and tHD;STA have the same values and are also controlled by MSTSCLHIGH.

`impl W<u32, Reg<u32, _MSTDAT>>`[src]

`pub fn data(&mut self) -> DATA_W<'_>`[src]

Bits 0:7 - Master function data register. Read: read the most recently received data for the Master function. Write: transmit data using the Master function.

`impl W<u32, Reg<u32, _SLVCTL>>`[src]

`pub fn slvcontinue(&mut self) -> SLVCONTINUE_W<'_>`[src]

Bit 0 - Slave Continue.

`pub fn slvnack(&mut self) -> SLVNACK_W<'_>`[src]

Bit 1 - Slave NACK.

`pub fn slvdma(&mut self) -> SLVDMA_W<'_>`[src]

Bit 3 - Slave DMA enable.

`pub fn autoack(&mut self) -> AUTOACK_W<'_>`[src]

Bit 8 - Automatic Acknowledge.When this bit is set, it will cause an I2C header which matches SLVADR0 and the direction set by AUTOMATCHREAD to be ACKed immediately; this is used with DMA to allow processing of the data without intervention. If this bit is clear and a header matches SLVADR0, the behavior is controlled by AUTONACK in the SLVADR0 register: allowing NACK or interrupt.

`pub fn automatchread(&mut self) -> AUTOMATCHREAD_W<'_>`[src]

Bit 9 - When AUTOACK is set, this bit controls whether it matches a read or write request on the next header with an address matching SLVADR0. Since DMA needs to be configured to match the transfer direction, the direction needs to be specified. This bit allows a direction to be chosen for the next operation.

`impl W<u32, Reg<u32, _SLVDAT>>`[src]

`pub fn data(&mut self) -> DATA_W<'_>`[src]

Bits 0:7 - Slave function data register. Read: read the most recently received data for the Slave function. Write: transmit data using the Slave function.

`impl W<u32, Reg<u32, _SLVADR0>>`[src]

`pub fn sadisable(&mut self) -> SADISABLE_W<'_>`[src]

Bit 0 - Slave Address n Disable.

`pub fn slvadr(&mut self) -> SLVADR_W<'_>`[src]

Bits 1:7 - Slave Address. Seven bit slave address that is compared to received addresses if enabled.

`pub fn autonack(&mut self) -> AUTONACK_W<'_>`[src]

Bit 15 - Automatic NACK operation. Used in conjunction with AUTOACK and AUTOMATCHREAD, allows software to ignore I2C traffic while handling previous I2C data or other operations.

`impl W<u32, Reg<u32, _SLVADR1>>`[src]

`pub fn sadisable(&mut self) -> SADISABLE_W<'_>`[src]

Bit 0 - Slave Address n Disable.

`pub fn slvadr(&mut self) -> SLVADR_W<'_>`[src]

Bits 1:7 - Slave Address. Seven bit slave address that is compared to received addresses if enabled.

`impl W<u32, Reg<u32, _SLVADR2>>`[src]

`pub fn sadisable(&mut self) -> SADISABLE_W<'_>`[src]

Bit 0 - Slave Address n Disable.

`pub fn slvadr(&mut self) -> SLVADR_W<'_>`[src]

Bits 1:7 - Slave Address. Seven bit slave address that is compared to received addresses if enabled.

`impl W<u32, Reg<u32, _SLVADR3>>`[src]

`pub fn sadisable(&mut self) -> SADISABLE_W<'_>`[src]

Bit 0 - Slave Address n Disable.

`pub fn slvadr(&mut self) -> SLVADR_W<'_>`[src]

Bits 1:7 - Slave Address. Seven bit slave address that is compared to received addresses if enabled.

`impl W<u32, Reg<u32, _SLVQUAL0>>`[src]

`pub fn qualmode0(&mut self) -> QUALMODE0_W<'_>`[src]

Bit 0 - Qualify mode for slave address 0.

`pub fn slvqual0(&mut self) -> SLVQUAL0_W<'_>`[src]

Bits 1:7 - Slave address Qualifier for address 0. A value of 0 causes the address in SLVADR0 to be used as-is, assuming that it is enabled. If QUALMODE0 = 0, any bit in this field which is set to 1 will cause an automatic match of the corresponding bit of the received address when it is compared to the SLVADR0 register. If QUALMODE0 = 1, an address range is matched for address 0. This range extends from the value defined by SLVADR0 to the address defined by SLVQUAL0 (address matches when SLVADR0[7:1] <= received address <= SLVQUAL0[7:1]).

`impl W<u32, Reg<u32, _CFG1>>`[src]

`pub fn mainenable(&mut self) -> MAINENABLE_W<'_>`[src]

Bit 0 - Main enable for I 2S function in this Flexcomm

`pub fn datapause(&mut self) -> DATAPAUSE_W<'_>`[src]

Bit 1 - Data flow Pause. Allows pausing data flow between the I2S serializer/deserializer and the FIFO. This could be done in order to change streams, or while restarting after a data underflow or overflow. When paused, FIFO operations can be done without corrupting data that is in the process of being sent or received. Once a data pause has been requested, the interface may need to complete sending data that was in progress before interrupting the flow of data. Software must check that the pause is actually in effect before taking action. This is done by monitoring the DATAPAUSED flag in the STAT register. When DATAPAUSE is cleared, data transfer will resume at the beginning of the next frame.

`pub fn paircount(&mut self) -> PAIRCOUNT_W<'_>`[src]

Bits 2:3 - Provides the number of I2S channel pairs in this Flexcomm This is a read-only field whose value may be different in other Flexcomms. 00 = there is 1 I2S channel pair in this Flexcomm. 01 = there are 2 I2S channel pairs in this Flexcomm. 10 = there are 3 I2S channel pairs in this Flexcomm. 11 = there are 4 I2S channel pairs in this Flexcomm.

`pub fn mstslvcfg(&mut self) -> MSTSLVCFG_W<'_>`[src]

Bits 4:5 - Master / slave configuration selection, determining how SCK and WS are used by all channel pairs in this Flexcomm.

`pub fn mode(&mut self) -> MODE_W<'_>`[src]

Bits 6:7 - Selects the basic I2S operating mode. Other configurations modify this to obtain all supported cases. See Formats and modes for examples.

`pub fn rightlow(&mut self) -> RIGHTLOW_W<'_>`[src]

Bit 8 - Right channel data is in the Low portion of FIFO data. Essentially, this swaps left and right channel data as it is transferred to or from the FIFO. This bit is not used if the data width is greater than 24 bits or if PDMDATA = 1. Note that if the ONECHANNEL field (bit 10 of this register) = 1, the one channel to be used is the nominally the left channel. POSITION can still place that data in the frame where right channel data is normally located. if all enabled channel pairs have ONECHANNEL = 1, then RIGHTLOW = 1 is not allowed.

`pub fn leftjust(&mut self) -> LEFTJUST_W<'_>`[src]

Bit 9 - Left Justify data.

`pub fn onechannel(&mut self) -> ONECHANNEL_W<'_>`[src]

Bit 10 - Single channel mode. Applies to both transmit and receive. This configuration bit applies only to the first I2S channel pair. Other channel pairs may select this mode independently in their separate CFG1 registers.

`pub fn sck_pol(&mut self) -> SCK_POL_W<'_>`[src]

Bit 12 - SCK polarity.

`pub fn ws_pol(&mut self) -> WS_POL_W<'_>`[src]

Bit 13 - WS polarity.

`pub fn datalen(&mut self) -> DATALEN_W<'_>`[src]

Bits 16:20 - Data Length, minus 1 encoded, defines the number of data bits to be transmitted or received for all I2S channel pairs in this Flexcomm. Note that data is only driven to or received from SDA for the number of bits defined by DATALEN. DATALEN is also used in these ways by the I2S: Determines the size of data transfers between the FIFO and the I2S serializer/deserializer. See FIFO buffer configurations and usage In mode 1, 2, and 3, determines the location of right data following left data in the frame. In mode 3 (where WS has a one data slot long pulse at the beginning of each data frame) determines the duration of the WS pulse. Values: 0x00 to 0x02 = not supported 0x03 = data is 4 bits in length 0x04 = data is 5 bits in length 0x1F = data is 32 bits in length

`impl W<u32, Reg<u32, _CFG2>>`[src]

`pub fn framelen(&mut self) -> FRAMELEN_W<'_>`[src]

Bits 0:8 - Frame Length, minus 1 encoded, defines the number of clocks and data bits in the frames that this channel pair participates in. See Frame format. 0x000 to 0x002 = not supported 0x003 = frame is 4 bits in total length 0x004 = frame is 5 bits in total length 0x1FF = frame is 512 bits in total length if FRAMELEN is an defines an odd length frame (e.g. 33 clocks) in mode 0 or 1, the extra clock appears in the right half. When MODE = 3, FRAMELEN must be larger than DATALEN in order for the WS pulse to be generated correctly.

`pub fn position(&mut self) -> POSITION_W<'_>`[src]

Bits 16:24 - Data Position. Defines the location within the frame of the data for this channel pair. POSITION + DATALEN must be less than FRAMELEN. See Frame format. When MODE = 0, POSITION defines the location of data in both the left phase and right phase, starting one clock after the WS edge. In other modes, POSITION defines the location of data within the entire frame. ONECHANNEL = 1 while MODE = 0 is a special case, see the description of ONECHANNEL. The combination of DATALEN and the POSITION fields of all channel pairs must be made such that the channels do not overlap within the frame. 0x000 = data begins at bit position 0 (the first bit position) within the frame or WS phase. 0x001 = data begins at bit position 1 within the frame or WS phase. 0x002 = data begins at bit position 2 within the frame or WS phase.

`impl W<u32, Reg<u32, _STAT>>`[src]

`pub fn slvfrmerr(&mut self) -> SLVFRMERR_W<'_>`[src]

Bit 1 - Slave Frame Error flag. This applies when at least one channel pair is operating as a slave. An error indicates that the incoming WS signal did not transition as expected due to a mismatch between FRAMELEN and the actual incoming I2S stream.

`impl W<u32, Reg<u32, _DIV>>`[src]

`pub fn div(&mut self) -> DIV_W<'_>`[src]

Bits 0:11 - This field controls how this I2S block uses the Flexcomm function clock. 0x000 = The Flexcomm function clock is used directly. 0x001 = The Flexcomm function clock is divided by 2. 0x002 = The Flexcomm function clock is divided by 3. 0xFFF = The Flexcomm function clock is divided by 4,096.

`impl W<u32, Reg<u32, _FIFOCFG>>`[src]

`pub fn enabletx(&mut self) -> ENABLETX_W<'_>`[src]

Bit 0 - Enable the transmit FIFO.

`pub fn enablerx(&mut self) -> ENABLERX_W<'_>`[src]

Bit 1 - Enable the receive FIFO.

`pub fn txi2se0(&mut self) -> TXI2SE0_W<'_>`[src]

Bit 2 - Transmit I2S empty 0. Determines the value sent by the I2S in transmit mode if the TX FIFO becomes empty. This value is sent repeatedly until the I2S is paused, the error is cleared, new data is provided, and the I2S is un-paused.

`pub fn pack48(&mut self) -> PACK48_W<'_>`[src]

Bit 3 - Packing format for 48-bit data. This relates to how data is entered into or taken from the FIFO by software or DMA.

`pub fn dmatx(&mut self) -> DMATX_W<'_>`[src]

Bit 12 - DMA configuration for transmit.

`pub fn dmarx(&mut self) -> DMARX_W<'_>`[src]

Bit 13 - DMA configuration for receive.

`pub fn waketx(&mut self) -> WAKETX_W<'_>`[src]

Bit 14 - Wake-up for transmit FIFO level. This allows the device to be woken from reduced power modes (up to power-down, as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up, processes data, and goes back to sleep. The CPU will remain stopped until woken by another cause, such as DMA completion. See Hardware Wake-up control register.

`pub fn wakerx(&mut self) -> WAKERX_W<'_>`[src]

Bit 15 - Wake-up for receive FIFO level. This allows the device to be woken from reduced power modes (up to power-down, as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up, processes data, and goes back to sleep. The CPU will remain stopped until woken by another cause, such as DMA completion. See Hardware Wake-up control register.

`pub fn emptytx(&mut self) -> EMPTYTX_W<'_>`[src]

Bit 16 - Empty command for the transmit FIFO. When a 1 is written to this bit, the TX FIFO is emptied.

`pub fn emptyrx(&mut self) -> EMPTYRX_W<'_>`[src]

Bit 17 - Empty command for the receive FIFO. When a 1 is written to this bit, the RX FIFO is emptied.

`impl W<u32, Reg<u32, _FIFOSTAT>>`[src]

`pub fn txerr(&mut self) -> TXERR_W<'_>`[src]

Bit 0 - TX FIFO error. Will be set if a transmit FIFO error occurs. This could be an overflow caused by pushing data into a full FIFO, or by an underflow if the FIFO is empty when data is needed. Cleared by writing a 1 to this bit.

`pub fn rxerr(&mut self) -> RXERR_W<'_>`[src]

Bit 1 - RX FIFO error. Will be set if a receive FIFO overflow occurs, caused by software or DMA not emptying the FIFO fast enough. Cleared by writing a 1 to this bit.

`impl W<u32, Reg<u32, _FIFOTRIG>>`[src]

`pub fn txlvlena(&mut self) -> TXLVLENA_W<'_>`[src]

Bit 0 - Transmit FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET, or a DMA trigger if DMATX in FIFOCFG is set.

`pub fn rxlvlena(&mut self) -> RXLVLENA_W<'_>`[src]

Bit 1 - Receive FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET, or a DMA trigger if DMARX in FIFOCFG is set.

`pub fn txlvl(&mut self) -> TXLVL_W<'_>`[src]

Bits 8:11 - Transmit FIFO level trigger point. This field is used only when TXLVLENA = 1. If enabled to do so, the FIFO level can wake up the device just enough to perform DMA, then return to the reduced power mode. See Hardware Wake-up control register. 0 = trigger when the TX FIFO becomes empty. 1 = trigger when the TX FIFO level decreases to one entry. 15 = trigger when the TX FIFO level decreases to 15 entries (is no longer full).

`pub fn rxlvl(&mut self) -> RXLVL_W<'_>`[src]

Bits 16:19 - Receive FIFO level trigger point. The RX FIFO level is checked when a new piece of data is received. This field is used only when RXLVLENA = 1. If enabled to do so, the FIFO level can wake up the device just enough to perform DMA, then return to the reduced power mode. See Hardware Wake-up control register. 0 = trigger when the RX FIFO has received one entry (is no longer empty). 1 = trigger when the RX FIFO has received two entries. 15 = trigger when the RX FIFO has received 16 entries (has become full).

`impl W<u32, Reg<u32, _FIFOINTENSET>>`[src]

`pub fn txerr(&mut self) -> TXERR_W<'_>`[src]

Bit 0 - Determines whether an interrupt occurs when a transmit error occurs, based on the TXERR flag in the FIFOSTAT register.

`pub fn rxerr(&mut self) -> RXERR_W<'_>`[src]

Bit 1 - Determines whether an interrupt occurs when a receive error occurs, based on the RXERR flag in the FIFOSTAT register.

`pub fn txlvl(&mut self) -> TXLVL_W<'_>`[src]

Bit 2 - Determines whether an interrupt occurs when a the transmit FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register.

`pub fn rxlvl(&mut self) -> RXLVL_W<'_>`[src]

Bit 3 - Determines whether an interrupt occurs when a the receive FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register.

`impl W<u32, Reg<u32, _FIFOINTENCLR>>`[src]

`pub fn txerr(&mut self) -> TXERR_W<'_>`[src]

Bit 0 - Writing one clears the corresponding bits in the FIFOINTENSET register.

`pub fn rxerr(&mut self) -> RXERR_W<'_>`[src]

Bit 1 - Writing one clears the corresponding bits in the FIFOINTENSET register.

`pub fn txlvl(&mut self) -> TXLVL_W<'_>`[src]

Bit 2 - Writing one clears the corresponding bits in the FIFOINTENSET register.

`pub fn rxlvl(&mut self) -> RXLVL_W<'_>`[src]

Bit 3 - Writing one clears the corresponding bits in the FIFOINTENSET register.

`impl W<u32, Reg<u32, _FIFOWR>>`[src]

`pub fn txdata(&mut self) -> TXDATA_W<'_>`[src]

Bits 0:31 - Transmit data to the FIFO. The number of bits used depends on configuration details.

`impl W<u32, Reg<u32, _FIFOWR48H>>`[src]

`pub fn txdata(&mut self) -> TXDATA_W<'_>`[src]

Bits 0:23 - Transmit data to the FIFO. Whether this register is used and the number of bits used depends on configuration details.

`impl W<u32, Reg<u32, _CFG>>`[src]

`pub fn enable(&mut self) -> ENABLE_W<'_>`[src]

Bit 0 - SPI enable.

`pub fn master(&mut self) -> MASTER_W<'_>`[src]

Bit 2 - Master mode select.

`pub fn lsbf(&mut self) -> LSBF_W<'_>`[src]

Bit 3 - LSB First mode enable.

`pub fn cpha(&mut self) -> CPHA_W<'_>`[src]

Bit 4 - Clock Phase select.

`pub fn cpol(&mut self) -> CPOL_W<'_>`[src]

Bit 5 - Clock Polarity select.

`pub fn loop_(&mut self) -> LOOP_W<'_>`[src]

Bit 7 - Loopback mode enable. Loopback mode applies only to Master mode, and connects transmit and receive data connected together to allow simple software testing.

`pub fn spol0(&mut self) -> SPOL0_W<'_>`[src]

Bit 8 - SSEL0 Polarity select.

`pub fn spol1(&mut self) -> SPOL1_W<'_>`[src]

Bit 9 - SSEL1 Polarity select.

`pub fn spol2(&mut self) -> SPOL2_W<'_>`[src]

Bit 10 - SSEL2 Polarity select.

`pub fn spol3(&mut self) -> SPOL3_W<'_>`[src]

Bit 11 - SSEL3 Polarity select.

`impl W<u32, Reg<u32, _DLY>>`[src]

`pub fn pre_delay(&mut self) -> PRE_DELAY_W<'_>`[src]

Bits 0:3 - Controls the amount of time between SSEL assertion and the beginning of a data transfer. There is always one SPI clock time between SSEL assertion and the first clock edge. This is not considered part of the pre-delay. 0x0 = No additional time is inserted. 0x1 = 1 SPI clock time is inserted. 0x2 = 2 SPI clock times are inserted. 0xF = 15 SPI clock times are inserted.

`pub fn post_delay(&mut self) -> POST_DELAY_W<'_>`[src]

Bits 4:7 - Controls the amount of time between the end of a data transfer and SSEL deassertion. 0x0 = No additional time is inserted. 0x1 = 1 SPI clock time is inserted. 0x2 = 2 SPI clock times are inserted. 0xF = 15 SPI clock times are inserted.

`pub fn frame_delay(&mut self) -> FRAME_DELAY_W<'_>`[src]

Bits 8:11 - If the EOF flag is set, controls the minimum amount of time between the current frame and the next frame (or SSEL deassertion if EOT). 0x0 = No additional time is inserted. 0x1 = 1 SPI clock time is inserted. 0x2 = 2 SPI clock times are inserted. 0xF = 15 SPI clock times are inserted.

`pub fn transfer_delay(&mut self) -> TRANSFER_DELAY_W<'_>`[src]

Bits 12:15 - Controls the minimum amount of time that the SSEL is deasserted between transfers. 0x0 = The minimum time that SSEL is deasserted is 1 SPI clock time. (Zero added time.) 0x1 = The minimum time that SSEL is deasserted is 2 SPI clock times. 0x2 = The minimum time that SSEL is deasserted is 3 SPI clock times. 0xF = The minimum time that SSEL is deasserted is 16 SPI clock times.

`impl W<u32, Reg<u32, _STAT>>`[src]

`pub fn ssa(&mut self) -> SSA_W<'_>`[src]

Bit 4 - Slave Select Assert. This flag is set whenever any slave select transitions from deasserted to asserted, in both master and slave modes. This allows determining when the SPI transmit/receive functions become busy, and allows waking up the device from reduced power modes when a slave mode access begins. This flag is cleared by software.

`pub fn ssd(&mut self) -> SSD_W<'_>`[src]

Bit 5 - Slave Select Deassert. This flag is set whenever any asserted slave selects transition to deasserted, in both master and slave modes. This allows determining when the SPI transmit/receive functions become idle. This flag is cleared by software.

`pub fn endtransfer(&mut self) -> ENDTRANSFER_W<'_>`[src]

Bit 7 - End Transfer control bit. Software can set this bit to force an end to the current transfer when the transmitter finishes any activity already in progress, as if the EOT flag had been set prior to the last transmission. This capability is included to support cases where it is not known when transmit data is written that it will be the end of a transfer. The bit is cleared when the transmitter becomes idle as the transfer comes to an end. Forcing an end of transfer in this manner causes any specified FRAME_DELAY and TRANSFER_DELAY to be inserted.

`impl W<u32, Reg<u32, _INTENSET>>`[src]

`pub fn ssaen(&mut self) -> SSAEN_W<'_>`[src]

Bit 4 - Slave select assert interrupt enable. Determines whether an interrupt occurs when the Slave Select is asserted.

`pub fn ssden(&mut self) -> SSDEN_W<'_>`[src]

Bit 5 - Slave select deassert interrupt enable. Determines whether an interrupt occurs when the Slave Select is deasserted.

`pub fn mstidleen(&mut self) -> MSTIDLEEN_W<'_>`[src]

Bit 8 - Master idle interrupt enable.

`impl W<u32, Reg<u32, _INTENCLR>>`[src]

`pub fn ssaen(&mut self) -> SSAEN_W<'_>`[src]

Bit 4 - Writing 1 clears the corresponding bit in the INTENSET register.

`pub fn ssden(&mut self) -> SSDEN_W<'_>`[src]

Bit 5 - Writing 1 clears the corresponding bit in the INTENSET register.

`pub fn mstidle(&mut self) -> MSTIDLE_W<'_>`[src]

Bit 8 - Writing 1 clears the corresponding bit in the INTENSET register.

`impl W<u32, Reg<u32, _DIV>>`[src]

`pub fn divval(&mut self) -> DIVVAL_W<'_>`[src]

Bits 0:15 - Rate divider value. Specifies how the Flexcomm clock (FCLK) is divided to produce the SPI clock rate in master mode. DIVVAL is -1 encoded such that the value 0 results in FCLK/1, the value 1 results in FCLK/2, up to the maximum possible divide value of 0xFFFF, which results in FCLK/65536.

`impl W<u32, Reg<u32, _FIFOCFG>>`[src]

`pub fn enabletx(&mut self) -> ENABLETX_W<'_>`[src]

Bit 0 - Enable the transmit FIFO.

`pub fn enablerx(&mut self) -> ENABLERX_W<'_>`[src]

Bit 1 - Enable the receive FIFO.

`pub fn dmatx(&mut self) -> DMATX_W<'_>`[src]

Bit 12 - DMA configuration for transmit.

`pub fn dmarx(&mut self) -> DMARX_W<'_>`[src]

Bit 13 - DMA configuration for receive.

`pub fn waketx(&mut self) -> WAKETX_W<'_>`[src]

Bit 14 - Wake-up for transmit FIFO level. This allows the device to be woken from reduced power modes (up to power-down, as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up, processes data, and goes back to sleep. The CPU will remain stopped until woken by another cause, such as DMA completion. See Hardware Wake-up control register.

`pub fn wakerx(&mut self) -> WAKERX_W<'_>`[src]

Bit 15 - Wake-up for receive FIFO level. This allows the device to be woken from reduced power modes (up to power-down, as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up, processes data, and goes back to sleep. The CPU will remain stopped until woken by another cause, such as DMA completion. See Hardware Wake-up control register.

`pub fn emptytx(&mut self) -> EMPTYTX_W<'_>`[src]

Bit 16 - Empty command for the transmit FIFO. When a 1 is written to this bit, the TX FIFO is emptied.

`pub fn emptyrx(&mut self) -> EMPTYRX_W<'_>`[src]

Bit 17 - Empty command for the receive FIFO. When a 1 is written to this bit, the RX FIFO is emptied.

`impl W<u32, Reg<u32, _FIFOSTAT>>`[src]

`pub fn txerr(&mut self) -> TXERR_W<'_>`[src]

Bit 0 - TX FIFO error. Will be set if a transmit FIFO error occurs. This could be an overflow caused by pushing data into a full FIFO, or by an underflow if the FIFO is empty when data is needed. Cleared by writing a 1 to this bit.

`pub fn rxerr(&mut self) -> RXERR_W<'_>`[src]

Bit 1 - RX FIFO error. Will be set if a receive FIFO overflow occurs, caused by software or DMA not emptying the FIFO fast enough. Cleared by writing a 1 to this bit.

`impl W<u32, Reg<u32, _FIFOTRIG>>`[src]

`pub fn txlvlena(&mut self) -> TXLVLENA_W<'_>`[src]

Bit 0 - Transmit FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET, or a DMA trigger if DMATX in FIFOCFG is set.

`pub fn rxlvlena(&mut self) -> RXLVLENA_W<'_>`[src]

Bit 1 - Receive FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET, or a DMA trigger if DMARX in FIFOCFG is set.

`pub fn txlvl(&mut self) -> TXLVL_W<'_>`[src]

Bits 8:11 - Transmit FIFO level trigger point. This field is used only when TXLVLENA = 1. If enabled to do so, the FIFO level can wake up the device just enough to perform DMA, then return to the reduced power mode. See Hardware Wake-up control register. 0 = trigger when the TX FIFO becomes empty. 1 = trigger when the TX FIFO level decreases to one entry. 15 = trigger when the TX FIFO level decreases to 15 entries (is no longer full).

`pub fn rxlvl(&mut self) -> RXLVL_W<'_>`[src]

Bits 16:19 - Receive FIFO level trigger point. The RX FIFO level is checked when a new piece of data is received. This field is used only when RXLVLENA = 1. If enabled to do so, the FIFO level can wake up the device just enough to perform DMA, then return to the reduced power mode. See Hardware Wake-up control register. 0 = trigger when the RX FIFO has received one entry (is no longer empty). 1 = trigger when the RX FIFO has received two entries. 15 = trigger when the RX FIFO has received 16 entries (has become full).

`impl W<u32, Reg<u32, _FIFOINTENSET>>`[src]

`pub fn txerr(&mut self) -> TXERR_W<'_>`[src]

Bit 0 - Determines whether an interrupt occurs when a transmit error occurs, based on the TXERR flag in the FIFOSTAT register.

`pub fn rxerr(&mut self) -> RXERR_W<'_>`[src]

Bit 1 - Determines whether an interrupt occurs when a receive error occurs, based on the RXERR flag in the FIFOSTAT register.

`pub fn txlvl(&mut self) -> TXLVL_W<'_>`[src]

Bit 2 - Determines whether an interrupt occurs when a the transmit FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register.

`pub fn rxlvl(&mut self) -> RXLVL_W<'_>`[src]

Bit 3 - Determines whether an interrupt occurs when a the receive FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register.

`impl W<u32, Reg<u32, _FIFOINTENCLR>>`[src]

`pub fn txerr(&mut self) -> TXERR_W<'_>`[src]

Bit 0 - Writing one clears the corresponding bits in the FIFOINTENSET register.

`pub fn rxerr(&mut self) -> RXERR_W<'_>`[src]

Bit 1 - Writing one clears the corresponding bits in the FIFOINTENSET register.

`pub fn txlvl(&mut self) -> TXLVL_W<'_>`[src]

Bit 2 - Writing one clears the corresponding bits in the FIFOINTENSET register.

`pub fn rxlvl(&mut self) -> RXLVL_W<'_>`[src]

Bit 3 - Writing one clears the corresponding bits in the FIFOINTENSET register.

`impl W<u32, Reg<u32, _FIFOWR>>`[src]

`pub fn txdata(&mut self) -> TXDATA_W<'_>`[src]

Bits 0:15 - Transmit data to the FIFO.

`pub fn txssel0_n(&mut self) -> TXSSEL0_N_W<'_>`[src]

Bit 16 - Transmit slave select. This field asserts SSEL0 in master mode. The output on the pin is active LOW by default.

`pub fn txssel1_n(&mut self) -> TXSSEL1_N_W<'_>`[src]

Bit 17 - Transmit slave select. This field asserts SSEL1 in master mode. The output on the pin is active LOW by default.

`pub fn txssel2_n(&mut self) -> TXSSEL2_N_W<'_>`[src]

Bit 18 - Transmit slave select. This field asserts SSEL2 in master mode. The output on the pin is active LOW by default.

`pub fn txssel3_n(&mut self) -> TXSSEL3_N_W<'_>`[src]

Bit 19 - Transmit slave select. This field asserts SSEL3 in master mode. The output on the pin is active LOW by default.

`pub fn eot(&mut self) -> EOT_W<'_>`[src]

Bit 20 - End of transfer. The asserted SSEL will be deasserted at the end of a transfer and remain so far at least the time specified by the Transfer_delay value in the DLY register.

`pub fn eof(&mut self) -> EOF_W<'_>`[src]

Bit 21 - End of frame. Between frames, a delay may be inserted, as defined by the Frame_delay value in the DLY register. The end of a frame may not be particularly meaningful if the Frame_delay value = 0. This control can be used as part of the support for frame lengths greater than 16 bits.

`pub fn rxignore(&mut self) -> RXIGNORE_W<'_>`[src]

Bit 22 - Receive Ignore. This allows data to be transmitted using the SPI without the need to read unneeded data from the receiver. Setting this bit simplifies the transmit process and can be used with the DMA.

`pub fn len(&mut self) -> LEN_W<'_>`[src]

Bits 24:27 - Data Length. Specifies the data length from 4 to 16 bits. Note that transfer lengths greater than 16 bits are supported by implementing multiple sequential transmits. 0x0-2 = Reserved. 0x3 = Data transfer is 4 bits in length. 0x4 = Data transfer is 5 bits in length. 0xF = Data transfer is 16 bits in length.

`impl W<u32, Reg<u32, _CFG>>`[src]

`pub fn enable(&mut self) -> ENABLE_W<'_>`[src]

Bit 0 - USART Enable.

`pub fn datalen(&mut self) -> DATALEN_W<'_>`[src]

Bits 2:3 - Selects the data size for the USART.

`pub fn paritysel(&mut self) -> PARITYSEL_W<'_>`[src]

Bits 4:5 - Selects what type of parity is used by the USART.

`pub fn stoplen(&mut self) -> STOPLEN_W<'_>`[src]

Bit 6 - Number of stop bits appended to transmitted data. Only a single stop bit is required for received data.

`pub fn mode32k(&mut self) -> MODE32K_W<'_>`[src]

Bit 7 - Selects standard or 32 kHz clocking mode.

`pub fn linmode(&mut self) -> LINMODE_W<'_>`[src]

Bit 8 - LIN break mode enable.

`pub fn ctsen(&mut self) -> CTSEN_W<'_>`[src]

Bit 9 - CTS Enable. Determines whether CTS is used for flow control. CTS can be from the input pin, or from the USART's own RTS if loopback mode is enabled.

`pub fn syncen(&mut self) -> SYNCEN_W<'_>`[src]

Bit 11 - Selects synchronous or asynchronous operation.

`pub fn clkpol(&mut self) -> CLKPOL_W<'_>`[src]

Bit 12 - Selects the clock polarity and sampling edge of received data in synchronous mode.

`pub fn syncmst(&mut self) -> SYNCMST_W<'_>`[src]

Bit 14 - Synchronous mode Master select.

`pub fn loop_(&mut self) -> LOOP_W<'_>`[src]

Bit 15 - Selects data loopback mode.

`pub fn oeta(&mut self) -> OETA_W<'_>`[src]

Bit 18 - Output Enable Turnaround time enable for RS-485 operation.

`pub fn autoaddr(&mut self) -> AUTOADDR_W<'_>`[src]

Bit 19 - Automatic Address matching enable.

`pub fn oesel(&mut self) -> OESEL_W<'_>`[src]

Bit 20 - Output Enable Select.

`pub fn oepol(&mut self) -> OEPOL_W<'_>`[src]

Bit 21 - Output Enable Polarity.

`pub fn rxpol(&mut self) -> RXPOL_W<'_>`[src]

Bit 22 - Receive data polarity.

`pub fn txpol(&mut self) -> TXPOL_W<'_>`[src]

Bit 23 - Transmit data polarity.

`impl W<u32, Reg<u32, _CTL>>`[src]

`pub fn txbrken(&mut self) -> TXBRKEN_W<'_>`[src]

Bit 1 - Break Enable.

`pub fn addrdet(&mut self) -> ADDRDET_W<'_>`[src]

Bit 2 - Enable address detect mode.

`pub fn txdis(&mut self) -> TXDIS_W<'_>`[src]

Bit 6 - Transmit Disable.

`pub fn cc(&mut self) -> CC_W<'_>`[src]

Bit 8 - Continuous Clock generation. By default, SCLK is only output while data is being transmitted in synchronous mode.

`pub fn clrcconrx(&mut self) -> CLRCCONRX_W<'_>`[src]

Bit 9 - Clear Continuous Clock.

`pub fn autobaud(&mut self) -> AUTOBAUD_W<'_>`[src]

Bit 16 - Autobaud enable.

`impl W<u32, Reg<u32, _STAT>>`[src]

`pub fn deltacts(&mut self) -> DELTACTS_W<'_>`[src]

Bit 5 - This bit is set when a change in the state is detected for the CTS flag above. This bit is cleared by software.

`pub fn deltarxbrk(&mut self) -> DELTARXBRK_W<'_>`[src]

Bit 11 - This bit is set when a change in the state of receiver break detection occurs. Cleared by software.

`pub fn start(&mut self) -> START_W<'_>`[src]

Bit 12 - This bit is set when a start is detected on the receiver input. Its purpose is primarily to allow wake-up from Deep-sleep or Power-down mode immediately when a start is detected. Cleared by software.

`pub fn framerrint(&mut self) -> FRAMERRINT_W<'_>`[src]

Bit 13 - Framing Error interrupt flag. This flag is set when a character is received with a missing stop bit at the expected location. This could be an indication of a baud rate or configuration mismatch with the transmitting source.

`pub fn parityerrint(&mut self) -> PARITYERRINT_W<'_>`[src]

Bit 14 - Parity Error interrupt flag. This flag is set when a parity error is detected in a received character.

`pub fn rxnoiseint(&mut self) -> RXNOISEINT_W<'_>`[src]

Bit 15 - Received Noise interrupt flag. Three samples of received data are taken in order to determine the value of each received data bit, except in synchronous mode. This acts as a noise filter if one sample disagrees. This flag is set when a received data bit contains one disagreeing sample. This could indicate line noise, a baud rate or character format mismatch, or loss of synchronization during data reception.

`pub fn aberr(&mut self) -> ABERR_W<'_>`[src]

Bit 16 - Auto baud Error. An auto baud error can occur if the BRG counts to its limit before the end of the start bit that is being measured, essentially an auto baud time-out.

`impl W<u32, Reg<u32, _INTENSET>>`[src]

`pub fn txidleen(&mut self) -> TXIDLEEN_W<'_>`[src]

Bit 3 - When 1, enables an interrupt when the transmitter becomes idle (TXIDLE = 1).

`pub fn deltactsen(&mut self) -> DELTACTSEN_W<'_>`[src]

Bit 5 - When 1, enables an interrupt when there is a change in the state of the CTS input.

`pub fn txdisen(&mut self) -> TXDISEN_W<'_>`[src]

Bit 6 - When 1, enables an interrupt when the transmitter is fully disabled as indicated by the TXDISINT flag in STAT. See description of the TXDISINT bit for details.

`pub fn deltarxbrken(&mut self) -> DELTARXBRKEN_W<'_>`[src]

Bit 11 - When 1, enables an interrupt when a change of state has occurred in the detection of a received break condition (break condition asserted or deasserted).

`pub fn starten(&mut self) -> STARTEN_W<'_>`[src]

Bit 12 - When 1, enables an interrupt when a received start bit has been detected.

`pub fn framerren(&mut self) -> FRAMERREN_W<'_>`[src]

Bit 13 - When 1, enables an interrupt when a framing error has been detected.

`pub fn parityerren(&mut self) -> PARITYERREN_W<'_>`[src]

Bit 14 - When 1, enables an interrupt when a parity error has been detected.

`pub fn rxnoiseen(&mut self) -> RXNOISEEN_W<'_>`[src]

Bit 15 - When 1, enables an interrupt when noise is detected. See description of the RXNOISEINT bit in Table 354.

`pub fn aberren(&mut self) -> ABERREN_W<'_>`[src]

Bit 16 - When 1, enables an interrupt when an auto baud error occurs.

`impl W<u32, Reg<u32, _INTENCLR>>`[src]

`pub fn txidleclr(&mut self) -> TXIDLECLR_W<'_>`[src]

Bit 3 - Writing 1 clears the corresponding bit in the INTENSET register.

`pub fn deltactsclr(&mut self) -> DELTACTSCLR_W<'_>`[src]

Bit 5 - Writing 1 clears the corresponding bit in the INTENSET register.

`pub fn txdisclr(&mut self) -> TXDISCLR_W<'_>`[src]

Bit 6 - Writing 1 clears the corresponding bit in the INTENSET register.

`pub fn deltarxbrkclr(&mut self) -> DELTARXBRKCLR_W<'_>`[src]

Bit 11 - Writing 1 clears the corresponding bit in the INTENSET register.

`pub fn startclr(&mut self) -> STARTCLR_W<'_>`[src]

Bit 12 - Writing 1 clears the corresponding bit in the INTENSET register.

`pub fn framerrclr(&mut self) -> FRAMERRCLR_W<'_>`[src]

Bit 13 - Writing 1 clears the corresponding bit in the INTENSET register.

`pub fn parityerrclr(&mut self) -> PARITYERRCLR_W<'_>`[src]

Bit 14 - Writing 1 clears the corresponding bit in the INTENSET register.

`pub fn rxnoiseclr(&mut self) -> RXNOISECLR_W<'_>`[src]

Bit 15 - Writing 1 clears the corresponding bit in the INTENSET register.

`pub fn aberrclr(&mut self) -> ABERRCLR_W<'_>`[src]

Bit 16 - Writing 1 clears the corresponding bit in the INTENSET register.

`impl W<u32, Reg<u32, _BRG>>`[src]

`pub fn brgval(&mut self) -> BRGVAL_W<'_>`[src]

Bits 0:15 - This value is used to divide the USART input clock to determine the baud rate, based on the input clock from the FRG. 0 = FCLK is used directly by the USART function. 1 = FCLK is divided by 2 before use by the USART function. 2 = FCLK is divided by 3 before use by the USART function. 0xFFFF = FCLK is divided by 65,536 before use by the USART function.

`impl W<u32, Reg<u32, _OSR>>`[src]

`pub fn osrval(&mut self) -> OSRVAL_W<'_>`[src]

Bits 0:3 - Oversample Selection Value. 0 to 3 = not supported 0x4 = 5 function clocks are used to transmit and receive each data bit. 0x5 = 6 function clocks are used to transmit and receive each data bit. 0xF= 16 function clocks are used to transmit and receive each data bit.

`impl W<u32, Reg<u32, _ADDR>>`[src]

`pub fn address(&mut self) -> ADDRESS_W<'_>`[src]

Bits 0:7 - 8-bit address used with automatic address matching. Used when address detection is enabled (ADDRDET in CTL = 1) and automatic address matching is enabled (AUTOADDR in CFG = 1).

`impl W<u32, Reg<u32, _FIFOCFG>>`[src]

`pub fn enabletx(&mut self) -> ENABLETX_W<'_>`[src]

Bit 0 - Enable the transmit FIFO.

`pub fn enablerx(&mut self) -> ENABLERX_W<'_>`[src]

Bit 1 - Enable the receive FIFO.

`pub fn dmatx(&mut self) -> DMATX_W<'_>`[src]

Bit 12 - DMA configuration for transmit.

`pub fn dmarx(&mut self) -> DMARX_W<'_>`[src]

Bit 13 - DMA configuration for receive.

`pub fn waketx(&mut self) -> WAKETX_W<'_>`[src]

Bit 14 - Wake-up for transmit FIFO level. This allows the device to be woken from reduced power modes (up to power-down, as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up, processes data, and goes back to sleep. The CPU will remain stopped until woken by another cause, such as DMA completion. See Hardware Wake-up control register.

`pub fn wakerx(&mut self) -> WAKERX_W<'_>`[src]

Bit 15 - Wake-up for receive FIFO level. This allows the device to be woken from reduced power modes (up to power-down, as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up, processes data, and goes back to sleep. The CPU will remain stopped until woken by another cause, such as DMA completion. See Hardware Wake-up control register.

`pub fn emptytx(&mut self) -> EMPTYTX_W<'_>`[src]

Bit 16 - Empty command for the transmit FIFO. When a 1 is written to this bit, the TX FIFO is emptied.

`pub fn emptyrx(&mut self) -> EMPTYRX_W<'_>`[src]

Bit 17 - Empty command for the receive FIFO. When a 1 is written to this bit, the RX FIFO is emptied.

`impl W<u32, Reg<u32, _FIFOSTAT>>`[src]

`pub fn txerr(&mut self) -> TXERR_W<'_>`[src]

Bit 0 - TX FIFO error. Will be set if a transmit FIFO error occurs. This could be an overflow caused by pushing data into a full FIFO, or by an underflow if the FIFO is empty when data is needed. Cleared by writing a 1 to this bit.

`pub fn rxerr(&mut self) -> RXERR_W<'_>`[src]

Bit 1 - RX FIFO error. Will be set if a receive FIFO overflow occurs, caused by software or DMA not emptying the FIFO fast enough. Cleared by writing a 1 to this bit.

`impl W<u32, Reg<u32, _FIFOTRIG>>`[src]

`pub fn txlvlena(&mut self) -> TXLVLENA_W<'_>`[src]

Bit 0 - Transmit FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET, or a DMA trigger if DMATX in FIFOCFG is set.

`pub fn rxlvlena(&mut self) -> RXLVLENA_W<'_>`[src]

Bit 1 - Receive FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET, or a DMA trigger if DMARX in FIFOCFG is set.

`pub fn txlvl(&mut self) -> TXLVL_W<'_>`[src]

Bits 8:11 - Transmit FIFO level trigger point. This field is used only when TXLVLENA = 1. If enabled to do so, the FIFO level can wake up the device just enough to perform DMA, then return to the reduced power mode. See Hardware Wake-up control register. 0 = trigger when the TX FIFO becomes empty. 1 = trigger when the TX FIFO level decreases to one entry. 15 = trigger when the TX FIFO level decreases to 15 entries (is no longer full).

`pub fn rxlvl(&mut self) -> RXLVL_W<'_>`[src]

Bits 16:19 - Receive FIFO level trigger point. The RX FIFO level is checked when a new piece of data is received. This field is used only when RXLVLENA = 1. If enabled to do so, the FIFO level can wake up the device just enough to perform DMA, then return to the reduced power mode. See Hardware Wake-up control register. 0 = trigger when the RX FIFO has received one entry (is no longer empty). 1 = trigger when the RX FIFO has received two entries. 15 = trigger when the RX FIFO has received 16 entries (has become full).

`impl W<u32, Reg<u32, _FIFOINTENSET>>`[src]

`pub fn txerr(&mut self) -> TXERR_W<'_>`[src]

Bit 0 - Determines whether an interrupt occurs when a transmit error occurs, based on the TXERR flag in the FIFOSTAT register.

`pub fn rxerr(&mut self) -> RXERR_W<'_>`[src]

Bit 1 - Determines whether an interrupt occurs when a receive error occurs, based on the RXERR flag in the FIFOSTAT register.

`pub fn txlvl(&mut self) -> TXLVL_W<'_>`[src]

Bit 2 - Determines whether an interrupt occurs when a the transmit FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register.

`pub fn rxlvl(&mut self) -> RXLVL_W<'_>`[src]

Bit 3 - Determines whether an interrupt occurs when a the receive FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register.

`impl W<u32, Reg<u32, _FIFOINTENCLR>>`[src]

`pub fn txerr(&mut self) -> TXERR_W<'_>`[src]

Bit 0 - Writing one clears the corresponding bits in the FIFOINTENSET register.

`pub fn rxerr(&mut self) -> RXERR_W<'_>`[src]

Bit 1 - Writing one clears the corresponding bits in the FIFOINTENSET register.

`pub fn txlvl(&mut self) -> TXLVL_W<'_>`[src]

Bit 2 - Writing one clears the corresponding bits in the FIFOINTENSET register.

`pub fn rxlvl(&mut self) -> RXLVL_W<'_>`[src]

Bit 3 - Writing one clears the corresponding bits in the FIFOINTENSET register.

`impl W<u32, Reg<u32, _FIFOWR>>`[src]

`pub fn txdata(&mut self) -> TXDATA_W<'_>`[src]

Bits 0:8 - Transmit data to the FIFO.

`impl W<u32, Reg<u32, _IRQ>>`[src]

`pub fn intreq(&mut self) -> INTREQ_W<'_>`[src]

Bits 0:31 - If any bit is set, an interrupt request is sent to the Cortex-M0+ interrupt controller.

`impl W<u32, Reg<u32, _IRQSET>>`[src]

`pub fn intreqset(&mut self) -> INTREQSET_W<'_>`[src]

Bits 0:31 - Writing 1 sets the corresponding bit in the IRQ0 register.

`impl W<u32, Reg<u32, _IRQCLR>>`[src]

`pub fn intreqclr(&mut self) -> INTREQCLR_W<'_>`[src]

Bits 0:31 - Writing 1 clears the corresponding bit in the IRQ0 register.

`impl W<u32, Reg<u32, _MUTEX>>`[src]

`pub fn ex(&mut self) -> EX_W<'_>`[src]

Bit 0 - Cleared when read, set when written. See usage description above.

`impl W<u8, Reg<u8, _B_>>`[src]

`pub fn pbyte(&mut self) -> PBYTE_W<'_>`[src]

Bit 0 - Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package.

`impl W<u32, Reg<u32, _W_>>`[src]

`pub fn pword(&mut self) -> PWORD_W<'_>`[src]

Bits 0:31 - Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package.

`impl W<u32, Reg<u32, _DIR>>`[src]

`pub fn dirp(&mut self) -> DIRP_W<'_>`[src]

Bits 0:31 - Selects pin direction for pin PIOm_n (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on the specific device and package. 0 = input. 1 = output.

`impl W<u32, Reg<u32, _MASK>>`[src]

`pub fn maskp(&mut self) -> MASKP_W<'_>`[src]

Bits 0:31 - Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on the specific device and package.0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected.

`impl W<u32, Reg<u32, _PIN>>`[src]

`pub fn port(&mut self) -> PORT_W<'_>`[src]

Bits 0:31 - Reads pin states or loads output bits (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on the specific device and package. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit.

`impl W<u32, Reg<u32, _MPIN>>`[src]

`pub fn mportp(&mut self) -> MPORTP_W<'_>`[src]

Bits 0:31 - Masked port register (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on the specific device and package. 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0.

`impl W<u32, Reg<u32, _SET>>`[src]

`pub fn setp(&mut self) -> SETP_W<'_>`[src]

Bits 0:31 - Read or set output bits (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on the specific device and package. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit.

`impl W<u32, Reg<u32, _CLR>>`[src]

`pub fn clrp(&mut self) -> CLRP_W<'_>`[src]

Bits 0:31 - Clear output bits (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on the specific device and package. 0 = No operation. 1 = Clear output bit.

`impl W<u32, Reg<u32, _NOT>>`[src]

`pub fn notp(&mut self) -> NOTP_W<'_>`[src]

Bits 0:31 - Toggle output bits (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on the specific device and package. 0 = no operation. 1 = Toggle output bit.

`impl W<u32, Reg<u32, _DIRSET>>`[src]

`pub fn dirsetp(&mut self) -> DIRSETP_W<'_>`[src]

Bits 0:31 - Set direction bits (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on the specific device and package. 0 = No operation. 1 = Set direction bit.

`impl W<u32, Reg<u32, _DIRCLR>>`[src]

`pub fn dirclrp(&mut self) -> DIRCLRP_W<'_>`[src]

Bits 0:31 - Clear direction bits (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on the specific device and package. 0 = No operation. 1 = Clear direction bit.

`impl W<u32, Reg<u32, _DIRNOT>>`[src]

`pub fn dirnotp(&mut self) -> DIRNOTP_W<'_>`[src]

Bits 0:31 - Toggle direction bits (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on the specific device and package. 0 = no operation. 1 = Toggle direction bit.

`impl W<u32, Reg<u32, _DEVCMDSTAT>>`[src]

`pub fn dev_addr(&mut self) -> DEV_ADDR_W<'_>`[src]

Bits 0:6 - USB device address.

`pub fn dev_en(&mut self) -> DEV_EN_W<'_>`[src]

Bit 7 - USB device enable.

`pub fn setup(&mut self) -> SETUP_W<'_>`[src]

Bit 8 - SETUP token received.

`pub fn force_needclk(&mut self) -> FORCE_NEEDCLK_W<'_>`[src]

Bit 9 - Forces the NEEDCLK output to always be on:.

`pub fn lpm_sup(&mut self) -> LPM_SUP_W<'_>`[src]

Bit 11 - LPM Supported:.

`pub fn intonnak_ao(&mut self) -> INTONNAK_AO_W<'_>`[src]

Bit 12 - Interrupt on NAK for interrupt and bulk OUT EP:.

`pub fn intonnak_ai(&mut self) -> INTONNAK_AI_W<'_>`[src]

Bit 13 - Interrupt on NAK for interrupt and bulk IN EP:.

`pub fn intonnak_co(&mut self) -> INTONNAK_CO_W<'_>`[src]

Bit 14 - Interrupt on NAK for control OUT EP:.

`pub fn intonnak_ci(&mut self) -> INTONNAK_CI_W<'_>`[src]

Bit 15 - Interrupt on NAK for control IN EP:.

`pub fn dcon(&mut self) -> DCON_W<'_>`[src]

Bit 16 - Device status - connect.

`pub fn dsus(&mut self) -> DSUS_W<'_>`[src]

Bit 17 - Device status - suspend.

`pub fn lpm_sus(&mut self) -> LPM_SUS_W<'_>`[src]

Bit 19 - Device status - LPM Suspend.

`pub fn dcon_c(&mut self) -> DCON_C_W<'_>`[src]

Bit 24 - Device status - connect change.

`pub fn dsus_c(&mut self) -> DSUS_C_W<'_>`[src]

Bit 25 - Device status - suspend change.

`pub fn dres_c(&mut self) -> DRES_C_W<'_>`[src]

Bit 26 - Device status - reset change.

`pub fn phy_test_mode(&mut self) -> PHY_TEST_MODE_W<'_>`[src]

Bits 29:31 - This field is written by firmware to put the PHY into a test mode as defined by the USB2.0 specification

`impl W<u32, Reg<u32, _EPLISTSTART>>`[src]

`pub fn ep_list(&mut self) -> EP_LIST_W<'_>`[src]

Bits 8:31 - Programmable portion of the USB EP command/status list address. The upper 12 bits should be 0x401.

`impl W<u32, Reg<u32, _DATABUFSTART>>`[src]

`pub fn da_buf(&mut self) -> DA_BUF_W<'_>`[src]

Bits 0:31 - Start address of the memory page where all endpoint data buffers are located.

`impl W<u32, Reg<u32, _LPM>>`[src]

`pub fn hird_sw(&mut self) -> HIRD_SW_W<'_>`[src]

Bits 4:7 - Host Initiated Resume Duration - SW.

`pub fn data_pending(&mut self) -> DATA_PENDING_W<'_>`[src]

Bit 8 - As long as this bit is set to one and LPM supported bit is set to one, HW will return a NYET handshake on every LPM token it receives.

`impl W<u32, Reg<u32, _EPSKIP>>`[src]

`pub fn skip(&mut self) -> SKIP_W<'_>`[src]

Bits 0:11 - Endpoint skip: Writing 1 to one of these bits, will indicate to HW that it must deactivate the buffer assigned to this endpoint and return control back to software.

`impl W<u32, Reg<u32, _EPINUSE>>`[src]

`pub fn buf(&mut self) -> BUF_W<'_>`[src]

Bits 2:11 - Buffer in use: This register has one bit per physical endpoint.

`impl W<u32, Reg<u32, _EPBUFCFG>>`[src]

`pub fn buf_sb(&mut self) -> BUF_SB_W<'_>`[src]

Bits 2:11 - Buffer usage: This register has one bit per physical endpoint.

`impl W<u32, Reg<u32, _INTSTAT>>`[src]

`pub fn ep0out(&mut self) -> EP0OUT_W<'_>`[src]

Bit 0 - Interrupt status register bit for the Control EP0 OUT direction.

`pub fn ep0in(&mut self) -> EP0IN_W<'_>`[src]

Bit 1 - Interrupt status register bit for the Control EP0 IN direction.

`pub fn ep1out(&mut self) -> EP1OUT_W<'_>`[src]

Bit 2 - Interrupt status register bit for the EP1 OUT direction.

`pub fn ep1in(&mut self) -> EP1IN_W<'_>`[src]

Bit 3 - Interrupt status register bit for the EP1 IN direction.

`pub fn ep2out(&mut self) -> EP2OUT_W<'_>`[src]

Bit 4 - Interrupt status register bit for the EP2 OUT direction.

`pub fn ep2in(&mut self) -> EP2IN_W<'_>`[src]

Bit 5 - Interrupt status register bit for the EP2 IN direction.

`pub fn ep3out(&mut self) -> EP3OUT_W<'_>`[src]

Bit 6 - Interrupt status register bit for the EP3 OUT direction.

`pub fn ep3in(&mut self) -> EP3IN_W<'_>`[src]

Bit 7 - Interrupt status register bit for the EP3 IN direction.

`pub fn ep4out(&mut self) -> EP4OUT_W<'_>`[src]

Bit 8 - Interrupt status register bit for the EP4 OUT direction.

`pub fn ep4in(&mut self) -> EP4IN_W<'_>`[src]

Bit 9 - Interrupt status register bit for the EP4 IN direction.

`pub fn ep5out(&mut self) -> EP5OUT_W<'_>`[src]

Bit 10 - Interrupt status register bit for the EP5 OUT direction.

`pub fn ep5in(&mut self) -> EP5IN_W<'_>`[src]

Bit 11 - Interrupt status register bit for the EP5 IN direction.

`pub fn frame_int(&mut self) -> FRAME_INT_W<'_>`[src]

Bit 30 - Frame interrupt.

`pub fn dev_int(&mut self) -> DEV_INT_W<'_>`[src]

Bit 31 - Device status interrupt.

`impl W<u32, Reg<u32, _INTEN>>`[src]

`pub fn ep_int_en(&mut self) -> EP_INT_EN_W<'_>`[src]

Bits 0:11 - If this bit is set and the corresponding USB interrupt status bit is set, a HW interrupt is generated on the interrupt line.

`pub fn frame_int_en(&mut self) -> FRAME_INT_EN_W<'_>`[src]

Bit 30 - If this bit is set and the corresponding USB interrupt status bit is set, a HW interrupt is generated on the interrupt line.

`pub fn dev_int_en(&mut self) -> DEV_INT_EN_W<'_>`[src]

Bit 31 - If this bit is set and the corresponding USB interrupt status bit is set, a HW interrupt is generated on the interrupt line.

`impl W<u32, Reg<u32, _INTSETSTAT>>`[src]

`pub fn ep_set_int(&mut self) -> EP_SET_INT_W<'_>`[src]

Bits 0:11 - If software writes a one to one of these bits, the corresponding USB interrupt status bit is set.

`pub fn frame_set_int(&mut self) -> FRAME_SET_INT_W<'_>`[src]

Bit 30 - If software writes a one to one of these bits, the corresponding USB interrupt status bit is set.

`pub fn dev_set_int(&mut self) -> DEV_SET_INT_W<'_>`[src]

Bit 31 - If software writes a one to one of these bits, the corresponding USB interrupt status bit is set.

`impl W<u32, Reg<u32, _MODE>>`[src]

`pub fn crc_poly(&mut self) -> CRC_POLY_W<'_>`[src]

Bits 0:1 - CRC polynomial: 1X = CRC-32 polynomial 01 = CRC-16 polynomial 00 = CRC-CCITT polynomial

`pub fn bit_rvs_wr(&mut self) -> BIT_RVS_WR_W<'_>`[src]

Bit 2 - Data bit order: 1 = Bit order reverse for CRC_WR_DATA (per byte) 0 = No bit order reverse for CRC_WR_DATA (per byte)

`pub fn cmpl_wr(&mut self) -> CMPL_WR_W<'_>`[src]

Bit 3 - Data complement: 1 = 1's complement for CRC_WR_DATA 0 = No 1's complement for CRC_WR_DATA

`pub fn bit_rvs_sum(&mut self) -> BIT_RVS_SUM_W<'_>`[src]

Bit 4 - CRC sum bit order: 1 = Bit order reverse for CRC_SUM 0 = No bit order reverse for CRC_SUM

`pub fn cmpl_sum(&mut self) -> CMPL_SUM_W<'_>`[src]

Bit 5 - CRC sum complement: 1 = 1's complement for CRC_SUM 0 = No 1's complement for CRC_SUM

`impl W<u32, Reg<u32, _SEED>>`[src]

`pub fn crc_seed(&mut self) -> CRC_SEED_W<'_>`[src]

Bits 0:31 - A write access to this register will load CRC seed value to CRC_SUM register with selected bit order and 1's complement pre-processes. A write access to this register will overrule the CRC calculation in progresses.

`impl W<u32, Reg<u32, _WR_DATA>>`[src]

`pub fn crc_wr_data(&mut self) -> CRC_WR_DATA_W<'_>`[src]

Bits 0:31 - Data written to this register will be taken to perform CRC calculation with selected bit order and 1's complement pre-process. Any write size 8, 16 or 32-bit are allowed and accept back-to-back transactions.

`impl W<u32, Reg<u32, _CTRL>>`[src]

`pub fn controller_reset(&mut self) -> CONTROLLER_RESET_W<'_>`[src]

Bit 0 - Controller reset.

`pub fn fifo_reset(&mut self) -> FIFO_RESET_W<'_>`[src]

Bit 1 - Fifo reset.

`pub fn dma_reset(&mut self) -> DMA_RESET_W<'_>`[src]

Bit 2 - DMA reset.

`pub fn int_enable(&mut self) -> INT_ENABLE_W<'_>`[src]

Bit 4 - Global interrupt enable/disable bit.

`pub fn read_wait(&mut self) -> READ_WAIT_W<'_>`[src]

Bit 6 - Read/wait.

`pub fn send_irq_response(&mut self) -> SEND_IRQ_RESPONSE_W<'_>`[src]

Bit 7 - Send irq response.

`pub fn abort_read_data(&mut self) -> ABORT_READ_DATA_W<'_>`[src]

Bit 8 - Abort read data.

`pub fn send_ccsd(&mut self) -> SEND_CCSD_W<'_>`[src]

Bit 9 - Send ccsd.

`pub fn send_auto_stop_ccsd(&mut self) -> SEND_AUTO_STOP_CCSD_W<'_>`[src]

Bit 10 - Send auto stop ccsd.

`pub fn ceata_device_interrupt_status( &mut self ) -> CEATA_DEVICE_INTERRUPT_STATUS_W<'_>`[src]

Bit 11 - CEATA device interrupt status.

`pub fn card_voltage_a0(&mut self) -> CARD_VOLTAGE_A0_W<'_>`[src]

Bit 16 - Controls the state of the SD_VOLT0 pin.

`pub fn card_voltage_a1(&mut self) -> CARD_VOLTAGE_A1_W<'_>`[src]

Bit 17 - Controls the state of the SD_VOLT1 pin.

`pub fn card_voltage_a2(&mut self) -> CARD_VOLTAGE_A2_W<'_>`[src]

Bit 18 - Controls the state of the SD_VOLT2 pin.

`pub fn use_internal_dmac(&mut self) -> USE_INTERNAL_DMAC_W<'_>`[src]

Bit 25 - SD/MMC DMA use.

`impl W<u32, Reg<u32, _PWREN>>`[src]

`pub fn power_enable0(&mut self) -> POWER_ENABLE0_W<'_>`[src]

Bit 0 - Power on/off switch for card 0; once power is turned on, software should wait for regulator/switch ramp-up time before trying to initialize card 0.

`pub fn power_enable1(&mut self) -> POWER_ENABLE1_W<'_>`[src]

Bit 1 - Power on/off switch for card 1; once power is turned on, software should wait for regulator/switch ramp-up time before trying to initialize card 1.

`impl W<u32, Reg<u32, _CLKDIV>>`[src]

`pub fn clk_divider0(&mut self) -> CLK_DIVIDER0_W<'_>`[src]

Bits 0:7 - Clock divider-0 value.

`impl W<u32, Reg<u32, _CLKENA>>`[src]

`pub fn cclk0_enable(&mut self) -> CCLK0_ENABLE_W<'_>`[src]

Bit 0 - Clock-enable control for SD card 0 clock.

`pub fn cclk1_enable(&mut self) -> CCLK1_ENABLE_W<'_>`[src]

Bit 1 - Clock-enable control for SD card 1 clock.

`pub fn cclk0_low_power(&mut self) -> CCLK0_LOW_POWER_W<'_>`[src]

Bit 16 - Low-power control for SD card 0 clock.

`pub fn cclk1_low_power(&mut self) -> CCLK1_LOW_POWER_W<'_>`[src]

Bit 17 - Low-power control for SD card 1 clock.

`impl W<u32, Reg<u32, _TMOUT>>`[src]

`pub fn response_timeout(&mut self) -> RESPONSE_TIMEOUT_W<'_>`[src]

Bits 0:7 - Response time-out value.

`pub fn data_timeout(&mut self) -> DATA_TIMEOUT_W<'_>`[src]

Bits 8:31 - Value for card Data Read time-out; same value also used for Data Starvation by Host time-out.

`impl W<u32, Reg<u32, _CTYPE>>`[src]

`pub fn card0_width0(&mut self) -> CARD0_WIDTH0_W<'_>`[src]

Bit 0 - Indicates if card 0 is 1-bit or 4-bit: 0 - 1-bit mode 1 - 4-bit mode 1 and 4-bit modes only work when 8-bit mode in CARD0_WIDTH1 is not enabled (bit 16 in this register is set to 0).

`pub fn card1_width0(&mut self) -> CARD1_WIDTH0_W<'_>`[src]

Bit 1 - Indicates if card 1 is 1-bit or 4-bit: 0 - 1-bit mode 1 - 4-bit mode 1 and 4-bit modes only work when 8-bit mode in CARD1_WIDTH1 is not enabled (bit 16 in this register is set to 0).

`pub fn card0_width1(&mut self) -> CARD0_WIDTH1_W<'_>`[src]

Bit 16 - Indicates if card 0 is 8-bit: 0 - Non 8-bit mode 1 - 8-bit mode.

`pub fn card1_width1(&mut self) -> CARD1_WIDTH1_W<'_>`[src]

Bit 17 - Indicates if card 1 is 8-bit: 0 - Non 8-bit mode 1 - 8-bit mode.

`impl W<u32, Reg<u32, _BLKSIZ>>`[src]

`pub fn block_size(&mut self) -> BLOCK_SIZE_W<'_>`[src]

Bits 0:15 - Block size.

`impl W<u32, Reg<u32, _BYTCNT>>`[src]

`pub fn byte_count(&mut self) -> BYTE_COUNT_W<'_>`[src]

Bits 0:31 - Number of bytes to be transferred; should be integer multiple of Block Size for block transfers.

`impl W<u32, Reg<u32, _INTMASK>>`[src]

`pub fn cdet(&mut self) -> CDET_W<'_>`[src]

Bit 0 - Card detect.

`pub fn re(&mut self) -> RE_W<'_>`[src]

Bit 1 - Response error.

`pub fn cdone(&mut self) -> CDONE_W<'_>`[src]

Bit 2 - Command done.

`pub fn dto(&mut self) -> DTO_W<'_>`[src]

Bit 3 - Data transfer over.

`pub fn txdr(&mut self) -> TXDR_W<'_>`[src]

Bit 4 - Transmit FIFO data request.

`pub fn rxdr(&mut self) -> RXDR_W<'_>`[src]

Bit 5 - Receive FIFO data request.

`pub fn rcrc(&mut self) -> RCRC_W<'_>`[src]

Bit 6 - Response CRC error.

`pub fn dcrc(&mut self) -> DCRC_W<'_>`[src]

Bit 7 - Data CRC error.

`pub fn rto(&mut self) -> RTO_W<'_>`[src]

Bit 8 - Response time-out.

`pub fn drto(&mut self) -> DRTO_W<'_>`[src]

Bit 9 - Data read time-out.

`pub fn hto(&mut self) -> HTO_W<'_>`[src]

Bit 10 - Data starvation-by-host time-out (HTO).

`pub fn frun(&mut self) -> FRUN_W<'_>`[src]

Bit 11 - FIFO underrun/overrun error.

`pub fn hle(&mut self) -> HLE_W<'_>`[src]

Bit 12 - Hardware locked write error.

`pub fn sbe(&mut self) -> SBE_W<'_>`[src]

Bit 13 - Start-bit error.

`pub fn acd(&mut self) -> ACD_W<'_>`[src]

Bit 14 - Auto command done.

`pub fn ebe(&mut self) -> EBE_W<'_>`[src]

Bit 15 - End-bit error (read)/Write no CRC.

`pub fn sdio_int_mask(&mut self) -> SDIO_INT_MASK_W<'_>`[src]

Bit 16 - Mask SDIO interrupt.

`impl W<u32, Reg<u32, _CMDARG>>`[src]

`pub fn cmd_arg(&mut self) -> CMD_ARG_W<'_>`[src]

Bits 0:31 - Value indicates command argument to be passed to card.

`impl W<u32, Reg<u32, _CMD>>`[src]

`pub fn cmd_index(&mut self) -> CMD_INDEX_W<'_>`[src]

Bits 0:5 - Command index.

`pub fn response_expect(&mut self) -> RESPONSE_EXPECT_W<'_>`[src]

Bit 6 - Response expect.

`pub fn response_length(&mut self) -> RESPONSE_LENGTH_W<'_>`[src]

Bit 7 - Response length.

`pub fn check_response_crc(&mut self) -> CHECK_RESPONSE_CRC_W<'_>`[src]

Bit 8 - Check response CRC.

`pub fn data_expected(&mut self) -> DATA_EXPECTED_W<'_>`[src]

Bit 9 - Data expected.

`pub fn read_write(&mut self) -> READ_WRITE_W<'_>`[src]

Bit 10 - read/write.

`pub fn transfer_mode(&mut self) -> TRANSFER_MODE_W<'_>`[src]

Bit 11 - Transfer mode.

`pub fn send_auto_stop(&mut self) -> SEND_AUTO_STOP_W<'_>`[src]

Bit 12 - Send auto stop.

`pub fn wait_prvdata_complete(&mut self) -> WAIT_PRVDATA_COMPLETE_W<'_>`[src]

Bit 13 - Wait prvdata complete.

`pub fn stop_abort_cmd(&mut self) -> STOP_ABORT_CMD_W<'_>`[src]

Bit 14 - Stop abort command.

`pub fn send_initialization(&mut self) -> SEND_INITIALIZATION_W<'_>`[src]

Bit 15 - Send initialization.

`pub fn card_number(&mut self) -> CARD_NUMBER_W<'_>`[src]

Bits 16:20 - Specifies the card number of SDCARD for which the current Command is being executed

`pub fn update_clock_registers_only( &mut self ) -> UPDATE_CLOCK_REGISTERS_ONLY_W<'_>`[src]

Bit 21 - Update clock registers only.

`pub fn read_ceata_device(&mut self) -> READ_CEATA_DEVICE_W<'_>`[src]

Bit 22 - Read ceata device.

`pub fn ccs_expected(&mut self) -> CCS_EXPECTED_W<'_>`[src]

Bit 23 - CCS expected.

`pub fn enable_boot(&mut self) -> ENABLE_BOOT_W<'_>`[src]

Bit 24 - Enable Boot - this bit should be set only for mandatory boot mode.

`pub fn expect_boot_ack(&mut self) -> EXPECT_BOOT_ACK_W<'_>`[src]

Bit 25 - Expect Boot Acknowledge.

`pub fn disable_boot(&mut self) -> DISABLE_BOOT_W<'_>`[src]

Bit 26 - Disable Boot.

`pub fn boot_mode(&mut self) -> BOOT_MODE_W<'_>`[src]

Bit 27 - Boot Mode.

`pub fn volt_switch(&mut self) -> VOLT_SWITCH_W<'_>`[src]

Bit 28 - Voltage switch bit.

`pub fn use_hold_reg(&mut self) -> USE_HOLD_REG_W<'_>`[src]

Bit 29 - Use Hold Register.

`pub fn start_cmd(&mut self) -> START_CMD_W<'_>`[src]

Bit 31 - Start command.

`impl W<u32, Reg<u32, _RESP>>`[src]

`pub fn response(&mut self) -> RESPONSE_W<'_>`[src]

Bits 0:31 - Bits of response.

`impl W<u32, Reg<u32, _MINTSTS>>`[src]

`pub fn cdet(&mut self) -> CDET_W<'_>`[src]

Bit 0 - Card detect.

`pub fn re(&mut self) -> RE_W<'_>`[src]

Bit 1 - Response error.

`pub fn cdone(&mut self) -> CDONE_W<'_>`[src]

Bit 2 - Command done.

`pub fn dto(&mut self) -> DTO_W<'_>`[src]

Bit 3 - Data transfer over.

`pub fn txdr(&mut self) -> TXDR_W<'_>`[src]

Bit 4 - Transmit FIFO data request.

`pub fn rxdr(&mut self) -> RXDR_W<'_>`[src]

Bit 5 - Receive FIFO data request.

`pub fn rcrc(&mut self) -> RCRC_W<'_>`[src]

Bit 6 - Response CRC error.

`pub fn dcrc(&mut self) -> DCRC_W<'_>`[src]

Bit 7 - Data CRC error.

`pub fn rto(&mut self) -> RTO_W<'_>`[src]

Bit 8 - Response time-out.

`pub fn drto(&mut self) -> DRTO_W<'_>`[src]

Bit 9 - Data read time-out.

`pub fn hto(&mut self) -> HTO_W<'_>`[src]

Bit 10 - Data starvation-by-host time-out (HTO).

`pub fn frun(&mut self) -> FRUN_W<'_>`[src]

Bit 11 - FIFO underrun/overrun error.

`pub fn hle(&mut self) -> HLE_W<'_>`[src]

Bit 12 - Hardware locked write error.

`pub fn sbe(&mut self) -> SBE_W<'_>`[src]

Bit 13 - Start-bit error.

`pub fn acd(&mut self) -> ACD_W<'_>`[src]

Bit 14 - Auto command done.

`pub fn ebe(&mut self) -> EBE_W<'_>`[src]

Bit 15 - End-bit error (read)/write no CRC.

`pub fn sdio_interrupt(&mut self) -> SDIO_INTERRUPT_W<'_>`[src]

Bit 16 - Interrupt from SDIO card.

`impl W<u32, Reg<u32, _RINTSTS>>`[src]

`pub fn cdet(&mut self) -> CDET_W<'_>`[src]

Bit 0 - Card detect.

`pub fn re(&mut self) -> RE_W<'_>`[src]

Bit 1 - Response error.

`pub fn cdone(&mut self) -> CDONE_W<'_>`[src]

Bit 2 - Command done.

`pub fn dto(&mut self) -> DTO_W<'_>`[src]

Bit 3 - Data transfer over.

`pub fn txdr(&mut self) -> TXDR_W<'_>`[src]

Bit 4 - Transmit FIFO data request.

`pub fn rxdr(&mut self) -> RXDR_W<'_>`[src]

Bit 5 - Receive FIFO data request.

`pub fn rcrc(&mut self) -> RCRC_W<'_>`[src]

Bit 6 - Response CRC error.

`pub fn dcrc(&mut self) -> DCRC_W<'_>`[src]

Bit 7 - Data CRC error.

`pub fn rto_bar(&mut self) -> RTO_BAR_W<'_>`[src]

Bit 8 - Response time-out (RTO)/Boot Ack Received (BAR).

`pub fn drto_bds(&mut self) -> DRTO_BDS_W<'_>`[src]

Bit 9 - Data read time-out (DRTO)/Boot Data Start (BDS).

`pub fn hto(&mut self) -> HTO_W<'_>`[src]

Bit 10 - Data starvation-by-host time-out (HTO).

`pub fn frun(&mut self) -> FRUN_W<'_>`[src]

Bit 11 - FIFO underrun/overrun error.

`pub fn hle(&mut self) -> HLE_W<'_>`[src]

Bit 12 - Hardware locked write error.

`pub fn sbe(&mut self) -> SBE_W<'_>`[src]

Bit 13 - Start-bit error.

`pub fn acd(&mut self) -> ACD_W<'_>`[src]

Bit 14 - Auto command done.

`pub fn ebe(&mut self) -> EBE_W<'_>`[src]

Bit 15 - End-bit error (read)/write no CRC.

`pub fn sdio_interrupt(&mut self) -> SDIO_INTERRUPT_W<'_>`[src]

Bit 16 - Interrupt from SDIO card.

`impl W<u32, Reg<u32, _STATUS>>`[src]

`pub fn fifo_rx_watermark(&mut self) -> FIFO_RX_WATERMARK_W<'_>`[src]

Bit 0 - FIFO reached Receive watermark level; not qualified with data transfer.

`pub fn fifo_tx_watermark(&mut self) -> FIFO_TX_WATERMARK_W<'_>`[src]

Bit 1 - FIFO reached Transmit watermark level; not qualified with data transfer.

`pub fn fifo_empty(&mut self) -> FIFO_EMPTY_W<'_>`[src]

Bit 2 - FIFO is empty status.

`pub fn fifo_full(&mut self) -> FIFO_FULL_W<'_>`[src]

Bit 3 - FIFO is full status.

`pub fn cmdfsmstates(&mut self) -> CMDFSMSTATES_W<'_>`[src]

Bits 4:7 - Command FSM states: 0 - Idle 1 - Send init sequence 2 - Tx cmd start bit 3 - Tx cmd tx bit 4 - Tx cmd index + arg 5 - Tx cmd crc7 6 - Tx cmd end bit 7 - Rx resp start bit 8 - Rx resp IRQ response 9 - Rx resp tx bit 10 - Rx resp cmd idx 11 - Rx resp data 12 - Rx resp crc7 13 - Rx resp end bit 14 - Cmd path wait NCC 15 - Wait; CMD-to-response turnaround NOTE: The command FSM state is represented using 19 bits.

`pub fn data_3_status(&mut self) -> DATA_3_STATUS_W<'_>`[src]

Bit 8 - Raw selected card_data[3]; checks whether card is present 0 - card not present 1 - card present.

`pub fn data_busy(&mut self) -> DATA_BUSY_W<'_>`[src]

Bit 9 - Inverted version of raw selected card_data[0] 0 - card data not busy 1 - card data busy.

`pub fn data_state_mc_busy(&mut self) -> DATA_STATE_MC_BUSY_W<'_>`[src]

Bit 10 - Data transmit or receive state-machine is busy.

`pub fn response_index(&mut self) -> RESPONSE_INDEX_W<'_>`[src]

Bits 11:16 - Index of previous response, including any auto-stop sent by core.

`pub fn fifo_count(&mut self) -> FIFO_COUNT_W<'_>`[src]

Bits 17:29 - FIFO count - Number of filled locations in FIFO.

`pub fn dma_ack(&mut self) -> DMA_ACK_W<'_>`[src]

Bit 30 - DMA acknowledge signal state.

`pub fn dma_req(&mut self) -> DMA_REQ_W<'_>`[src]

Bit 31 - DMA request signal state.

`impl W<u32, Reg<u32, _FIFOTH>>`[src]

`pub fn tx_wmark(&mut self) -> TX_WMARK_W<'_>`[src]

Bits 0:11 - FIFO threshold watermark level when transmitting data to card.

`pub fn rx_wmark(&mut self) -> RX_WMARK_W<'_>`[src]

Bits 16:27 - FIFO threshold watermark level when receiving data to card.

`pub fn dma_mts(&mut self) -> DMA_MTS_W<'_>`[src]

Bits 28:30 - Burst size of multiple transaction; should be programmed same as DW-DMA controller multiple-transaction-size SRC/DEST_MSIZE.

`impl W<u32, Reg<u32, _CDETECT>>`[src]

`pub fn card0_detect(&mut self) -> CARD0_DETECT_W<'_>`[src]

Bit 0 - Card 0 detect

`pub fn card1_detect(&mut self) -> CARD1_DETECT_W<'_>`[src]

Bit 1 - Card 1 detect

`impl W<u32, Reg<u32, _WRTPRT>>`[src]

`pub fn write_protect(&mut self) -> WRITE_PROTECT_W<'_>`[src]

Bit 0 - Write protect.

`impl W<u32, Reg<u32, _TCBCNT>>`[src]

`pub fn trans_card_byte_count(&mut self) -> TRANS_CARD_BYTE_COUNT_W<'_>`[src]

Bits 0:31 - Number of bytes transferred by CIU unit to card.

`impl W<u32, Reg<u32, _TBBCNT>>`[src]

`pub fn trans_fifo_byte_count(&mut self) -> TRANS_FIFO_BYTE_COUNT_W<'_>`[src]

Bits 0:31 - Number of bytes transferred between Host/DMA memory and BIU FIFO.

`impl W<u32, Reg<u32, _DEBNCE>>`[src]

`pub fn debounce_count(&mut self) -> DEBOUNCE_COUNT_W<'_>`[src]

Bits 0:23 - Number of host clocks (SD_CLK) used by debounce filter logic for card detect; typical debounce time is 5-25 ms.

`impl W<u32, Reg<u32, _RST_N>>`[src]

`pub fn card_reset(&mut self) -> CARD_RESET_W<'_>`[src]

Bit 0 - Hardware reset.

`impl W<u32, Reg<u32, _BMOD>>`[src]

`pub fn swr(&mut self) -> SWR_W<'_>`[src]

Bit 0 - Software Reset.

`pub fn fb(&mut self) -> FB_W<'_>`[src]

Bit 1 - Fixed Burst.

`pub fn dsl(&mut self) -> DSL_W<'_>`[src]

Bits 2:6 - Descriptor Skip Length.

`pub fn de(&mut self) -> DE_W<'_>`[src]

Bit 7 - SD/MMC DMA Enable.

`pub fn pbl(&mut self) -> PBL_W<'_>`[src]

Bits 8:10 - Programmable Burst Length.

`impl W<u32, Reg<u32, _PLDMND>>`[src]

`pub fn pd(&mut self) -> PD_W<'_>`[src]

Bits 0:31 - Poll Demand.

`impl W<u32, Reg<u32, _DBADDR>>`[src]

`pub fn sdl(&mut self) -> SDL_W<'_>`[src]

Bits 0:31 - Start of Descriptor List.

`impl W<u32, Reg<u32, _IDSTS>>`[src]

`pub fn ti(&mut self) -> TI_W<'_>`[src]

Bit 0 - Transmit Interrupt.

`pub fn ri(&mut self) -> RI_W<'_>`[src]

Bit 1 - Receive Interrupt.

`pub fn fbe(&mut self) -> FBE_W<'_>`[src]

Bit 2 - Fatal Bus Error Interrupt.

`pub fn du(&mut self) -> DU_W<'_>`[src]

Bit 4 - Descriptor Unavailable Interrupt.

`pub fn ces(&mut self) -> CES_W<'_>`[src]

Bit 5 - Card Error Summary.

`pub fn nis(&mut self) -> NIS_W<'_>`[src]

Bit 8 - Normal Interrupt Summary.

`pub fn ais(&mut self) -> AIS_W<'_>`[src]

Bit 9 - Abnormal Interrupt Summary.

`pub fn eb(&mut self) -> EB_W<'_>`[src]

Bits 10:12 - Error Bits.

`pub fn fsm(&mut self) -> FSM_W<'_>`[src]

Bits 13:16 - DMAC state machine present state.

`impl W<u32, Reg<u32, _IDINTEN>>`[src]

`pub fn ti(&mut self) -> TI_W<'_>`[src]

Bit 0 - Transmit Interrupt Enable.

`pub fn ri(&mut self) -> RI_W<'_>`[src]

Bit 1 - Receive Interrupt Enable.

`pub fn fbe(&mut self) -> FBE_W<'_>`[src]

Bit 2 - Fatal Bus Error Enable.

`pub fn du(&mut self) -> DU_W<'_>`[src]

Bit 4 - Descriptor Unavailable Interrupt.

`pub fn ces(&mut self) -> CES_W<'_>`[src]

Bit 5 - Card Error summary Interrupt Enable.

`pub fn nis(&mut self) -> NIS_W<'_>`[src]

Bit 8 - Normal Interrupt Summary Enable.

`pub fn ais(&mut self) -> AIS_W<'_>`[src]

Bit 9 - Abnormal Interrupt Summary Enable.

`impl W<u32, Reg<u32, _DSCADDR>>`[src]

`pub fn hda(&mut self) -> HDA_W<'_>`[src]

Bits 0:31 - Host Descriptor Address Pointer.

`impl W<u32, Reg<u32, _BUFADDR>>`[src]

`pub fn hba(&mut self) -> HBA_W<'_>`[src]

Bits 0:31 - Host Buffer Address Pointer.

`impl W<u32, Reg<u32, _CARDTHRCTL>>`[src]

`pub fn cardrdthren(&mut self) -> CARDRDTHREN_W<'_>`[src]

Bit 0 - Card Read Threshold Enable.

`pub fn bsyclrinten(&mut self) -> BSYCLRINTEN_W<'_>`[src]

Bit 1 - Busy Clear Interrupt Enable.

`pub fn cardthreshold(&mut self) -> CARDTHRESHOLD_W<'_>`[src]

Bits 16:23 - Card Threshold size.

`impl W<u32, Reg<u32, _BACKENDPWR>>`[src]

`pub fn backendpwr(&mut self) -> BACKENDPWR_W<'_>`[src]

Bit 0 - Back-end Power control for card application.

`impl W<u32, Reg<u32, _FIFO>>`[src]

`pub fn data(&mut self) -> DATA_W<'_>`[src]

Bits 0:31 - SDIF FIFO.

`impl W<u32, Reg<u32, _CSW>>`[src]

`pub fn resynch_req(&mut self) -> RESYNCH_REQ_W<'_>`[src]

Bit 0 - Debugger will set this bit to 1 to request a resynchronrisation

`pub fn req_pending(&mut self) -> REQ_PENDING_W<'_>`[src]

Bit 1 - Request is pending from debugger (i.e unread value in REQUEST)

`pub fn dbg_or_err(&mut self) -> DBG_OR_ERR_W<'_>`[src]

Bit 2 - Debugger overrun error (previous REQUEST overwritten before being picked up by ROM)

`pub fn ahb_or_err(&mut self) -> AHB_OR_ERR_W<'_>`[src]

Bit 3 - AHB overrun Error (Return value overwritten by ROM)

`pub fn soft_reset(&mut self) -> SOFT_RESET_W<'_>`[src]

Bit 4 - Soft Reset for DM (write-only from AHB, not readable and selfclearing). A write to this bit will cause a soft reset for DM.

`pub fn chip_reset_req(&mut self) -> CHIP_RESET_REQ_W<'_>`[src]

Bit 5 - Write only bit. Once written will cause the chip to reset (note that the DM is not reset by this reset as it is only resettable by a SOFT reset or a POR/BOD event)

`impl W<u32, Reg<u32, _REQUEST>>`[src]

`pub fn req(&mut self) -> REQ_W<'_>`[src]

Bits 0:31 - Request Value

`impl W<u32, Reg<u32, _RETURN>>`[src]

`pub fn ret(&mut self) -> RET_W<'_>`[src]

Bits 0:31 - The Return value from ROM.

`impl W<u32, Reg<u32, _CTRL>>`[src]

`pub fn adcen(&mut self) -> ADCEN_W<'_>`[src]

Bit 0 - ADC Enable

`pub fn rst(&mut self) -> RST_W<'_>`[src]

Bit 1 - Software Reset

`pub fn dozen(&mut self) -> DOZEN_W<'_>`[src]

Bit 2 - Doze Enable

`pub fn cal_req(&mut self) -> CAL_REQ_W<'_>`[src]

Bit 3 - Auto-Calibration Request

`pub fn calofs(&mut self) -> CALOFS_W<'_>`[src]

Bit 4 - Configure for offset calibration function

`pub fn rstfifo0(&mut self) -> RSTFIFO0_W<'_>`[src]

Bit 8 - Reset FIFO 0

`pub fn rstfifo1(&mut self) -> RSTFIFO1_W<'_>`[src]

Bit 9 - Reset FIFO 1

`pub fn cal_avgs(&mut self) -> CAL_AVGS_W<'_>`[src]

Bits 16:18 - Auto-Calibration Averages

`impl W<u32, Reg<u32, _STAT>>`[src]

`pub fn fof0(&mut self) -> FOF0_W<'_>`[src]

Bit 1 - Result FIFO 0 Overflow Flag

`pub fn fof1(&mut self) -> FOF1_W<'_>`[src]

Bit 3 - Result FIFO1 Overflow Flag

`pub fn texc_int(&mut self) -> TEXC_INT_W<'_>`[src]

Bit 8 - Interrupt Flag For High Priority Trigger Exception

`pub fn tcomp_int(&mut self) -> TCOMP_INT_W<'_>`[src]

Bit 9 - Interrupt Flag For Trigger Completion

`impl W<u32, Reg<u32, _IE>>`[src]

`pub fn fwmie0(&mut self) -> FWMIE0_W<'_>`[src]

Bit 0 - FIFO 0 Watermark Interrupt Enable

`pub fn fofie0(&mut self) -> FOFIE0_W<'_>`[src]

Bit 1 - Result FIFO 0 Overflow Interrupt Enable

`pub fn fwmie1(&mut self) -> FWMIE1_W<'_>`[src]

Bit 2 - FIFO1 Watermark Interrupt Enable

`pub fn fofie1(&mut self) -> FOFIE1_W<'_>`[src]

Bit 3 - Result FIFO1 Overflow Interrupt Enable

`pub fn texc_ie(&mut self) -> TEXC_IE_W<'_>`[src]

Bit 8 - Trigger Exception Interrupt Enable

`pub fn tcomp_ie(&mut self) -> TCOMP_IE_W<'_>`[src]

Bits 16:31 - Trigger Completion Interrupt Enable

`impl W<u32, Reg<u32, _DE>>`[src]

`pub fn fwmde0(&mut self) -> FWMDE0_W<'_>`[src]

Bit 0 - FIFO 0 Watermark DMA Enable

`pub fn fwmde1(&mut self) -> FWMDE1_W<'_>`[src]

Bit 1 - FIFO1 Watermark DMA Enable

`impl W<u32, Reg<u32, _CFG>>`[src]

`pub fn tprictrl(&mut self) -> TPRICTRL_W<'_>`[src]

Bits 0:1 - ADC trigger priority control

`pub fn pwrsel(&mut self) -> PWRSEL_W<'_>`[src]

Bits 4:5 - Power Configuration Select

`pub fn refsel(&mut self) -> REFSEL_W<'_>`[src]

Bits 6:7 - Voltage Reference Selection

`pub fn tres(&mut self) -> TRES_W<'_>`[src]

Bit 8 - Trigger Resume Enable

`pub fn tcmdres(&mut self) -> TCMDRES_W<'_>`[src]

Bit 9 - Trigger Command Resume

`pub fn hpt_exdi(&mut self) -> HPT_EXDI_W<'_>`[src]

Bit 10 - High Priority Trigger Exception Disable

`pub fn pudly(&mut self) -> PUDLY_W<'_>`[src]

Bits 16:23 - Power Up Delay

`pub fn pwren(&mut self) -> PWREN_W<'_>`[src]

Bit 28 - ADC Analog Pre-Enable

`impl W<u32, Reg<u32, _PAUSE>>`[src]

`pub fn pausedly(&mut self) -> PAUSEDLY_W<'_>`[src]

Bits 0:8 - Pause Delay

`pub fn pauseen(&mut self) -> PAUSEEN_W<'_>`[src]

Bit 31 - PAUSE Option Enable

`impl W<u32, Reg<u32, _SWTRIG>>`[src]

`pub fn swt0(&mut self) -> SWT0_W<'_>`[src]

Bit 0 - Software trigger 0 event

`pub fn swt1(&mut self) -> SWT1_W<'_>`[src]

Bit 1 - Software trigger 1 event

`pub fn swt2(&mut self) -> SWT2_W<'_>`[src]

Bit 2 - Software trigger 2 event

`pub fn swt3(&mut self) -> SWT3_W<'_>`[src]

Bit 3 - Software trigger 3 event

`pub fn swt4(&mut self) -> SWT4_W<'_>`[src]

Bit 4 - Software trigger 4 event

`pub fn swt5(&mut self) -> SWT5_W<'_>`[src]

Bit 5 - Software trigger 5 event

`pub fn swt6(&mut self) -> SWT6_W<'_>`[src]

Bit 6 - Software trigger 6 event

`pub fn swt7(&mut self) -> SWT7_W<'_>`[src]

Bit 7 - Software trigger 7 event

`pub fn swt8(&mut self) -> SWT8_W<'_>`[src]

Bit 8 - Software trigger 8 event

`pub fn swt9(&mut self) -> SWT9_W<'_>`[src]

Bit 9 - Software trigger 9 event

`pub fn swt10(&mut self) -> SWT10_W<'_>`[src]

Bit 10 - Software trigger 10 event

`pub fn swt11(&mut self) -> SWT11_W<'_>`[src]

Bit 11 - Software trigger 11 event

`pub fn swt12(&mut self) -> SWT12_W<'_>`[src]

Bit 12 - Software trigger 12 event

`pub fn swt13(&mut self) -> SWT13_W<'_>`[src]

Bit 13 - Software trigger 13 event

`pub fn swt14(&mut self) -> SWT14_W<'_>`[src]

Bit 14 - Software trigger 14 event

`pub fn swt15(&mut self) -> SWT15_W<'_>`[src]

Bit 15 - Software trigger 15 event

`impl W<u32, Reg<u32, _TSTAT>>`[src]

`pub fn texc_num(&mut self) -> TEXC_NUM_W<'_>`[src]

Bits 0:15 - Trigger Exception Number

`pub fn tcomp_flag(&mut self) -> TCOMP_FLAG_W<'_>`[src]

Bits 16:31 - Trigger Completion Flag

`impl W<u32, Reg<u32, _OFSTRIM>>`[src]

`pub fn ofstrim_a(&mut self) -> OFSTRIM_A_W<'_>`[src]

Bits 0:4 - Trim for offset

`pub fn ofstrim_b(&mut self) -> OFSTRIM_B_W<'_>`[src]

Bits 16:20 - Trim for offset

`impl W<u32, Reg<u32, _TCTRL>>`[src]

`pub fn hten(&mut self) -> HTEN_W<'_>`[src]

Bit 0 - Trigger enable

`pub fn fifo_sel_a(&mut self) -> FIFO_SEL_A_W<'_>`[src]

Bit 1 - SAR Result Destination For Channel A

`pub fn fifo_sel_b(&mut self) -> FIFO_SEL_B_W<'_>`[src]

Bit 2 - SAR Result Destination For Channel B

`pub fn tpri(&mut self) -> TPRI_W<'_>`[src]

Bits 8:11 - Trigger priority setting

`pub fn rsync(&mut self) -> RSYNC_W<'_>`[src]

Bit 15 - Trigger Resync

`pub fn tdly(&mut self) -> TDLY_W<'_>`[src]

Bits 16:19 - Trigger delay select

`pub fn tcmd(&mut self) -> TCMD_W<'_>`[src]

Bits 24:27 - Trigger command select

`impl W<u32, Reg<u32, _FCTRL>>`[src]

`pub fn fwmark(&mut self) -> FWMARK_W<'_>`[src]

Bits 16:19 - Watermark level selection

`impl W<u32, Reg<u32, _GCR>>`[src]

`pub fn gcalr(&mut self) -> GCALR_W<'_>`[src]

Bits 0:15 - Gain Calculation Result

`pub fn rdy(&mut self) -> RDY_W<'_>`[src]

Bit 24 - Gain Calculation Ready

`impl W<u32, Reg<u32, _CMDL1>>`[src]

`pub fn adch(&mut self) -> ADCH_W<'_>`[src]

Bits 0:4 - Input channel select

`pub fn ctype(&mut self) -> CTYPE_W<'_>`[src]

Bits 5:6 - Conversion Type

`pub fn mode(&mut self) -> MODE_W<'_>`[src]

Bit 7 - Select resolution of conversions

`impl W<u32, Reg<u32, _CMDH1>>`[src]

`pub fn cmpen(&mut self) -> CMPEN_W<'_>`[src]

Bits 0:1 - Compare Function Enable

`pub fn wait_trig(&mut self) -> WAIT_TRIG_W<'_>`[src]

Bit 2 - Wait for trigger assertion before execution.

`pub fn lwi(&mut self) -> LWI_W<'_>`[src]

Bit 7 - Loop with Increment

`pub fn sts(&mut self) -> STS_W<'_>`[src]

Bits 8:10 - Sample Time Select

`pub fn avgs(&mut self) -> AVGS_W<'_>`[src]

Bits 12:14 - Hardware Average Select

`pub fn loop_(&mut self) -> LOOP_W<'_>`[src]

Bits 16:19 - Loop Count Select

`pub fn next(&mut self) -> NEXT_W<'_>`[src]

Bits 24:27 - Next Command Select

`impl W<u32, Reg<u32, _CMDL2>>`[src]

`pub fn adch(&mut self) -> ADCH_W<'_>`[src]

Bits 0:4 - Input channel select

`pub fn ctype(&mut self) -> CTYPE_W<'_>`[src]

Bits 5:6 - Conversion Type

`pub fn mode(&mut self) -> MODE_W<'_>`[src]

Bit 7 - Select resolution of conversions

`impl W<u32, Reg<u32, _CMDH2>>`[src]

`pub fn cmpen(&mut self) -> CMPEN_W<'_>`[src]

Bits 0:1 - Compare Function Enable

`pub fn wait_trig(&mut self) -> WAIT_TRIG_W<'_>`[src]

Bit 2 - Wait for trigger assertion before execution.

`pub fn lwi(&mut self) -> LWI_W<'_>`[src]

Bit 7 - Loop with Increment

`pub fn sts(&mut self) -> STS_W<'_>`[src]

Bits 8:10 - Sample Time Select

`pub fn avgs(&mut self) -> AVGS_W<'_>`[src]

Bits 12:14 - Hardware Average Select

`pub fn loop_(&mut self) -> LOOP_W<'_>`[src]

Bits 16:19 - Loop Count Select

`pub fn next(&mut self) -> NEXT_W<'_>`[src]

Bits 24:27 - Next Command Select

`impl W<u32, Reg<u32, _CMDL3>>`[src]

`pub fn adch(&mut self) -> ADCH_W<'_>`[src]

Bits 0:4 - Input channel select

`pub fn ctype(&mut self) -> CTYPE_W<'_>`[src]

Bits 5:6 - Conversion Type

`pub fn mode(&mut self) -> MODE_W<'_>`[src]

Bit 7 - Select resolution of conversions

`impl W<u32, Reg<u32, _CMDH3>>`[src]

`pub fn cmpen(&mut self) -> CMPEN_W<'_>`[src]

Bits 0:1 - Compare Function Enable

`pub fn wait_trig(&mut self) -> WAIT_TRIG_W<'_>`[src]

Bit 2 - Wait for trigger assertion before execution.

`pub fn lwi(&mut self) -> LWI_W<'_>`[src]

Bit 7 - Loop with Increment

`pub fn sts(&mut self) -> STS_W<'_>`[src]

Bits 8:10 - Sample Time Select

`pub fn avgs(&mut self) -> AVGS_W<'_>`[src]

Bits 12:14 - Hardware Average Select

`pub fn loop_(&mut self) -> LOOP_W<'_>`[src]

Bits 16:19 - Loop Count Select

`pub fn next(&mut self) -> NEXT_W<'_>`[src]

Bits 24:27 - Next Command Select

`impl W<u32, Reg<u32, _CMDL4>>`[src]

`pub fn adch(&mut self) -> ADCH_W<'_>`[src]

Bits 0:4 - Input channel select

`pub fn ctype(&mut self) -> CTYPE_W<'_>`[src]

Bits 5:6 - Conversion Type

`pub fn mode(&mut self) -> MODE_W<'_>`[src]

Bit 7 - Select resolution of conversions

`impl W<u32, Reg<u32, _CMDH4>>`[src]

`pub fn cmpen(&mut self) -> CMPEN_W<'_>`[src]

Bits 0:1 - Compare Function Enable

`pub fn wait_trig(&mut self) -> WAIT_TRIG_W<'_>`[src]

Bit 2 - Wait for trigger assertion before execution.

`pub fn lwi(&mut self) -> LWI_W<'_>`[src]

Bit 7 - Loop with Increment

`pub fn sts(&mut self) -> STS_W<'_>`[src]

Bits 8:10 - Sample Time Select

`pub fn avgs(&mut self) -> AVGS_W<'_>`[src]

Bits 12:14 - Hardware Average Select

`pub fn loop_(&mut self) -> LOOP_W<'_>`[src]

Bits 16:19 - Loop Count Select

`pub fn next(&mut self) -> NEXT_W<'_>`[src]

Bits 24:27 - Next Command Select

`impl W<u32, Reg<u32, _CMDL5>>`[src]

`pub fn adch(&mut self) -> ADCH_W<'_>`[src]

Bits 0:4 - Input channel select

`pub fn ctype(&mut self) -> CTYPE_W<'_>`[src]

Bits 5:6 - Conversion Type

`pub fn mode(&mut self) -> MODE_W<'_>`[src]

Bit 7 - Select resolution of conversions

`impl W<u32, Reg<u32, _CMDH5>>`[src]

`pub fn wait_trig(&mut self) -> WAIT_TRIG_W<'_>`[src]

Bit 2 - Wait for trigger assertion before execution.

`pub fn lwi(&mut self) -> LWI_W<'_>`[src]

Bit 7 - Loop with Increment

`pub fn sts(&mut self) -> STS_W<'_>`[src]

Bits 8:10 - Sample Time Select

`pub fn avgs(&mut self) -> AVGS_W<'_>`[src]

Bits 12:14 - Hardware Average Select

`pub fn loop_(&mut self) -> LOOP_W<'_>`[src]

Bits 16:19 - Loop Count Select

`pub fn next(&mut self) -> NEXT_W<'_>`[src]

Bits 24:27 - Next Command Select

`impl W<u32, Reg<u32, _CMDL6>>`[src]

`pub fn adch(&mut self) -> ADCH_W<'_>`[src]

Bits 0:4 - Input channel select

`pub fn ctype(&mut self) -> CTYPE_W<'_>`[src]

Bits 5:6 - Conversion Type

`pub fn mode(&mut self) -> MODE_W<'_>`[src]

Bit 7 - Select resolution of conversions

`impl W<u32, Reg<u32, _CMDH6>>`[src]

`pub fn wait_trig(&mut self) -> WAIT_TRIG_W<'_>`[src]

Bit 2 - Wait for trigger assertion before execution.

`pub fn lwi(&mut self) -> LWI_W<'_>`[src]

Bit 7 - Loop with Increment

`pub fn sts(&mut self) -> STS_W<'_>`[src]

Bits 8:10 - Sample Time Select

`pub fn avgs(&mut self) -> AVGS_W<'_>`[src]

Bits 12:14 - Hardware Average Select

`pub fn loop_(&mut self) -> LOOP_W<'_>`[src]

Bits 16:19 - Loop Count Select

`pub fn next(&mut self) -> NEXT_W<'_>`[src]

Bits 24:27 - Next Command Select

`impl W<u32, Reg<u32, _CMDL7>>`[src]

`pub fn adch(&mut self) -> ADCH_W<'_>`[src]

Bits 0:4 - Input channel select

`pub fn ctype(&mut self) -> CTYPE_W<'_>`[src]

Bits 5:6 - Conversion Type

`pub fn mode(&mut self) -> MODE_W<'_>`[src]

Bit 7 - Select resolution of conversions

`impl W<u32, Reg<u32, _CMDH7>>`[src]

`pub fn wait_trig(&mut self) -> WAIT_TRIG_W<'_>`[src]

Bit 2 - Wait for trigger assertion before execution.

`pub fn lwi(&mut self) -> LWI_W<'_>`[src]

Bit 7 - Loop with Increment

`pub fn sts(&mut self) -> STS_W<'_>`[src]

Bits 8:10 - Sample Time Select

`pub fn avgs(&mut self) -> AVGS_W<'_>`[src]

Bits 12:14 - Hardware Average Select

`pub fn loop_(&mut self) -> LOOP_W<'_>`[src]

Bits 16:19 - Loop Count Select

`pub fn next(&mut self) -> NEXT_W<'_>`[src]

Bits 24:27 - Next Command Select

`impl W<u32, Reg<u32, _CMDL8>>`[src]

`pub fn adch(&mut self) -> ADCH_W<'_>`[src]

Bits 0:4 - Input channel select

`pub fn ctype(&mut self) -> CTYPE_W<'_>`[src]

Bits 5:6 - Conversion Type

`pub fn mode(&mut self) -> MODE_W<'_>`[src]

Bit 7 - Select resolution of conversions

`impl W<u32, Reg<u32, _CMDH8>>`[src]

`pub fn wait_trig(&mut self) -> WAIT_TRIG_W<'_>`[src]

Bit 2 - Wait for trigger assertion before execution.

`pub fn lwi(&mut self) -> LWI_W<'_>`[src]

Bit 7 - Loop with Increment

`pub fn sts(&mut self) -> STS_W<'_>`[src]

Bits 8:10 - Sample Time Select

`pub fn avgs(&mut self) -> AVGS_W<'_>`[src]

Bits 12:14 - Hardware Average Select

`pub fn loop_(&mut self) -> LOOP_W<'_>`[src]

Bits 16:19 - Loop Count Select

`pub fn next(&mut self) -> NEXT_W<'_>`[src]

Bits 24:27 - Next Command Select

`impl W<u32, Reg<u32, _CMDL9>>`[src]

`pub fn adch(&mut self) -> ADCH_W<'_>`[src]

Bits 0:4 - Input channel select

`pub fn ctype(&mut self) -> CTYPE_W<'_>`[src]

Bits 5:6 - Conversion Type

`pub fn mode(&mut self) -> MODE_W<'_>`[src]

Bit 7 - Select resolution of conversions

`impl W<u32, Reg<u32, _CMDH9>>`[src]

`pub fn wait_trig(&mut self) -> WAIT_TRIG_W<'_>`[src]

Bit 2 - Wait for trigger assertion before execution.

`pub fn lwi(&mut self) -> LWI_W<'_>`[src]

Bit 7 - Loop with Increment

`pub fn sts(&mut self) -> STS_W<'_>`[src]

Bits 8:10 - Sample Time Select

`pub fn avgs(&mut self) -> AVGS_W<'_>`[src]

Bits 12:14 - Hardware Average Select

`pub fn loop_(&mut self) -> LOOP_W<'_>`[src]

Bits 16:19 - Loop Count Select

`pub fn next(&mut self) -> NEXT_W<'_>`[src]

Bits 24:27 - Next Command Select

`impl W<u32, Reg<u32, _CMDL10>>`[src]

`pub fn adch(&mut self) -> ADCH_W<'_>`[src]

Bits 0:4 - Input channel select

`pub fn ctype(&mut self) -> CTYPE_W<'_>`[src]

Bits 5:6 - Conversion Type

`pub fn mode(&mut self) -> MODE_W<'_>`[src]

Bit 7 - Select resolution of conversions

`impl W<u32, Reg<u32, _CMDH10>>`[src]

`pub fn wait_trig(&mut self) -> WAIT_TRIG_W<'_>`[src]

Bit 2 - Wait for trigger assertion before execution.

`pub fn lwi(&mut self) -> LWI_W<'_>`[src]

Bit 7 - Loop with Increment

`pub fn sts(&mut self) -> STS_W<'_>`[src]

Bits 8:10 - Sample Time Select

`pub fn avgs(&mut self) -> AVGS_W<'_>`[src]

Bits 12:14 - Hardware Average Select

`pub fn loop_(&mut self) -> LOOP_W<'_>`[src]

Bits 16:19 - Loop Count Select

`pub fn next(&mut self) -> NEXT_W<'_>`[src]

Bits 24:27 - Next Command Select

`impl W<u32, Reg<u32, _CMDL11>>`[src]

`pub fn adch(&mut self) -> ADCH_W<'_>`[src]

Bits 0:4 - Input channel select

`pub fn ctype(&mut self) -> CTYPE_W<'_>`[src]

Bits 5:6 - Conversion Type

`pub fn mode(&mut self) -> MODE_W<'_>`[src]

Bit 7 - Select resolution of conversions

`impl W<u32, Reg<u32, _CMDH11>>`[src]

`pub fn wait_trig(&mut self) -> WAIT_TRIG_W<'_>`[src]

Bit 2 - Wait for trigger assertion before execution.

`pub fn lwi(&mut self) -> LWI_W<'_>`[src]

Bit 7 - Loop with Increment

`pub fn sts(&mut self) -> STS_W<'_>`[src]

Bits 8:10 - Sample Time Select

`pub fn avgs(&mut self) -> AVGS_W<'_>`[src]

Bits 12:14 - Hardware Average Select

`pub fn loop_(&mut self) -> LOOP_W<'_>`[src]

Bits 16:19 - Loop Count Select

`pub fn next(&mut self) -> NEXT_W<'_>`[src]

Bits 24:27 - Next Command Select

`impl W<u32, Reg<u32, _CMDL12>>`[src]

`pub fn adch(&mut self) -> ADCH_W<'_>`[src]

Bits 0:4 - Input channel select

`pub fn ctype(&mut self) -> CTYPE_W<'_>`[src]

Bits 5:6 - Conversion Type

`pub fn mode(&mut self) -> MODE_W<'_>`[src]

Bit 7 - Select resolution of conversions

`impl W<u32, Reg<u32, _CMDH12>>`[src]

`pub fn wait_trig(&mut self) -> WAIT_TRIG_W<'_>`[src]

Bit 2 - Wait for trigger assertion before execution.

`pub fn lwi(&mut self) -> LWI_W<'_>`[src]

Bit 7 - Loop with Increment

`pub fn sts(&mut self) -> STS_W<'_>`[src]

Bits 8:10 - Sample Time Select

`pub fn avgs(&mut self) -> AVGS_W<'_>`[src]

Bits 12:14 - Hardware Average Select

`pub fn loop_(&mut self) -> LOOP_W<'_>`[src]

Bits 16:19 - Loop Count Select

`pub fn next(&mut self) -> NEXT_W<'_>`[src]

Bits 24:27 - Next Command Select

`impl W<u32, Reg<u32, _CMDL13>>`[src]

`pub fn adch(&mut self) -> ADCH_W<'_>`[src]

Bits 0:4 - Input channel select

`pub fn ctype(&mut self) -> CTYPE_W<'_>`[src]

Bits 5:6 - Conversion Type

`pub fn mode(&mut self) -> MODE_W<'_>`[src]

Bit 7 - Select resolution of conversions

`impl W<u32, Reg<u32, _CMDH13>>`[src]

`pub fn wait_trig(&mut self) -> WAIT_TRIG_W<'_>`[src]

Bit 2 - Wait for trigger assertion before execution.

`pub fn lwi(&mut self) -> LWI_W<'_>`[src]

Bit 7 - Loop with Increment

`pub fn sts(&mut self) -> STS_W<'_>`[src]

Bits 8:10 - Sample Time Select

`pub fn avgs(&mut self) -> AVGS_W<'_>`[src]

Bits 12:14 - Hardware Average Select

`pub fn loop_(&mut self) -> LOOP_W<'_>`[src]

Bits 16:19 - Loop Count Select

`pub fn next(&mut self) -> NEXT_W<'_>`[src]

Bits 24:27 - Next Command Select

`impl W<u32, Reg<u32, _CMDL14>>`[src]

`pub fn adch(&mut self) -> ADCH_W<'_>`[src]

Bits 0:4 - Input channel select

`pub fn ctype(&mut self) -> CTYPE_W<'_>`[src]

Bits 5:6 - Conversion Type

`pub fn mode(&mut self) -> MODE_W<'_>`[src]

Bit 7 - Select resolution of conversions

`impl W<u32, Reg<u32, _CMDH14>>`[src]

`pub fn wait_trig(&mut self) -> WAIT_TRIG_W<'_>`[src]

Bit 2 - Wait for trigger assertion before execution.

`pub fn lwi(&mut self) -> LWI_W<'_>`[src]

Bit 7 - Loop with Increment

`pub fn sts(&mut self) -> STS_W<'_>`[src]

Bits 8:10 - Sample Time Select

`pub fn avgs(&mut self) -> AVGS_W<'_>`[src]

Bits 12:14 - Hardware Average Select

`pub fn loop_(&mut self) -> LOOP_W<'_>`[src]

Bits 16:19 - Loop Count Select

`pub fn next(&mut self) -> NEXT_W<'_>`[src]

Bits 24:27 - Next Command Select

`impl W<u32, Reg<u32, _CMDL15>>`[src]

`pub fn adch(&mut self) -> ADCH_W<'_>`[src]

Bits 0:4 - Input channel select

`pub fn ctype(&mut self) -> CTYPE_W<'_>`[src]

Bits 5:6 - Conversion Type

`pub fn mode(&mut self) -> MODE_W<'_>`[src]

Bit 7 - Select resolution of conversions

`impl W<u32, Reg<u32, _CMDH15>>`[src]

`pub fn wait_trig(&mut self) -> WAIT_TRIG_W<'_>`[src]

Bit 2 - Wait for trigger assertion before execution.

`pub fn lwi(&mut self) -> LWI_W<'_>`[src]

Bit 7 - Loop with Increment

`pub fn sts(&mut self) -> STS_W<'_>`[src]

Bits 8:10 - Sample Time Select

`pub fn avgs(&mut self) -> AVGS_W<'_>`[src]

Bits 12:14 - Hardware Average Select

`pub fn loop_(&mut self) -> LOOP_W<'_>`[src]

Bits 16:19 - Loop Count Select

`pub fn next(&mut self) -> NEXT_W<'_>`[src]

Bits 24:27 - Next Command Select

`impl W<u32, Reg<u32, _CV>>`[src]

`pub fn cvl(&mut self) -> CVL_W<'_>`[src]

Bits 0:15 - Compare Value Low.

`pub fn cvh(&mut self) -> CVH_W<'_>`[src]

Bits 16:31 - Compare Value High.

`impl W<u32, Reg<u32, _CAL_GAR>>`[src]

`pub fn cal_gar_val(&mut self) -> CAL_GAR_VAL_W<'_>`[src]

Bits 0:15 - Calibration General A Side Register Element

`impl W<u32, Reg<u32, _CAL_GBR>>`[src]

`pub fn cal_gbr_val(&mut self) -> CAL_GBR_VAL_W<'_>`[src]

Bits 0:15 - Calibration General B Side Register Element

`impl W<u32, Reg<u32, _TST>>`[src]

`pub fn cst_long(&mut self) -> CST_LONG_W<'_>`[src]

Bit 0 - Calibration Sample Time Long

`pub fn foffm(&mut self) -> FOFFM_W<'_>`[src]

Bit 8 - Force M-side positive offset

`pub fn foffp(&mut self) -> FOFFP_W<'_>`[src]

Bit 9 - Force P-side positive offset

`pub fn foffm2(&mut self) -> FOFFM2_W<'_>`[src]

Bit 10 - Force M-side negative offset

`pub fn foffp2(&mut self) -> FOFFP2_W<'_>`[src]

Bit 11 - Force P-side negative offset

`pub fn testen(&mut self) -> TESTEN_W<'_>`[src]

Bit 23 - Enable test configuration

`impl W<u32, Reg<u32, _HCCONTROL>>`[src]

`pub fn cbsr(&mut self) -> CBSR_W<'_>`[src]

Bits 0:1 - ControlBulkServiceRatio.

`pub fn ple(&mut self) -> PLE_W<'_>`[src]

Bit 2 - PeriodicListEnable.

`pub fn ie(&mut self) -> IE_W<'_>`[src]

Bit 3 - IsochronousEnable.

`pub fn cle(&mut self) -> CLE_W<'_>`[src]

Bit 4 - ControlListEnable.

`pub fn ble(&mut self) -> BLE_W<'_>`[src]

Bit 5 - BulkListEnable This bit is set to enable the processing of the Bulk list in the next Frame.

`pub fn hcfs(&mut self) -> HCFS_W<'_>`[src]

Bits 6:7 - HostControllerFunctionalState for USB 00b: USBRESET 01b: USBRESUME 10b: USBOPERATIONAL 11b: USBSUSPEND A transition to USBOPERATIONAL from another state causes SOFgeneration to begin 1 ms later.

`pub fn ir(&mut self) -> IR_W<'_>`[src]

Bit 8 - InterruptRouting This bit determines the routing of interrupts generated by events registered in HcInterruptStatus.

`pub fn rwc(&mut self) -> RWC_W<'_>`[src]

Bit 9 - RemoteWakeupConnected This bit indicates whether HC supports remote wake-up signaling.

`pub fn rwe(&mut self) -> RWE_W<'_>`[src]

Bit 10 - RemoteWakeupEnable This bit is used by HCD to enable or disable the remote wake-up feature upon the detection of upstream resume signaling.

`impl W<u32, Reg<u32, _HCCOMMANDSTATUS>>`[src]

`pub fn hcr(&mut self) -> HCR_W<'_>`[src]

Bit 0 - HostControllerReset This bit is set by HCD to initiate a software reset of HC.

`pub fn clf(&mut self) -> CLF_W<'_>`[src]

Bit 1 - ControlListFilled This bit is used to indicate whether there are any TDs on the Control list.

`pub fn blf(&mut self) -> BLF_W<'_>`[src]

Bit 2 - BulkListFilled This bit is used to indicate whether there are any TDs on the Bulk list.

`pub fn ocr(&mut self) -> OCR_W<'_>`[src]

Bit 3 - OwnershipChangeRequest This bit is set by an OS HCD to request a change of control of the HC.

`pub fn soc(&mut self) -> SOC_W<'_>`[src]

Bits 6:7 - SchedulingOverrunCount These bits are incremented on each scheduling overrun error.

`impl W<u32, Reg<u32, _HCINTERRUPTSTATUS>>`[src]

`pub fn so(&mut self) -> SO_W<'_>`[src]

Bit 0 - SchedulingOverrun This bit is set when the USB schedule for the current Frame overruns and after the update of HccaFrameNumber.

`pub fn wdh(&mut self) -> WDH_W<'_>`[src]

Bit 1 - WritebackDoneHead This bit is set immediately after HC has written HcDoneHead to HccaDoneHead.

`pub fn sf(&mut self) -> SF_W<'_>`[src]

Bit 2 - StartofFrame This bit is set by HC at each start of a frame and after the update of HccaFrameNumber.

`pub fn rd(&mut self) -> RD_W<'_>`[src]

Bit 3 - ResumeDetected This bit is set when HC detects that a device on the USB is asserting resume signaling.

`pub fn ue(&mut self) -> UE_W<'_>`[src]

Bit 4 - UnrecoverableError This bit is set when HC detects a system error not related to USB.

`pub fn fno(&mut self) -> FNO_W<'_>`[src]

Bit 5 - FrameNumberOverflow This bit is set when the MSb of HcFmNumber (bit 15) changes value, from 0 to 1 or from 1 to 0, and after HccaFrameNumber has been updated.

`pub fn rhsc(&mut self) -> RHSC_W<'_>`[src]

Bit 6 - RootHubStatusChange This bit is set when the content of HcRhStatus or the content of any of HcRhPortStatus[NumberofDownstreamPort] has changed.

`pub fn oc(&mut self) -> OC_W<'_>`[src]

Bits 10:31 - OwnershipChange This bit is set by HC when HCD sets the OwnershipChangeRequest field in HcCommandStatus.

`impl W<u32, Reg<u32, _HCINTERRUPTENABLE>>`[src]

`pub fn so(&mut self) -> SO_W<'_>`[src]

Bit 0 - Scheduling Overrun interrupt.

`pub fn wdh(&mut self) -> WDH_W<'_>`[src]

Bit 1 - HcDoneHead Writeback interrupt.

`pub fn sf(&mut self) -> SF_W<'_>`[src]

Bit 2 - Start of Frame interrupt.

`pub fn rd(&mut self) -> RD_W<'_>`[src]

Bit 3 - Resume Detect interrupt.

`pub fn ue(&mut self) -> UE_W<'_>`[src]

Bit 4 - Unrecoverable Error interrupt.

`pub fn fno(&mut self) -> FNO_W<'_>`[src]

Bit 5 - Frame Number Overflow interrupt.

`pub fn rhsc(&mut self) -> RHSC_W<'_>`[src]

Bit 6 - Root Hub Status Change interrupt.

`pub fn oc(&mut self) -> OC_W<'_>`[src]

Bit 30 - Ownership Change interrupt.

`pub fn mie(&mut self) -> MIE_W<'_>`[src]

Bit 31 - Master Interrupt Enable.

`impl W<u32, Reg<u32, _HCINTERRUPTDISABLE>>`[src]

`pub fn so(&mut self) -> SO_W<'_>`[src]

Bit 0 - Scheduling Overrun interrupt.

`pub fn wdh(&mut self) -> WDH_W<'_>`[src]

Bit 1 - HcDoneHead Writeback interrupt.

`pub fn sf(&mut self) -> SF_W<'_>`[src]

Bit 2 - Start of Frame interrupt.

`pub fn rd(&mut self) -> RD_W<'_>`[src]

Bit 3 - Resume Detect interrupt.

`pub fn ue(&mut self) -> UE_W<'_>`[src]

Bit 4 - Unrecoverable Error interrupt.

`pub fn fno(&mut self) -> FNO_W<'_>`[src]

Bit 5 - Frame Number Overflow interrupt.

`pub fn rhsc(&mut self) -> RHSC_W<'_>`[src]

Bit 6 - Root Hub Status Change interrupt.

`pub fn oc(&mut self) -> OC_W<'_>`[src]

Bit 30 - Ownership Change interrupt.

`pub fn mie(&mut self) -> MIE_W<'_>`[src]

Bit 31 - A 0 written to this field is ignored by HC.

`impl W<u32, Reg<u32, _HCHCCA>>`[src]

`pub fn hcca(&mut self) -> HCCA_W<'_>`[src]

Bits 8:31 - Base address of the Host Controller Communication Area.

`impl W<u32, Reg<u32, _HCCONTROLHEADED>>`[src]

`pub fn ched(&mut self) -> CHED_W<'_>`[src]

Bits 4:31 - HC traverses the Control list starting with the HcControlHeadED pointer.

`impl W<u32, Reg<u32, _HCCONTROLCURRENTED>>`[src]

`pub fn cced(&mut self) -> CCED_W<'_>`[src]

Bits 4:31 - ControlCurrentED.

`impl W<u32, Reg<u32, _HCBULKHEADED>>`[src]

`pub fn bhed(&mut self) -> BHED_W<'_>`[src]

Bits 4:31 - BulkHeadED HC traverses the bulk list starting with the HcBulkHeadED pointer.

`impl W<u32, Reg<u32, _HCBULKCURRENTED>>`[src]

`pub fn bced(&mut self) -> BCED_W<'_>`[src]

Bits 4:31 - BulkCurrentED This is advanced to the next ED after the HC has served the current one.

`impl W<u32, Reg<u32, _HCFMINTERVAL>>`[src]

`pub fn fi(&mut self) -> FI_W<'_>`[src]

Bits 0:13 - FrameInterval This specifies the interval between two consecutive SOFs in bit times.

`pub fn fsmps(&mut self) -> FSMPS_W<'_>`[src]

Bits 16:30 - FSLargestDataPacket This field specifies a value which is loaded into the Largest Data Packet Counter at the beginning of each frame.

`pub fn fit(&mut self) -> FIT_W<'_>`[src]

Bit 31 - FrameIntervalToggle HCD toggles this bit whenever it loads a new value to FrameInterval.

`impl W<u32, Reg<u32, _HCPERIODICSTART>>`[src]

`pub fn ps(&mut self) -> PS_W<'_>`[src]

Bits 0:13 - PeriodicStart After a hardware reset, this field is cleared and then set by HCD during the HC initialization.

`impl W<u32, Reg<u32, _HCLSTHRESHOLD>>`[src]

`pub fn lst(&mut self) -> LST_W<'_>`[src]

Bits 0:11 - LSThreshold This field contains a value which is compared to the FrameRemaining field prior to initiating a Low Speed transaction.

`impl W<u32, Reg<u32, _HCRHDESCRIPTORA>>`[src]

`pub fn ndp(&mut self) -> NDP_W<'_>`[src]

Bits 0:7 - NumberDownstreamPorts These bits specify the number of downstream ports supported by the root hub.

`pub fn psm(&mut self) -> PSM_W<'_>`[src]

Bit 8 - PowerSwitchingMode This bit is used to specify how the power switching of the root hub ports is controlled.

`pub fn nps(&mut self) -> NPS_W<'_>`[src]

Bit 9 - NoPowerSwitching These bits are used to specify whether power switching is supported or port are always powered.

`pub fn dt(&mut self) -> DT_W<'_>`[src]

Bit 10 - DeviceType This bit specifies that the root hub is not a compound device.

`pub fn ocpm(&mut self) -> OCPM_W<'_>`[src]

Bit 11 - OverCurrentProtectionMode This bit describes how the overcurrent status for the root hub ports are reported.

`pub fn nocp(&mut self) -> NOCP_W<'_>`[src]

Bit 12 - NoOverCurrentProtection This bit describes how the overcurrent status for the root hub ports are reported.

`pub fn potpgt(&mut self) -> POTPGT_W<'_>`[src]

Bits 24:31 - PowerOnToPowerGoodTime This byte specifies the duration the HCD has to wait before accessing a powered-on port of the root hub.

`impl W<u32, Reg<u32, _HCRHDESCRIPTORB>>`[src]

`pub fn dr(&mut self) -> DR_W<'_>`[src]

Bits 0:15 - DeviceRemovable Each bit is dedicated to a port of the Root Hub.

`pub fn ppcm(&mut self) -> PPCM_W<'_>`[src]

Bits 16:31 - PortPowerControlMask Each bit indicates if a port is affected by a global power control command when PowerSwitchingMode is set.

`impl W<u32, Reg<u32, _HCRHSTATUS>>`[src]

`pub fn lps(&mut self) -> LPS_W<'_>`[src]

Bit 0 - (read) LocalPowerStatus The Root Hub does not support the local power status feature; thus, this bit is always read as 0.

`pub fn oci(&mut self) -> OCI_W<'_>`[src]

Bit 1 - OverCurrentIndicator This bit reports overcurrent conditions when the global reporting is implemented.

`pub fn drwe(&mut self) -> DRWE_W<'_>`[src]

Bit 15 - (read) DeviceRemoteWakeupEnable This bit enables a ConnectStatusChange bit as a resume event, causing a USBSUSPEND to USBRESUME state transition and setting the ResumeDetected interrupt.

`pub fn lpsc(&mut self) -> LPSC_W<'_>`[src]

Bit 16 - (read) LocalPowerStatusChange The root hub does not support the local power status feature.

`pub fn ocic(&mut self) -> OCIC_W<'_>`[src]

Bit 17 - OverCurrentIndicatorChange This bit is set by hardware when a change has occurred to the OCI field of this register.

`pub fn crwe(&mut self) -> CRWE_W<'_>`[src]

Bit 31 - (write) ClearRemoteWakeupEnable Writing a 1 clears DeviceRemoveWakeupEnable.

`impl W<u32, Reg<u32, _HCRHPORTSTATUS>>`[src]

`pub fn ccs(&mut self) -> CCS_W<'_>`[src]

Bit 0 - (read) CurrentConnectStatus This bit reflects the current state of the downstream port.

`pub fn pes(&mut self) -> PES_W<'_>`[src]

Bit 1 - (read) PortEnableStatus This bit indicates whether the port is enabled or disabled.

`pub fn pss(&mut self) -> PSS_W<'_>`[src]

Bit 2 - (read) PortSuspendStatus This bit indicates the port is suspended or in the resume sequence.

`pub fn poci(&mut self) -> POCI_W<'_>`[src]

Bit 3 - (read) PortOverCurrentIndicator This bit is only valid when the Root Hub is configured in such a way that overcurrent conditions are reported on a per-port basis.

`pub fn prs(&mut self) -> PRS_W<'_>`[src]

Bit 4 - (read) PortResetStatus When this bit is set by a write to SetPortReset, port reset signaling is asserted.

`pub fn pps(&mut self) -> PPS_W<'_>`[src]

Bit 8 - (read) PortPowerStatus This bit reflects the porta's power status, regardless of the type of power switching implemented.

`pub fn lsda(&mut self) -> LSDA_W<'_>`[src]

Bit 9 - (read) LowSpeedDeviceAttached This bit indicates the speed of the device attached to this port.

`pub fn csc(&mut self) -> CSC_W<'_>`[src]

Bit 16 - ConnectStatusChange This bit is set whenever a connect or disconnect event occurs.

`pub fn pesc(&mut self) -> PESC_W<'_>`[src]

Bit 17 - PortEnableStatusChange This bit is set when hardware events cause the PortEnableStatus bit to be cleared.

`pub fn pssc(&mut self) -> PSSC_W<'_>`[src]

Bit 18 - PortSuspendStatusChange This bit is set when the full resume sequence is completed.

`pub fn ocic(&mut self) -> OCIC_W<'_>`[src]

Bit 19 - PortOverCurrentIndicatorChange This bit is valid only if overcurrent conditions are reported on a per-port basis.

`pub fn prsc(&mut self) -> PRSC_W<'_>`[src]

Bit 20 - PortResetStatusChange This bit is set at the end of the 10 ms port reset signal.

`impl W<u32, Reg<u32, _PORTMODE>>`[src]

`pub fn id(&mut self) -> ID_W<'_>`[src]

Bit 0 - Port ID pin value.

`pub fn id_en(&mut self) -> ID_EN_W<'_>`[src]

Bit 8 - Port ID pin pull-up enable.

`pub fn dev_enable(&mut self) -> DEV_ENABLE_W<'_>`[src]

Bit 16 - 1: device 0: host.

`impl W<u32, Reg<u32, _FLADJ_FRINDEX>>`[src]

`pub fn fladj(&mut self) -> FLADJ_W<'_>`[src]

Bits 0:5 - Frame Length Timing Value.

`pub fn frindex(&mut self) -> FRINDEX_W<'_>`[src]

Bits 16:29 - Frame Index: Bits 29 to16 in this register are used for the frame number field in the SOF packet.

`impl W<u32, Reg<u32, _ATLPTD>>`[src]

`pub fn atl_cur(&mut self) -> ATL_CUR_W<'_>`[src]

Bits 4:8 - This indicates the current PTD that is used by the hardware when it is processing the ATL list.

`pub fn atl_base(&mut self) -> ATL_BASE_W<'_>`[src]

Bits 9:31 - Base address to be used by the hardware to find the start of the ATL list.

`impl W<u32, Reg<u32, _ISOPTD>>`[src]

`pub fn iso_first(&mut self) -> ISO_FIRST_W<'_>`[src]

Bits 5:9 - This indicates the first PTD that is used by the hardware when it is processing the ISO list.

`pub fn iso_base(&mut self) -> ISO_BASE_W<'_>`[src]

Bits 10:31 - Base address to be used by the hardware to find the start of the ISO list.

`impl W<u32, Reg<u32, _INTPTD>>`[src]

`pub fn int_first(&mut self) -> INT_FIRST_W<'_>`[src]

Bits 5:9 - This indicates the first PTD that is used by the hardware when it is processing the INT list.

`pub fn int_base(&mut self) -> INT_BASE_W<'_>`[src]

Bits 10:31 - Base address to be used by the hardware to find the start of the INT list.

`impl W<u32, Reg<u32, _DATAPAYLOAD>>`[src]

`pub fn dat_base(&mut self) -> DAT_BASE_W<'_>`[src]

Bits 16:31 - Base address to be used by the hardware to find the start of the data payload section.

`impl W<u32, Reg<u32, _USBCMD>>`[src]

`pub fn rs(&mut self) -> RS_W<'_>`[src]

Bit 0 - Run/Stop: 1b = Run.

`pub fn hcreset(&mut self) -> HCRESET_W<'_>`[src]

Bit 1 - Host Controller Reset: This control bit is used by the software to reset the host controller.

`pub fn fls(&mut self) -> FLS_W<'_>`[src]

Bits 2:3 - Frame List Size: This field specifies the size of the frame list.

`pub fn lhcr(&mut self) -> LHCR_W<'_>`[src]

Bit 7 - Light Host Controller Reset: This bit allows the driver software to reset the host controller without affecting the state of the ports.

`pub fn atl_en(&mut self) -> ATL_EN_W<'_>`[src]

Bit 8 - ATL List enabled.

`pub fn iso_en(&mut self) -> ISO_EN_W<'_>`[src]

Bit 9 - ISO List enabled.

`pub fn int_en(&mut self) -> INT_EN_W<'_>`[src]

Bit 10 - INT List enabled.

`impl W<u32, Reg<u32, _USBSTS>>`[src]

`pub fn pcd(&mut self) -> PCD_W<'_>`[src]

Bit 2 - Port Change Detect: The host controller sets this bit to logic 1 when any port has a change bit transition from a 0 to a one or a Force Port Resume bit transition from a 0 to a 1 as a result of a J-K transition detected on a suspended port.

`pub fn flr(&mut self) -> FLR_W<'_>`[src]

Bit 3 - Frame List Rollover: The host controller sets this bit to logic 1 when the frame list index rolls over its maximum value to 0.

`pub fn atl_irq(&mut self) -> ATL_IRQ_W<'_>`[src]

Bit 16 - ATL IRQ: Indicates that an ATL PTD (with I-bit set) was completed.

`pub fn iso_irq(&mut self) -> ISO_IRQ_W<'_>`[src]

Bit 17 - ISO IRQ: Indicates that an ISO PTD (with I-bit set) was completed.

`pub fn int_irq(&mut self) -> INT_IRQ_W<'_>`[src]

Bit 18 - INT IRQ: Indicates that an INT PTD (with I-bit set) was completed.

`pub fn sof_irq(&mut self) -> SOF_IRQ_W<'_>`[src]

Bit 19 - SOF interrupt: Every time when the host sends a Start of Frame token on the USB bus, this bit is set.

`impl W<u32, Reg<u32, _USBINTR>>`[src]

`pub fn pcde(&mut self) -> PCDE_W<'_>`[src]

Bit 2 - Port Change Detect Interrupt Enable: 1: enable 0: disable.

`pub fn flre(&mut self) -> FLRE_W<'_>`[src]

Bit 3 - Frame List Rollover Interrupt Enable: 1: enable 0: disable.

`pub fn atl_irq_e(&mut self) -> ATL_IRQ_E_W<'_>`[src]

Bit 16 - ATL IRQ Enable bit: 1: enable 0: disable.

`pub fn iso_irq_e(&mut self) -> ISO_IRQ_E_W<'_>`[src]

Bit 17 - ISO IRQ Enable bit: 1: enable 0: disable.

`pub fn int_irq_e(&mut self) -> INT_IRQ_E_W<'_>`[src]

Bit 18 - INT IRQ Enable bit: 1: enable 0: disable.

`pub fn sof_e(&mut self) -> SOF_E_W<'_>`[src]

Bit 19 - SOF Interrupt Enable bit: 1: enable 0: disable.

`impl W<u32, Reg<u32, _PORTSC1>>`[src]

`pub fn ccs(&mut self) -> CCS_W<'_>`[src]

Bit 0 - Current Connect Status: Logic 1 indicates a device is present on the port.

`pub fn csc(&mut self) -> CSC_W<'_>`[src]

Bit 1 - Connect Status Change: Logic 1 means that the value of CCS has changed.

`pub fn ped(&mut self) -> PED_W<'_>`[src]

Bit 2 - Port Enabled/Disabled.

`pub fn pedc(&mut self) -> PEDC_W<'_>`[src]

Bit 3 - Port Enabled/Disabled Change: Logic 1 means that the value of PED has changed.

`pub fn oca(&mut self) -> OCA_W<'_>`[src]

Bit 4 - Over-current active: Logic 1 means that this port has an over-current condition.

`pub fn occ(&mut self) -> OCC_W<'_>`[src]

Bit 5 - Over-current change: Logic 1 means that the value of OCA has changed.

`pub fn fpr(&mut self) -> FPR_W<'_>`[src]

Bit 6 - Force Port Resume: Logic 1 means resume (K-state) detected or driven on the port.

`pub fn susp(&mut self) -> SUSP_W<'_>`[src]

Bit 7 - Suspend: Logic 1 means port is in the suspend state.

`pub fn pr(&mut self) -> PR_W<'_>`[src]

Bit 8 - Port Reset: Logic 1 means the port is in the reset state.

`pub fn pp(&mut self) -> PP_W<'_>`[src]

Bit 12 - Port Power: The function of this bit depends on the value of the Port Power Control (PPC) bit in the HCSPARAMS register.

`pub fn pic(&mut self) -> PIC_W<'_>`[src]

Bits 14:15 - Port Indicator Control : Writing to this field has no effect if the P_INDICATOR bit in the HCSPARAMS register is logic 0.

`pub fn ptc(&mut self) -> PTC_W<'_>`[src]

Bits 16:19 - Port Test Control: A non-zero value indicates that the port is operating in the test mode as indicated by the value.

`pub fn pspd(&mut self) -> PSPD_W<'_>`[src]

Bits 20:21 - Port Speed: 00b: Low-speed 01b: Full-speed 10b: High-speed 11b: Reserved.

`pub fn woo(&mut self) -> WOO_W<'_>`[src]

Bit 22 - Wake on overcurrent enable: Writing this bit to a one enables the port to be sensitive to overcurrent conditions as wake-up events.

`impl W<u32, Reg<u32, _ATLPTDD>>`[src]

`pub fn atl_done(&mut self) -> ATL_DONE_W<'_>`[src]

Bits 0:31 - The bit corresponding to a certain PTD will be set to logic 1 as soon as that PTD execution is completed.

`impl W<u32, Reg<u32, _ATLPTDS>>`[src]

`pub fn atl_skip(&mut self) -> ATL_SKIP_W<'_>`[src]

Bits 0:31 - When a bit in the PTD Skip Map is set to logic 1, the corresponding PTD will be skipped, independent of the V bit setting.

`impl W<u32, Reg<u32, _ISOPTDD>>`[src]

`pub fn iso_done(&mut self) -> ISO_DONE_W<'_>`[src]

Bits 0:31 - The bit corresponding to a certain PTD will be set to logic 1 as soon as that PTD execution is completed.

`impl W<u32, Reg<u32, _ISOPTDS>>`[src]

`pub fn iso_skip(&mut self) -> ISO_SKIP_W<'_>`[src]

Bits 0:31 - The bit corresponding to a certain PTD will be set to logic 1 as soon as that PTD execution is completed.

`impl W<u32, Reg<u32, _INTPTDD>>`[src]

`pub fn int_done(&mut self) -> INT_DONE_W<'_>`[src]

Bits 0:31 - The bit corresponding to a certain PTD will be set to logic 1 as soon as that PTD execution is completed.

`impl W<u32, Reg<u32, _INTPTDS>>`[src]

`pub fn int_skip(&mut self) -> INT_SKIP_W<'_>`[src]

Bits 0:31 - When a bit in the PTD Skip Map is set to logic 1, the corresponding PTD will be skipped, independent of the V bit setting.

`impl W<u32, Reg<u32, _LASTPTD>>`[src]

`pub fn atl_last(&mut self) -> ATL_LAST_W<'_>`[src]

Bits 0:4 - If hardware has reached this PTD and the J bit is not set, it will go to PTD0 as the next PTD to be processed.

`pub fn iso_last(&mut self) -> ISO_LAST_W<'_>`[src]

Bits 8:12 - This indicates the last PTD in the ISO list.

`pub fn int_last(&mut self) -> INT_LAST_W<'_>`[src]

Bits 16:20 - This indicates the last PTD in the INT list.

`impl W<u32, Reg<u32, _PORTMODE>>`[src]

`pub fn dev_enable(&mut self) -> DEV_ENABLE_W<'_>`[src]

Bit 16 - If this bit is set to one, one of the ports will behave as a USB device.

`pub fn sw_ctrl_pdcom(&mut self) -> SW_CTRL_PDCOM_W<'_>`[src]

Bit 18 - This bit indicates if the PHY power-down input is controlled by software or by hardware.

`pub fn sw_pdcom(&mut self) -> SW_PDCOM_W<'_>`[src]

Bit 19 - This bit is only used when SW_CTRL_PDCOM is set to 1b.

`impl W<u32, Reg<u32, _CTRL>>`[src]

`pub fn mode(&mut self) -> MODE_W<'_>`[src]

Bits 0:2 - The operational mode to use, or 0 if none. Note that the CONFIG register will indicate if specific modes beyond SHA1 and SHA2-256 are available.

`pub fn new_hash(&mut self) -> NEW_HASH_W<'_>`[src]

Bit 4 - Written with 1 when starting a new Hash/Crypto. It self clears. Note that the WAITING Status bit will clear for a cycle during the initialization from New=1.

`pub fn dma_i(&mut self) -> DMA_I_W<'_>`[src]

Bit 8 - Written with 1 to use DMA to fill INDATA. If Hash, will request from DMA for 16 words and then will process the Hash. If Cryptographic, it will load as many words as needed, including key if not already loaded. It will then request again. Normal model is that the DMA interrupts the processor when its length expires. Note that if the processor will write the key and optionally IV, it should not enable this until it has done so. Otherwise, the DMA will be expected to load those for the 1st block (when needed).

`pub fn dma_o(&mut self) -> DMA_O_W<'_>`[src]

Bit 9 - Written to 1 to use DMA to drain the digest/output. If both DMA_I and DMA_O are set, the DMA has to know to switch direction and the locations. This can be used for crypto uses.

`pub fn hashswpb(&mut self) -> HASHSWPB_W<'_>`[src]

Bit 12 - If 1, will swap bytes in the word for SHA hashing. The default is byte order (so LSB is 1st byte) but this allows swapping to MSB is 1st such as is shown in SHS spec. For cryptographic swapping, see the CRYPTCFG register.

`impl W<u32, Reg<u32, _STATUS>>`[src]

`pub fn error(&mut self) -> ERROR_W<'_>`[src]

Bit 2 - If 1, an error occurred. For normal uses, this is due to an attempted overrun: INDATA was written when it was not appropriate. For Master cases, this is an AHB bus error; the COUNT field will indicate which block it was on.

`impl W<u32, Reg<u32, _INTENSET>>`[src]

`pub fn waiting(&mut self) -> WAITING_W<'_>`[src]

Bit 0 - Indicates if should interrupt when waiting for data input.

`pub fn digest(&mut self) -> DIGEST_W<'_>`[src]

Bit 1 - Indicates if should interrupt when Digest (or Outdata) is ready (completed a hash/crypto or completed a full sequence).

`pub fn error(&mut self) -> ERROR_W<'_>`[src]

Bit 2 - Indicates if should interrupt on an ERROR (as defined in Status)

`impl W<u32, Reg<u32, _INTENCLR>>`[src]

`pub fn waiting(&mut self) -> WAITING_W<'_>`[src]

Bit 0 - Write 1 to clear mask.

`pub fn digest(&mut self) -> DIGEST_W<'_>`[src]

Bit 1 - Write 1 to clear mask.

`pub fn error(&mut self) -> ERROR_W<'_>`[src]

Bit 2 - Write 1 to clear mask.

`impl W<u32, Reg<u32, _MEMCTRL>>`[src]

`pub fn master(&mut self) -> MASTER_W<'_>`[src]

Bit 0 - Enables mastering.

`pub fn count(&mut self) -> COUNT_W<'_>`[src]

Bits 16:26 - Number of 512-bit (128-bit if AES, except 1st block which may include key and IV) blocks to copy starting at MEMADDR. This register will decrement after each block is copied, ending in 0. For Hash, the DIGEST interrupt will occur when it reaches 0. Fro AES, the DIGEST/OUTDATA interrupt will occur on ever block. If a bus error occurs, it will stop with this field set to the block that failed. 0:Done - nothing to process. 1 to 2K: Number of 512-bit (or 128bit) blocks to hash.

`impl W<u32, Reg<u32, _MEMADDR>>`[src]

`pub fn base(&mut self) -> BASE_W<'_>`[src]

Bits 0:31 - Address base to start copying from, word aligned (so bits 1:0 must be 0). This field will advance as it processes the words. If it fails with a bus error, the register will contain the failing word. N:Address in Flash or RAM space; RAM only as mapped in this part. May also be able to address SPIFI.

`impl W<u32, Reg<u32, _INDATA>>`[src]

`pub fn data(&mut self) -> DATA_W<'_>`[src]

Bits 0:31 - Write next word in little-endian form. The hash requires big endian word data, but this block swaps the bytes automatically. That is, SHA assumes the data coming in is treated as bytes (e.g. "abcd") and since the ARM core will treat "abcd" as a word as 0x64636261, the block will swap the word to restore into big endian.

`impl W<u32, Reg<u32, _ALIAS>>`[src]

`pub fn data(&mut self) -> DATA_W<'_>`[src]

Bits 0:31 - Write next word in little-endian form. The hash requires big endian word data, but this block swaps the bytes automatically. That is, SHA assumes the data coming in is treated as bytes (e.g. "abcd") and since the ARM core will treat "abcd" as a word as 0x64636261, the block will swap the word to restore into big endian.

`impl W<u32, Reg<u32, _CRYPTCFG>>`[src]

`pub fn msw1st_out(&mut self) -> MSW1ST_OUT_W<'_>`[src]

Bit 0 - If 1, OUTDATA0 will be read Most significant word 1st for AES. Else it will be read in normal little endian - Least significant word 1st. Note: only if allowed by configuration.

`pub fn swapkey(&mut self) -> SWAPKEY_W<'_>`[src]

Bit 1 - If 1, will Swap the key input (bytes in each word).

`pub fn swapdat(&mut self) -> SWAPDAT_W<'_>`[src]

Bit 2 - If 1, will SWAP the data and IV inputs (bytes in each word).

`pub fn msw1st(&mut self) -> MSW1ST_W<'_>`[src]

Bit 3 - If 1, load of key, IV, and data is MSW 1st for AES. Else, the words are little endian. Note: only if allowed by configuration.

`pub fn aesmode(&mut self) -> AESMODE_W<'_>`[src]

Bits 4:5 - AES Cipher mode to use if plain AES

`pub fn aesdecrypt(&mut self) -> AESDECRYPT_W<'_>`[src]

Bit 6 - AES ECB direction. Only encryption used if CTR mode or manual modes such as CFB

`pub fn aessecret(&mut self) -> AESSECRET_W<'_>`[src]

Bit 7 - Selects the Hidden Secret key vs. User key, if provided. If security levels are used, only the highest level is permitted to select this.

`pub fn aeskeysz(&mut self) -> AESKEYSZ_W<'_>`[src]

Bits 8:9 - Sets the AES key size

`pub fn aesctrpos(&mut self) -> AESCTRPOS_W<'_>`[src]

Bits 10:12 - Halfword position of 16b counter in IV if AESMODE is CTR (position is fixed for Salsa and ChaCha). Only supports 16b counter, so application must control any additional bytes if using more. The 16-bit counter is read from the IV and incremented by 1 each time. Any other use CTR should use ECB directly and do its own XOR and so on.

`pub fn streamlast(&mut self) -> STREAMLAST_W<'_>`[src]

Bit 16 - Is 1 if last stream block. If not 1, then the engine will compute the next "hash".

`pub fn icbsz(&mut self) -> ICBSZ_W<'_>`[src]

Bits 20:21 - This sets the ICB size between 32 and 128 bits, using the following rules. Note that the counter is assumed to occupy the low order bits of the IV.

`pub fn icbstrm(&mut self) -> ICBSTRM_W<'_>`[src]

Bits 22:23 - The size of the ICB-AES stream that can be pushed before needing to compute a new IV/ctr (counter start). This optimizes the performance of the stream of blocks after the 1st.

`impl W<u32, Reg<u32, _LOCK>>`[src]

`pub fn seclock(&mut self) -> SECLOCK_W<'_>`[src]

Bits 0:1 - Write 1 to secure-lock this block (if running in a security state). Write 0 to unlock. If locked already, may only write if at same or higher security level as lock. Reads as: 0 if unlocked, else 1, 2, 3 to indicate security level it is locked at. NOTE: this and ID are the only readable registers if locked and current state is lower than lock level.

`pub fn pattern(&mut self) -> PATTERN_W<'_>`[src]

Bits 4:15 - Must write 0xA75 to change lock state. A75:Pattern needed to change bits 1:0

`impl W<u32, Reg<u32, _MASK>>`[src]

`pub fn mask(&mut self) -> MASK_W<'_>`[src]

Bits 0:31 - A random word.

`impl W<u32, Reg<u32, _CTRL0>>`[src]

`pub fn abbpair(&mut self) -> ABBPAIR_W<'_>`[src]

Bit 0 - Which bank-pair the offset ABOFF is within. This must be 0 if only 2-up

`pub fn aboff(&mut self) -> ABOFF_W<'_>`[src]

Bit 2 - Word or DWord Offset of AB values, with B at [2]=0 and A at [2]=1 as far as the code sees (normally will be an interleaved bank so only sequential to AHB). Word offset only allowed if 32 bit operation. Ideally not in the same RAM as the CD values if 4-up

`pub fn cdbpair(&mut self) -> CDBPAIR_W<'_>`[src]

Bit 16 - Which bank-pair the offset CDOFF is within. This must be 0 if only 2-up

`pub fn cdoff(&mut self) -> CDOFF_W<'_>`[src]

Bits 18:28 - Word or DWord Offset of CD, with D at [2]=0 and C at [2]=1 as far as the code sees (normally will be an interleaved bank so only sequential to AHB). Word offset only allowed if 32 bit operation. Ideally not in the same RAM as the AB values

`impl W<u32, Reg<u32, _CTRL1>>`[src]

`pub fn iter(&mut self) -> ITER_W<'_>`[src]

Bits 0:7 - Iteration counter. Is number_cycles - 1. write 0 means Does one cycle - does not iterate.

`pub fn mode(&mut self) -> MODE_W<'_>`[src]

Bits 8:15 - Operation mode to perform. write 0 means Accelerator is inactive. write others means accelerator is active.

`pub fn resbpair(&mut self) -> RESBPAIR_W<'_>`[src]

Bit 16 - Which bank-pair the offset RESOFF is within. This must be 0 if only 2-up. Ideally this is not the same bank as ABBPAIR (when 4-up supported)

`pub fn resoff(&mut self) -> RESOFF_W<'_>`[src]

Bits 18:28 - Word or DWord Offset of result. Word offset only allowed if 32 bit operation. Ideally not in the same RAM as the AB and CD values

`pub fn cskip(&mut self) -> CSKIP_W<'_>`[src]

Bits 30:31 - Skip rules on Carry if needed. This operation will be skipped based on Carry value (from previous operation) if not 0:

`impl W<u32, Reg<u32, _LOADER>>`[src]

`pub fn count(&mut self) -> COUNT_W<'_>`[src]

Bits 0:7 - Number of control pairs to load 0 relative (so 1 means load 1). write 1 means Does one op - does not iterate, write N means N control pairs to load

`pub fn ctrlbpair(&mut self) -> CTRLBPAIR_W<'_>`[src]

Bit 16 - Which bank-pair the offset CTRLOFF is within. This must be 0 if only 2-up. Does not matter which bank is used as this is loaded when not performing an operation.

`pub fn ctrloff(&mut self) -> CTRLOFF_W<'_>`[src]

Bits 18:28 - DWord Offset of CTRL pair to load next.

`impl W<u32, Reg<u32, _STATUS>>`[src]

`pub fn done(&mut self) -> DONE_W<'_>`[src]

Bit 0 - Indicates if the accelerator has finished an operation. Write 1 to clear, or write CTRL1 to clear.

`impl W<u32, Reg<u32, _INTENSET>>`[src]

`pub fn done(&mut self) -> DONE_W<'_>`[src]

Bit 0 - Set if the accelerator should interrupt when done.

`impl W<u32, Reg<u32, _INTENCLR>>`[src]

`pub fn done(&mut self) -> DONE_W<'_>`[src]

Bit 0 - Written to clear an interrupt set with INTENSET.

`impl W<u32, Reg<u32, _AREG>>`[src]

`pub fn reg_value(&mut self) -> REG_VALUE_W<'_>`[src]

Bits 0:31 - Register to be fed into Multiplier. Is not normally written or read by application, but is available when accelerator not busy.

`impl W<u32, Reg<u32, _BREG>>`[src]

`pub fn reg_value(&mut self) -> REG_VALUE_W<'_>`[src]

Bits 0:31 - Register to be fed into Multiplier. Is not normally written or read by application, but is available when accelerator not busy.

`impl W<u32, Reg<u32, _CREG>>`[src]

`pub fn reg_value(&mut self) -> REG_VALUE_W<'_>`[src]

Bits 0:31 - Register to be fed into Multiplier. Is not normally written or read by application, but is available when accelerator not busy.

`impl W<u32, Reg<u32, _DREG>>`[src]

`pub fn reg_value(&mut self) -> REG_VALUE_W<'_>`[src]

Bits 0:31 - Register to be fed into Multiplier. Is not normally written or read by application, but is available when accelerator not busy.

`impl W<u32, Reg<u32, _RES0>>`[src]

`pub fn reg_value(&mut self) -> REG_VALUE_W<'_>`[src]

Bits 0:31 - Register to hold working result (from multiplier, adder/xor, etc). Is not normally written or read by application, but is available when accelerator not busy.

`impl W<u32, Reg<u32, _RES1>>`[src]

`pub fn reg_value(&mut self) -> REG_VALUE_W<'_>`[src]

Bits 0:31 - Register to hold working result (from multiplier, adder/xor, etc). Is not normally written or read by application, but is available when accelerator not busy.

`impl W<u32, Reg<u32, _RES2>>`[src]

`pub fn reg_value(&mut self) -> REG_VALUE_W<'_>`[src]

Bits 0:31 - Register to hold working result (from multiplier, adder/xor, etc). Is not normally written or read by application, but is available when accelerator not busy.

`impl W<u32, Reg<u32, _RES3>>`[src]

`pub fn reg_value(&mut self) -> REG_VALUE_W<'_>`[src]

Bits 0:31 - Register to hold working result (from multiplier, adder/xor, etc). Is not normally written or read by application, but is available when accelerator not busy.

`impl W<u32, Reg<u32, _MASK>>`[src]

`pub fn mask(&mut self) -> MASK_W<'_>`[src]

Bits 0:31 - Mask to apply as side channel countermeasure. 0: No mask to be used. N: Mask to XOR onto values

`impl W<u32, Reg<u32, _REMASK>>`[src]

`pub fn mask(&mut self) -> MASK_W<'_>`[src]

Bits 0:31 - Mask to apply as side channel countermeasure. 0: No mask to be used. N: Mask to XOR onto values

`impl W<u32, Reg<u32, _LOCK>>`[src]

`pub fn lock(&mut self) -> LOCK_W<'_>`[src]

Bit 0 - Reads back with security level locked to, or 0. Writes as 0 to unlock, 1 to lock.

`pub fn key(&mut self) -> KEY_W<'_>`[src]

Bits 4:16 - Must be written as 0x73D to change the register.

`impl W<u32, Reg<u32, _OUTBASE>>`[src]

`pub fn outbase(&mut self) -> OUTBASE_W<'_>`[src]

Bits 0:31 - Base address register for the output region

`impl W<u32, Reg<u32, _OUTFORMAT>>`[src]

`pub fn out_formatint(&mut self) -> OUT_FORMATINT_W<'_>`[src]

Bits 0:1 - Output Internal format (00: q15; 01:q31; 10:float)

`pub fn out_formatext(&mut self) -> OUT_FORMATEXT_W<'_>`[src]

Bits 4:5 - Output External format (00: q15; 01:q31; 10:float)

`pub fn out_scaler(&mut self) -> OUT_SCALER_W<'_>`[src]

Bits 8:15 - Output Scaler value (for scaled 'q31' formats)

`impl W<u32, Reg<u32, _TMPBASE>>`[src]

`pub fn tmpbase(&mut self) -> TMPBASE_W<'_>`[src]

Bits 0:31 - Base address register for the temporary region

`impl W<u32, Reg<u32, _TMPFORMAT>>`[src]

`pub fn tmp_formatint(&mut self) -> TMP_FORMATINT_W<'_>`[src]

Bits 0:1 - Temp Internal format (00: q15; 01:q31; 10:float)

`pub fn tmp_formatext(&mut self) -> TMP_FORMATEXT_W<'_>`[src]

Bits 4:5 - Temp External format (00: q15; 01:q31; 10:float)

`pub fn tmp_scaler(&mut self) -> TMP_SCALER_W<'_>`[src]

Bits 8:15 - Temp Scaler value (for scaled 'q31' formats)

`impl W<u32, Reg<u32, _INABASE>>`[src]

`pub fn inabase(&mut self) -> INABASE_W<'_>`[src]

Bits 0:31 - Base address register for the input A region

`impl W<u32, Reg<u32, _INAFORMAT>>`[src]

`pub fn ina_formatint(&mut self) -> INA_FORMATINT_W<'_>`[src]

Bits 0:1 - Input A Internal format (00: q15; 01:q31; 10:float)

`pub fn ina_formatext(&mut self) -> INA_FORMATEXT_W<'_>`[src]

Bits 4:5 - Input A External format (00: q15; 01:q31; 10:float)

`pub fn ina_scaler(&mut self) -> INA_SCALER_W<'_>`[src]

Bits 8:15 - Input A Scaler value (for scaled 'q31' formats)

`impl W<u32, Reg<u32, _INBBASE>>`[src]

`pub fn inbbase(&mut self) -> INBBASE_W<'_>`[src]

Bits 0:31 - Base address register for the input B region

`impl W<u32, Reg<u32, _INBFORMAT>>`[src]

`pub fn inb_formatint(&mut self) -> INB_FORMATINT_W<'_>`[src]

Bits 0:1 - Input B Internal format (00: q15; 01:q31; 10:float)

`pub fn inb_formatext(&mut self) -> INB_FORMATEXT_W<'_>`[src]

Bits 4:5 - Input B External format (00: q15; 01:q31; 10:float)

`pub fn inb_scaler(&mut self) -> INB_SCALER_W<'_>`[src]

Bits 8:15 - Input B Scaler value (for scaled 'q31' formats)

`impl W<u32, Reg<u32, _CONTROL>>`[src]

`pub fn decode_opcode(&mut self) -> DECODE_OPCODE_W<'_>`[src]

Bits 0:3 - opcode specific to decode_machine

`pub fn decode_machine(&mut self) -> DECODE_MACHINE_W<'_>`[src]

Bits 4:7 - 0 : Coprocessor , 1 : matrix , 2 : fft , 3 : fir , 4 : stat , 5 : cordic , 6 -15 : NA

`impl W<u32, Reg<u32, _LENGTH>>`[src]

`pub fn inst_length(&mut self) -> INST_LENGTH_W<'_>`[src]

Bits 0:31 - Length register. When FIR : fir_xlength = inst_length[15:0] , fir_tlength = inst_len[31:16]. When MTX : rows_a = inst_length[4:0] , cols_a = inst_length[12:8] , cols_b = inst_length[20:16]

`impl W<u32, Reg<u32, _CPPRE>>`[src]

`pub fn cppre_in(&mut self) -> CPPRE_IN_W<'_>`[src]

Bits 0:7 - co-processor scaling of input

`pub fn cppre_out(&mut self) -> CPPRE_OUT_W<'_>`[src]

Bits 8:15 - co-processor fixed point output

`pub fn cppre_sat(&mut self) -> CPPRE_SAT_W<'_>`[src]

Bit 16 - 1 : forces sub-32 bit saturation

`pub fn cppre_sat8(&mut self) -> CPPRE_SAT8_W<'_>`[src]

Bit 17 - 0 = 8bits, 1 = 16bits

`impl W<u32, Reg<u32, _MISC>>`[src]

`pub fn inst_misc(&mut self) -> INST_MISC_W<'_>`[src]

Bits 0:31 - Misc register. For Matrix : Used for scale factor

`impl W<u32, Reg<u32, _CURSORY>>`[src]

`pub fn cursory(&mut self) -> CURSORY_W<'_>`[src]

Bit 0 - 1 : Enable cursory mode

`impl W<u32, Reg<u32, _CORDIC_X>>`[src]

`pub fn cordic_x(&mut self) -> CORDIC_X_W<'_>`[src]

Bits 0:31 - Cordic input x

`impl W<u32, Reg<u32, _CORDIC_Y>>`[src]

`pub fn cordic_y(&mut self) -> CORDIC_Y_W<'_>`[src]

Bits 0:31 - Cordic input y

`impl W<u32, Reg<u32, _CORDIC_Z>>`[src]

`pub fn cordic_z(&mut self) -> CORDIC_Z_W<'_>`[src]

Bits 0:31 - Cordic input z

`impl W<u32, Reg<u32, _ERRSTAT>>`[src]

`pub fn overflow(&mut self) -> OVERFLOW_W<'_>`[src]

Bit 0 - overflow

`pub fn nan(&mut self) -> NAN_W<'_>`[src]

Bit 1 - nan

`pub fn fixedoverflow(&mut self) -> FIXEDOVERFLOW_W<'_>`[src]

Bit 2 - fixed_pt_overflow

`pub fn underflow(&mut self) -> UNDERFLOW_W<'_>`[src]

Bit 3 - underflow

`pub fn buserror(&mut self) -> BUSERROR_W<'_>`[src]

Bit 4 - bus_error

`impl W<u32, Reg<u32, _INTREN>>`[src]

`pub fn intr_oflow(&mut self) -> INTR_OFLOW_W<'_>`[src]

Bit 0 - 1 : Enable interrupt on Floating point overflow

`pub fn intr_nan(&mut self) -> INTR_NAN_W<'_>`[src]

Bit 1 - 1 : Enable interrupt on Floating point NaN

`pub fn intr_fixed(&mut self) -> INTR_FIXED_W<'_>`[src]

Bit 2 - 1: Enable interrupt on Fixed point Overflow

`pub fn intr_uflow(&mut self) -> INTR_UFLOW_W<'_>`[src]

Bit 3 - 1 : Enable interrupt on Subnormal truncation

`pub fn intr_berr(&mut self) -> INTR_BERR_W<'_>`[src]

Bit 4 - 1: Enable interrupt on AHBM Buss Error

`pub fn intr_comp(&mut self) -> INTR_COMP_W<'_>`[src]

Bit 7 - 1: Enable interrupt on instruction completion

`impl W<u32, Reg<u32, _EVENTEN>>`[src]

`pub fn event_oflow(&mut self) -> EVENT_OFLOW_W<'_>`[src]

Bit 0 - 1 : Enable event trigger on Floating point overflow

`pub fn event_nan(&mut self) -> EVENT_NAN_W<'_>`[src]

Bit 1 - 1 : Enable event trigger on Floating point NaN

`pub fn event_fixed(&mut self) -> EVENT_FIXED_W<'_>`[src]

Bit 2 - 1: Enable event trigger on Fixed point Overflow

`pub fn event_uflow(&mut self) -> EVENT_UFLOW_W<'_>`[src]

Bit 3 - 1 : Enable event trigger on Subnormal truncation

`pub fn event_berr(&mut self) -> EVENT_BERR_W<'_>`[src]

Bit 4 - 1: Enable event trigger on AHBM Buss Error

`pub fn event_comp(&mut self) -> EVENT_COMP_W<'_>`[src]

Bit 7 - 1: Enable event trigger on instruction completion

`impl W<u32, Reg<u32, _INTRSTAT>>`[src]

`pub fn intr_stat(&mut self) -> INTR_STAT_W<'_>`[src]

Bit 0 - Intr status ( 1 bit to indicate interrupt captured, 0 means no new interrupt), write any value will clear this bit

`impl W<u32, Reg<u32, _GPREG>>`[src]

`pub fn gpreg(&mut self) -> GPREG_W<'_>`[src]

Bits 0:31 - General purpose register bank

`impl W<u32, Reg<u32, _COMPREG>>`[src]

`pub fn compreg(&mut self) -> COMPREG_W<'_>`[src]

Bits 0:31 - Compute register bank

`impl W<u8, Reg<u8, _B0_0>>`[src]

`pub fn pbyte(&mut self) -> PBYTE_W<'_>`[src]

Bit 0 - Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package.

`impl W<u8, Reg<u8, _B0_1>>`[src]

`pub fn pbyte(&mut self) -> PBYTE_W<'_>`[src]

Bit 0 - Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package.

`impl W<u8, Reg<u8, _B0_2>>`[src]

`pub fn pbyte(&mut self) -> PBYTE_W<'_>`[src]

Bit 0 - Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package.

`impl W<u8, Reg<u8, _B0_3>>`[src]

`pub fn pbyte(&mut self) -> PBYTE_W<'_>`[src]

Bit 0 - Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package.

`impl W<u8, Reg<u8, _B0_4>>`[src]

`pub fn pbyte(&mut self) -> PBYTE_W<'_>`[src]

Bit 0 - Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package.

`impl W<u8, Reg<u8, _B0_5>>`[src]

`pub fn pbyte(&mut self) -> PBYTE_W<'_>`[src]

Bit 0 - Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package.

`impl W<u8, Reg<u8, _B0_6>>`[src]

`pub fn pbyte(&mut self) -> PBYTE_W<'_>`[src]

Bit 0 - Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package.

`impl W<u8, Reg<u8, _B0_7>>`[src]

`pub fn pbyte(&mut self) -> PBYTE_W<'_>`[src]

Bit 0 - Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package.

`impl W<u8, Reg<u8, _B0_8>>`[src]

`pub fn pbyte(&mut self) -> PBYTE_W<'_>`[src]

Bit 0 - Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package.

`impl W<u8, Reg<u8, _B0_9>>`[src]

`pub fn pbyte(&mut self) -> PBYTE_W<'_>`[src]

Bit 0 - Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package.

`impl W<u8, Reg<u8, _B0_10>>`[src]

`pub fn pbyte(&mut self) -> PBYTE_W<'_>`[src]

Bit 0 - Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package.

`impl W<u8, Reg<u8, _B0_11>>`[src]

`pub fn pbyte(&mut self) -> PBYTE_W<'_>`[src]

Bit 0 - Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package.

`impl W<u8, Reg<u8, _B0_12>>`[src]

`pub fn pbyte(&mut self) -> PBYTE_W<'_>`[src]

Bit 0 - Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package.

`impl W<u8, Reg<u8, _B0_13>>`[src]

`pub fn pbyte(&mut self) -> PBYTE_W<'_>`[src]

Bit 0 - Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package.

`impl W<u8, Reg<u8, _B0_14>>`[src]

`pub fn pbyte(&mut self) -> PBYTE_W<'_>`[src]

Bit 0 - Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package.

`impl W<u8, Reg<u8, _B0_15>>`[src]

`pub fn pbyte(&mut self) -> PBYTE_W<'_>`[src]

Bit 0 - Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package.

`impl W<u8, Reg<u8, _B0_16>>`[src]

`pub fn pbyte(&mut self) -> PBYTE_W<'_>`[src]

Bit 0 - Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package.

`impl W<u8, Reg<u8, _B0_17>>`[src]

`pub fn pbyte(&mut self) -> PBYTE_W<'_>`[src]

Bit 0 - Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package.

`impl W<u8, Reg<u8, _B0_18>>`[src]

`pub fn pbyte(&mut self) -> PBYTE_W<'_>`[src]

Bit 0 - Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package.

`impl W<u8, Reg<u8, _B0_19>>`[src]

`pub fn pbyte(&mut self) -> PBYTE_W<'_>`[src]

Bit 0 - Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package.

`impl W<u8, Reg<u8, _B0_20>>`[src]

`pub fn pbyte(&mut self) -> PBYTE_W<'_>`[src]

Bit 0 - Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package.

`impl W<u8, Reg<u8, _B0_21>>`[src]

`pub fn pbyte(&mut self) -> PBYTE_W<'_>`[src]

Bit 0 - Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package.

`impl W<u8, Reg<u8, _B0_22>>`[src]

`pub fn pbyte(&mut self) -> PBYTE_W<'_>`[src]

Bit 0 - Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package.

`impl W<u8, Reg<u8, _B0_23>>`[src]

`pub fn pbyte(&mut self) -> PBYTE_W<'_>`[src]

Bit 0 - Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package.

`impl W<u8, Reg<u8, _B0_24>>`[src]

`pub fn pbyte(&mut self) -> PBYTE_W<'_>`[src]

Bit 0 - Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package.

`impl W<u8, Reg<u8, _B0_25>>`[src]

`pub fn pbyte(&mut self) -> PBYTE_W<'_>`[src]

Bit 0 - Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package.

`impl W<u8, Reg<u8, _B0_26>>`[src]

`pub fn pbyte(&mut self) -> PBYTE_W<'_>`[src]

Bit 0 - Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package.

`impl W<u8, Reg<u8, _B0_27>>`[src]

`pub fn pbyte(&mut self) -> PBYTE_W<'_>`[src]

Bit 0 - Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package.

`impl W<u8, Reg<u8, _B0_28>>`[src]

`pub fn pbyte(&mut self) -> PBYTE_W<'_>`[src]

Bit 0 - Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package.

`impl W<u8, Reg<u8, _B0_29>>`[src]

`pub fn pbyte(&mut self) -> PBYTE_W<'_>`[src]

Bit 0 - Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package.

`impl W<u8, Reg<u8, _B0_30>>`[src]

`pub fn pbyte(&mut self) -> PBYTE_W<'_>`[src]

Bit 0 - Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package.

`impl W<u8, Reg<u8, _B0_31>>`[src]

`pub fn pbyte(&mut self) -> PBYTE_W<'_>`[src]

Bit 0 - Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package.

`impl W<u32, Reg<u32, _W0_0>>`[src]

`pub fn pword(&mut self) -> PWORD_W<'_>`[src]

Bits 0:31 - Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package.

`impl W<u32, Reg<u32, _W0_1>>`[src]

`pub fn pword(&mut self) -> PWORD_W<'_>`[src]

Bits 0:31 - Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package.

`impl W<u32, Reg<u32, _W0_2>>`[src]

`pub fn pword(&mut self) -> PWORD_W<'_>`[src]

Bits 0:31 - Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package.

`impl W<u32, Reg<u32, _W0_3>>`[src]

`pub fn pword(&mut self) -> PWORD_W<'_>`[src]

Bits 0:31 - Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package.

`impl W<u32, Reg<u32, _W0_4>>`[src]

`pub fn pword(&mut self) -> PWORD_W<'_>`[src]

Bits 0:31 - Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package.

`impl W<u32, Reg<u32, _W0_5>>`[src]

`pub fn pword(&mut self) -> PWORD_W<'_>`[src]

Bits 0:31 - Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package.

`impl W<u32, Reg<u32, _W0_6>>`[src]

`pub fn pword(&mut self) -> PWORD_W<'_>`[src]

Bits 0:31 - Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package.

`impl W<u32, Reg<u32, _W0_7>>`[src]

`pub fn pword(&mut self) -> PWORD_W<'_>`[src]

Bits 0:31 - Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package.

`impl W<u32, Reg<u32, _W0_8>>`[src]

`pub fn pword(&mut self) -> PWORD_W<'_>`[src]

Bits 0:31 - Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package.

`impl W<u32, Reg<u32, _W0_9>>`[src]

`pub fn pword(&mut self) -> PWORD_W<'_>`[src]

Bits 0:31 - Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package.

`impl W<u32, Reg<u32, _W0_10>>`[src]

`pub fn pword(&mut self) -> PWORD_W<'_>`[src]

Bits 0:31 - Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package.

`impl W<u32, Reg<u32, _W0_11>>`[src]

`pub fn pword(&mut self) -> PWORD_W<'_>`[src]

Bits 0:31 - Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package.

`impl W<u32, Reg<u32, _W0_12>>`[src]

`pub fn pword(&mut self) -> PWORD_W<'_>`[src]

Bits 0:31 - Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package.

`impl W<u32, Reg<u32, _W0_13>>`[src]

`pub fn pword(&mut self) -> PWORD_W<'_>`[src]

Bits 0:31 - Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package.

`impl W<u32, Reg<u32, _W0_14>>`[src]

`pub fn pword(&mut self) -> PWORD_W<'_>`[src]

Bits 0:31 - Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package.

`impl W<u32, Reg<u32, _W0_15>>`[src]

`pub fn pword(&mut self) -> PWORD_W<'_>`[src]

Bits 0:31 - Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package.

`impl W<u32, Reg<u32, _W0_16>>`[src]

`pub fn pword(&mut self) -> PWORD_W<'_>`[src]

Bits 0:31 - Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package.

`impl W<u32, Reg<u32, _W0_17>>`[src]

`pub fn pword(&mut self) -> PWORD_W<'_>`[src]

Bits 0:31 - Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package.

`impl W<u32, Reg<u32, _W0_18>>`[src]

`pub fn pword(&mut self) -> PWORD_W<'_>`[src]

Bits 0:31 - Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package.

`impl W<u32, Reg<u32, _W0_19>>`[src]

`pub fn pword(&mut self) -> PWORD_W<'_>`[src]

Bits 0:31 - Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package.

`impl W<u32, Reg<u32, _W0_20>>`[src]

`pub fn pword(&mut self) -> PWORD_W<'_>`[src]

Bits 0:31 - Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package.

`impl W<u32, Reg<u32, _W0_21>>`[src]

`pub fn pword(&mut self) -> PWORD_W<'_>`[src]

Bits 0:31 - Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package.

`impl W<u32, Reg<u32, _W0_22>>`[src]

`pub fn pword(&mut self) -> PWORD_W<'_>`[src]

Bits 0:31 - Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package.

`impl W<u32, Reg<u32, _W0_23>>`[src]

`pub fn pword(&mut self) -> PWORD_W<'_>`[src]

Bits 0:31 - Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package.

`impl W<u32, Reg<u32, _W0_24>>`[src]

`pub fn pword(&mut self) -> PWORD_W<'_>`[src]

Bits 0:31 - Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package.

`impl W<u32, Reg<u32, _W0_25>>`[src]

`pub fn pword(&mut self) -> PWORD_W<'_>`[src]

Bits 0:31 - Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package.

`impl W<u32, Reg<u32, _W0_26>>`[src]

`pub fn pword(&mut self) -> PWORD_W<'_>`[src]

Bits 0:31 - Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package.

`impl W<u32, Reg<u32, _W0_27>>`[src]

`pub fn pword(&mut self) -> PWORD_W<'_>`[src]

Bits 0:31 - Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package.

`impl W<u32, Reg<u32, _W0_28>>`[src]

`pub fn pword(&mut self) -> PWORD_W<'_>`[src]

Bits 0:31 - Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package.

`impl W<u32, Reg<u32, _W0_29>>`[src]

`pub fn pword(&mut self) -> PWORD_W<'_>`[src]

Bits 0:31 - Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package.

`impl W<u32, Reg<u32, _W0_30>>`[src]

`pub fn pword(&mut self) -> PWORD_W<'_>`[src]

Bits 0:31 - Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package.

`impl W<u32, Reg<u32, _W0_31>>`[src]

`pub fn pword(&mut self) -> PWORD_W<'_>`[src]

Bits 0:31 - Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package.

`impl W<u32, Reg<u32, _DIR0>>`[src]

`pub fn dirp(&mut self) -> DIRP_W<'_>`[src]

Bits 0:31 - Selects pin direction for pin PIOm_n (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on the specific device and package. 0 = input. 1 = output.

`impl W<u32, Reg<u32, _MASK0>>`[src]

`pub fn maskp(&mut self) -> MASKP_W<'_>`[src]

Bits 0:31 - Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on the specific device and package.0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected.

`impl W<u32, Reg<u32, _PIN0>>`[src]

`pub fn port(&mut self) -> PORT_W<'_>`[src]

Bits 0:31 - Reads pin states or loads output bits (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on the specific device and package. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit.

`impl W<u32, Reg<u32, _MPIN0>>`[src]

`pub fn mportp(&mut self) -> MPORTP_W<'_>`[src]

Bits 0:31 - Masked port register (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on the specific device and package. 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0.

`impl W<u32, Reg<u32, _SET0>>`[src]

`pub fn setp(&mut self) -> SETP_W<'_>`[src]

Bits 0:31 - Read or set output bits (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on the specific device and package. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit.

`impl W<u32, Reg<u32, _CLR0>>`[src]

`pub fn clrp(&mut self) -> CLRP_W<'_>`[src]

Bits 0:31 - Clear output bits (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on the specific device and package. 0 = No operation. 1 = Clear output bit.

`impl W<u32, Reg<u32, _NOT0>>`[src]

`pub fn notp(&mut self) -> NOTP_W<'_>`[src]

Bits 0:31 - Toggle output bits (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on the specific device and package. 0 = no operation. 1 = Toggle output bit.

`impl W<u32, Reg<u32, _DIRSET0>>`[src]

`pub fn dirsetp(&mut self) -> DIRSETP_W<'_>`[src]

Bits 0:31 - Set direction bits (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on the specific device and package. 0 = No operation. 1 = Set direction bit.

`impl W<u32, Reg<u32, _DIRCLR0>>`[src]

`pub fn dirclrp(&mut self) -> DIRCLRP_W<'_>`[src]

Bits 0:31 - Clear direction bits (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on the specific device and package. 0 = No operation. 1 = Clear direction bit.

`impl W<u32, Reg<u32, _DIRNOT0>>`[src]

`pub fn dirnotp(&mut self) -> DIRNOTP_W<'_>`[src]

Bits 0:31 - Toggle direction bits (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on the specific device and package. 0 = no operation. 1 = Toggle direction bit.

`impl W<u32, Reg<u32, _SEC_CTRL_FLASH_ROM_SLAVE_RULE>>`[src]

`pub fn flash_rule(&mut self) -> FLASH_RULE_W<'_>`[src]

Bits 0:1 - Security access rules for the whole FLASH : 0x0000_0000 - 0x0009_FFFF

`pub fn rom_rule(&mut self) -> ROM_RULE_W<'_>`[src]

Bits 4:5 - Security access rules for the whole ROM : 0x0300_0000 - 0x0301_FFFF

`impl W<u32, Reg<u32, _SEC_CTRL_FLASH_MEM_RULE0>>`[src]

`pub fn rule0(&mut self) -> RULE0_W<'_>`[src]

Bits 0:1 - secure control rule0. it can be set when check_reg's write_lock is '0'

`pub fn rule1(&mut self) -> RULE1_W<'_>`[src]

Bits 4:5 - secure control rule1. it can be set when check_reg's write_lock is '0'

`pub fn rule2(&mut self) -> RULE2_W<'_>`[src]

Bits 8:9 - secure control rule2. it can be set when check_reg's write_lock is '0'

`pub fn rule3(&mut self) -> RULE3_W<'_>`[src]

Bits 12:13 - secure control rule3. it can be set when check_reg's write_lock is '0'

`pub fn rule4(&mut self) -> RULE4_W<'_>`[src]

Bits 16:17 - secure control rule4. it can be set when check_reg's write_lock is '0'

`pub fn rule5(&mut self) -> RULE5_W<'_>`[src]

Bits 20:21 - secure control rule5. it can be set when check_reg's write_lock is '0'

`pub fn rule6(&mut self) -> RULE6_W<'_>`[src]

Bits 24:25 - secure control rule6. it can be set when check_reg's write_lock is '0'

`pub fn rule7(&mut self) -> RULE7_W<'_>`[src]

Bits 28:29 - secure control rule7. it can be set when check_reg's write_lock is '0'

`impl W<u32, Reg<u32, _SEC_CTRL_FLASH_MEM_RULE1>>`[src]

`pub fn rule0(&mut self) -> RULE0_W<'_>`[src]

Bits 0:1 - secure control rule0. it can be set when check_reg's write_lock is '0'

`pub fn rule1(&mut self) -> RULE1_W<'_>`[src]

Bits 4:5 - secure control rule1. it can be set when check_reg's write_lock is '0'

`pub fn rule2(&mut self) -> RULE2_W<'_>`[src]

Bits 8:9 - secure control rule2. it can be set when check_reg's write_lock is '0'

`pub fn rule3(&mut self) -> RULE3_W<'_>`[src]

Bits 12:13 - secure control rule3. it can be set when check_reg's write_lock is '0'

`pub fn rule4(&mut self) -> RULE4_W<'_>`[src]

Bits 16:17 - secure control rule4. it can be set when check_reg's write_lock is '0'

`pub fn rule5(&mut self) -> RULE5_W<'_>`[src]

Bits 20:21 - secure control rule5. it can be set when check_reg's write_lock is '0'

`pub fn rule6(&mut self) -> RULE6_W<'_>`[src]

Bits 24:25 - secure control rule6. it can be set when check_reg's write_lock is '0'

`pub fn rule7(&mut self) -> RULE7_W<'_>`[src]

Bits 28:29 - secure control rule7. it can be set when check_reg's write_lock is '0'

`impl W<u32, Reg<u32, _SEC_CTRL_FLASH_MEM_RULE2>>`[src]

`pub fn rule0(&mut self) -> RULE0_W<'_>`[src]

Bits 0:1 - secure control rule0. it can be set when check_reg's write_lock is '0'

`pub fn rule1(&mut self) -> RULE1_W<'_>`[src]

Bits 4:5 - secure control rule1. it can be set when check_reg's write_lock is '0'

`pub fn rule2(&mut self) -> RULE2_W<'_>`[src]

Bits 8:9 - secure control rule2. it can be set when check_reg's write_lock is '0'

`pub fn rule3(&mut self) -> RULE3_W<'_>`[src]

Bits 12:13 - secure control rule3. it can be set when check_reg's write_lock is '0'

`pub fn rule4(&mut self) -> RULE4_W<'_>`[src]

Bits 16:17 - secure control rule4. it can be set when check_reg's write_lock is '0'

`pub fn rule5(&mut self) -> RULE5_W<'_>`[src]

Bits 20:21 - secure control rule5. it can be set when check_reg's write_lock is '0'

`pub fn rule6(&mut self) -> RULE6_W<'_>`[src]

Bits 24:25 - secure control rule6. it can be set when check_reg's write_lock is '0'

`pub fn rule7(&mut self) -> RULE7_W<'_>`[src]

Bits 28:29 - secure control rule7. it can be set when check_reg's write_lock is '0'

`impl W<u32, Reg<u32, _SEC_CTRL_ROM_MEM_RULE0>>`[src]

`pub fn rule0(&mut self) -> RULE0_W<'_>`[src]

Bits 0:1 - secure control rule0. it can be set when check_reg's write_lock is '0'

`pub fn rule1(&mut self) -> RULE1_W<'_>`[src]

Bits 4:5 - secure control rule1. it can be set when check_reg's write_lock is '0'

`pub fn rule2(&mut self) -> RULE2_W<'_>`[src]

Bits 8:9 - secure control rule2. it can be set when check_reg's write_lock is '0'

`pub fn rule3(&mut self) -> RULE3_W<'_>`[src]

Bits 12:13 - secure control rule3. it can be set when check_reg's write_lock is '0'

`pub fn rule4(&mut self) -> RULE4_W<'_>`[src]

Bits 16:17 - secure control rule4. it can be set when check_reg's write_lock is '0'

`pub fn rule5(&mut self) -> RULE5_W<'_>`[src]

Bits 20:21 - secure control rule5. it can be set when check_reg's write_lock is '0'

`pub fn rule6(&mut self) -> RULE6_W<'_>`[src]

Bits 24:25 - secure control rule6. it can be set when check_reg's write_lock is '0'

`pub fn rule7(&mut self) -> RULE7_W<'_>`[src]

Bits 28:29 - secure control rule7. it can be set when check_reg's write_lock is '0'

`impl W<u32, Reg<u32, _SEC_CTRL_ROM_MEM_RULE1>>`[src]

`pub fn rule0(&mut self) -> RULE0_W<'_>`[src]

Bits 0:1 - secure control rule0. it can be set when check_reg's write_lock is '0'

`pub fn rule1(&mut self) -> RULE1_W<'_>`[src]

Bits 4:5 - secure control rule1. it can be set when check_reg's write_lock is '0'

`pub fn rule2(&mut self) -> RULE2_W<'_>`[src]

Bits 8:9 - secure control rule2. it can be set when check_reg's write_lock is '0'

`pub fn rule3(&mut self) -> RULE3_W<'_>`[src]

Bits 12:13 - secure control rule3. it can be set when check_reg's write_lock is '0'

`pub fn rule4(&mut self) -> RULE4_W<'_>`[src]

Bits 16:17 - secure control rule4. it can be set when check_reg's write_lock is '0'

`pub fn rule5(&mut self) -> RULE5_W<'_>`[src]

Bits 20:21 - secure control rule5. it can be set when check_reg's write_lock is '0'

`pub fn rule6(&mut self) -> RULE6_W<'_>`[src]

Bits 24:25 - secure control rule6. it can be set when check_reg's write_lock is '0'

`pub fn rule7(&mut self) -> RULE7_W<'_>`[src]

Bits 28:29 - secure control rule7. it can be set when check_reg's write_lock is '0'

`impl W<u32, Reg<u32, _SEC_CTRL_ROM_MEM_RULE2>>`[src]

`pub fn rule0(&mut self) -> RULE0_W<'_>`[src]

Bits 0:1 - secure control rule0. it can be set when check_reg's write_lock is '0'

`pub fn rule1(&mut self) -> RULE1_W<'_>`[src]

Bits 4:5 - secure control rule1. it can be set when check_reg's write_lock is '0'

`pub fn rule2(&mut self) -> RULE2_W<'_>`[src]

Bits 8:9 - secure control rule2. it can be set when check_reg's write_lock is '0'

`pub fn rule3(&mut self) -> RULE3_W<'_>`[src]

Bits 12:13 - secure control rule3. it can be set when check_reg's write_lock is '0'

`pub fn rule4(&mut self) -> RULE4_W<'_>`[src]

Bits 16:17 - secure control rule4. it can be set when check_reg's write_lock is '0'

`pub fn rule5(&mut self) -> RULE5_W<'_>`[src]

Bits 20:21 - secure control rule5. it can be set when check_reg's write_lock is '0'

`pub fn rule6(&mut self) -> RULE6_W<'_>`[src]

Bits 24:25 - secure control rule6. it can be set when check_reg's write_lock is '0'

`pub fn rule7(&mut self) -> RULE7_W<'_>`[src]

Bits 28:29 - secure control rule7. it can be set when check_reg's write_lock is '0'

`impl W<u32, Reg<u32, _SEC_CTRL_ROM_MEM_RULE3>>`[src]

`pub fn rule0(&mut self) -> RULE0_W<'_>`[src]

Bits 0:1 - secure control rule0. it can be set when check_reg's write_lock is '0'

`pub fn rule1(&mut self) -> RULE1_W<'_>`[src]

Bits 4:5 - secure control rule1. it can be set when check_reg's write_lock is '0'

`pub fn rule2(&mut self) -> RULE2_W<'_>`[src]

Bits 8:9 - secure control rule2. it can be set when check_reg's write_lock is '0'

`pub fn rule3(&mut self) -> RULE3_W<'_>`[src]

Bits 12:13 - secure control rule3. it can be set when check_reg's write_lock is '0'

`pub fn rule4(&mut self) -> RULE4_W<'_>`[src]

Bits 16:17 - secure control rule4. it can be set when check_reg's write_lock is '0'

`pub fn rule5(&mut self) -> RULE5_W<'_>`[src]

Bits 20:21 - secure control rule5. it can be set when check_reg's write_lock is '0'

`pub fn rule6(&mut self) -> RULE6_W<'_>`[src]

Bits 24:25 - secure control rule6. it can be set when check_reg's write_lock is '0'

`pub fn rule7(&mut self) -> RULE7_W<'_>`[src]

Bits 28:29 - secure control rule7. it can be set when check_reg's write_lock is '0'

`impl W<u32, Reg<u32, _SEC_CTRL_RAMX_SLAVE_RULE>>`[src]

`pub fn ramx_rule(&mut self) -> RAMX_RULE_W<'_>`[src]

Bits 0:1 - Security access rules for the whole RAMX : 0x0400_0000 - 0x0400_7FFF

`impl W<u32, Reg<u32, _SEC_CTRL_RAMX_MEM_RULE0>>`[src]

`pub fn rule0(&mut self) -> RULE0_W<'_>`[src]

Bits 0:1 - secure control rule0. it can be set when check_reg's write_lock is '0'

`pub fn rule1(&mut self) -> RULE1_W<'_>`[src]

Bits 4:5 - secure control rule1. it can be set when check_reg's write_lock is '0'

`pub fn rule2(&mut self) -> RULE2_W<'_>`[src]

Bits 8:9 - secure control rule2. it can be set when check_reg's write_lock is '0'

`pub fn rule3(&mut self) -> RULE3_W<'_>`[src]

Bits 12:13 - secure control rule3. it can be set when check_reg's write_lock is '0'

`pub fn rule4(&mut self) -> RULE4_W<'_>`[src]

Bits 16:17 - secure control rule4. it can be set when check_reg's write_lock is '0'

`pub fn rule5(&mut self) -> RULE5_W<'_>`[src]

Bits 20:21 - secure control rule5. it can be set when check_reg's write_lock is '0'

`pub fn rule6(&mut self) -> RULE6_W<'_>`[src]

Bits 24:25 - secure control rule6. it can be set when check_reg's write_lock is '0'

`pub fn rule7(&mut self) -> RULE7_W<'_>`[src]

Bits 28:29 - secure control rule7. it can be set when check_reg's write_lock is '0'

`impl W<u32, Reg<u32, _SEC_CTRL_RAM0_SLAVE_RULE>>`[src]

`pub fn ram0_rule(&mut self) -> RAM0_RULE_W<'_>`[src]

Bits 0:1 - Security access rules for the whole RAM0 : 0x2000_0000 - 0x2000_FFFF

`impl W<u32, Reg<u32, _SEC_CTRL_RAM0_MEM_RULE0>>`[src]

`pub fn rule0(&mut self) -> RULE0_W<'_>`[src]

Bits 0:1 - secure control rule0. it can be set when check_reg's write_lock is '0'

`pub fn rule1(&mut self) -> RULE1_W<'_>`[src]

Bits 4:5 - secure control rule1. it can be set when check_reg's write_lock is '0'

`pub fn rule2(&mut self) -> RULE2_W<'_>`[src]

Bits 8:9 - secure control rule2. it can be set when check_reg's write_lock is '0'

`pub fn rule3(&mut self) -> RULE3_W<'_>`[src]

Bits 12:13 - secure control rule3. it can be set when check_reg's write_lock is '0'

`pub fn rule4(&mut self) -> RULE4_W<'_>`[src]

Bits 16:17 - secure control rule4. it can be set when check_reg's write_lock is '0'

`pub fn rule5(&mut self) -> RULE5_W<'_>`[src]

Bits 20:21 - secure control rule5. it can be set when check_reg's write_lock is '0'

`pub fn rule6(&mut self) -> RULE6_W<'_>`[src]

Bits 24:25 - secure control rule6. it can be set when check_reg's write_lock is '0'

`pub fn rule7(&mut self) -> RULE7_W<'_>`[src]

Bits 28:29 - secure control rule7. it can be set when check_reg's write_lock is '0'

`impl W<u32, Reg<u32, _SEC_CTRL_RAM0_MEM_RULE1>>`[src]

`pub fn rule0(&mut self) -> RULE0_W<'_>`[src]

Bits 0:1 - secure control rule0. it can be set when check_reg's write_lock is '0'

`pub fn rule1(&mut self) -> RULE1_W<'_>`[src]

Bits 4:5 - secure control rule1. it can be set when check_reg's write_lock is '0'

`pub fn rule2(&mut self) -> RULE2_W<'_>`[src]

Bits 8:9 - secure control rule2. it can be set when check_reg's write_lock is '0'

`pub fn rule3(&mut self) -> RULE3_W<'_>`[src]

Bits 12:13 - secure control rule3. it can be set when check_reg's write_lock is '0'

`pub fn rule4(&mut self) -> RULE4_W<'_>`[src]

Bits 16:17 - secure control rule4. it can be set when check_reg's write_lock is '0'

`pub fn rule5(&mut self) -> RULE5_W<'_>`[src]

Bits 20:21 - secure control rule5. it can be set when check_reg's write_lock is '0'

`pub fn rule6(&mut self) -> RULE6_W<'_>`[src]

Bits 24:25 - secure control rule6. it can be set when check_reg's write_lock is '0'

`pub fn rule7(&mut self) -> RULE7_W<'_>`[src]

Bits 28:29 - secure control rule7. it can be set when check_reg's write_lock is '0'

`impl W<u32, Reg<u32, _SEC_CTRL_RAM1_SLAVE_RULE>>`[src]

`pub fn ram1_rule(&mut self) -> RAM1_RULE_W<'_>`[src]

Bits 0:1 - Security access rules for the whole RAM1 : 0x2001_0000 - 0x2001_FFFF" name="0

`impl W<u32, Reg<u32, _SEC_CTRL_RAM1_MEM_RULE0>>`[src]

`pub fn rule0(&mut self) -> RULE0_W<'_>`[src]

Bits 0:1 - secure control rule0. it can be set when check_reg's write_lock is '0'

`pub fn rule1(&mut self) -> RULE1_W<'_>`[src]

Bits 4:5 - secure control rule1. it can be set when check_reg's write_lock is '0'

`pub fn rule2(&mut self) -> RULE2_W<'_>`[src]

Bits 8:9 - secure control rule2. it can be set when check_reg's write_lock is '0'

`pub fn rule3(&mut self) -> RULE3_W<'_>`[src]

Bits 12:13 - secure control rule3. it can be set when check_reg's write_lock is '0'

`pub fn rule4(&mut self) -> RULE4_W<'_>`[src]

Bits 16:17 - secure control rule4. it can be set when check_reg's write_lock is '0'

`pub fn rule5(&mut self) -> RULE5_W<'_>`[src]

Bits 20:21 - secure control rule5. it can be set when check_reg's write_lock is '0'

`pub fn rule6(&mut self) -> RULE6_W<'_>`[src]

Bits 24:25 - secure control rule6. it can be set when check_reg's write_lock is '0'

`pub fn rule7(&mut self) -> RULE7_W<'_>`[src]

Bits 28:29 - secure control rule7. it can be set when check_reg's write_lock is '0'

`impl W<u32, Reg<u32, _SEC_CTRL_RAM1_MEM_RULE1>>`[src]

`pub fn rule0(&mut self) -> RULE0_W<'_>`[src]

Bits 0:1 - secure control rule0. it can be set when check_reg's write_lock is '0'

`pub fn rule1(&mut self) -> RULE1_W<'_>`[src]

Bits 4:5 - secure control rule1. it can be set when check_reg's write_lock is '0'

`pub fn rule2(&mut self) -> RULE2_W<'_>`[src]

Bits 8:9 - secure control rule2. it can be set when check_reg's write_lock is '0'

`pub fn rule3(&mut self) -> RULE3_W<'_>`[src]

Bits 12:13 - secure control rule3. it can be set when check_reg's write_lock is '0'

`pub fn rule4(&mut self) -> RULE4_W<'_>`[src]

Bits 16:17 - secure control rule4. it can be set when check_reg's write_lock is '0'

`pub fn rule5(&mut self) -> RULE5_W<'_>`[src]

Bits 20:21 - secure control rule5. it can be set when check_reg's write_lock is '0'

`pub fn rule6(&mut self) -> RULE6_W<'_>`[src]

Bits 24:25 - secure control rule6. it can be set when check_reg's write_lock is '0'

`pub fn rule7(&mut self) -> RULE7_W<'_>`[src]

Bits 28:29 - secure control rule7. it can be set when check_reg's write_lock is '0'

`impl W<u32, Reg<u32, _SEC_CTRL_RAM2_SLAVE_RULE>>`[src]

`pub fn ram2_rule(&mut self) -> RAM2_RULE_W<'_>`[src]

Bits 0:1 - Security access rules for the whole RAM2 : 0x2002_0000 - 0x2002_FFFF

`impl W<u32, Reg<u32, _SEC_CTRL_RAM2_MEM_RULE0>>`[src]

`pub fn rule0(&mut self) -> RULE0_W<'_>`[src]

Bits 0:1 - secure control rule0. it can be set when check_reg's write_lock is '0'

`pub fn rule1(&mut self) -> RULE1_W<'_>`[src]

Bits 4:5 - secure control rule1. it can be set when check_reg's write_lock is '0'

`pub fn rule2(&mut self) -> RULE2_W<'_>`[src]

Bits 8:9 - secure control rule2. it can be set when check_reg's write_lock is '0'

`pub fn rule3(&mut self) -> RULE3_W<'_>`[src]

Bits 12:13 - secure control rule3. it can be set when check_reg's write_lock is '0'

`pub fn rule4(&mut self) -> RULE4_W<'_>`[src]

Bits 16:17 - secure control rule4. it can be set when check_reg's write_lock is '0'

`pub fn rule5(&mut self) -> RULE5_W<'_>`[src]

Bits 20:21 - secure control rule5. it can be set when check_reg's write_lock is '0'

`pub fn rule6(&mut self) -> RULE6_W<'_>`[src]

Bits 24:25 - secure control rule6. it can be set when check_reg's write_lock is '0'

`pub fn rule7(&mut self) -> RULE7_W<'_>`[src]

Bits 28:29 - secure control rule7. it can be set when check_reg's write_lock is '0'

`impl W<u32, Reg<u32, _SEC_CTRL_RAM2_MEM_RULE1>>`[src]

`pub fn rule0(&mut self) -> RULE0_W<'_>`[src]

Bits 0:1 - secure control rule0. it can be set when check_reg's write_lock is '0'

`pub fn rule1(&mut self) -> RULE1_W<'_>`[src]

Bits 4:5 - secure control rule1. it can be set when check_reg's write_lock is '0'

`pub fn rule2(&mut self) -> RULE2_W<'_>`[src]

Bits 8:9 - secure control rule2. it can be set when check_reg's write_lock is '0'

`pub fn rule3(&mut self) -> RULE3_W<'_>`[src]

Bits 12:13 - secure control rule3. it can be set when check_reg's write_lock is '0'

`pub fn rule4(&mut self) -> RULE4_W<'_>`[src]

Bits 16:17 - secure control rule4. it can be set when check_reg's write_lock is '0'

`pub fn rule5(&mut self) -> RULE5_W<'_>`[src]

Bits 20:21 - secure control rule5. it can be set when check_reg's write_lock is '0'

`pub fn rule6(&mut self) -> RULE6_W<'_>`[src]

Bits 24:25 - secure control rule6. it can be set when check_reg's write_lock is '0'

`pub fn rule7(&mut self) -> RULE7_W<'_>`[src]

Bits 28:29 - secure control rule7. it can be set when check_reg's write_lock is '0'

`impl W<u32, Reg<u32, _SEC_CTRL_RAM3_SLAVE_RULE>>`[src]

`pub fn ram3_rule(&mut self) -> RAM3_RULE_W<'_>`[src]

Bits 0:1 - Security access rules for the whole RAM3: 0x2003_0000 - 0x2003_FFFF

`impl W<u32, Reg<u32, _SEC_CTRL_RAM3_MEM_RULE0>>`[src]

`pub fn rule0(&mut self) -> RULE0_W<'_>`[src]

Bits 0:1 - secure control rule0. it can be set when check_reg's write_lock is '0'

`pub fn rule1(&mut self) -> RULE1_W<'_>`[src]

Bits 4:5 - secure control rule1. it can be set when check_reg's write_lock is '0'

`pub fn rule2(&mut self) -> RULE2_W<'_>`[src]

Bits 8:9 - secure control rule2. it can be set when check_reg's write_lock is '0'

`pub fn rule3(&mut self) -> RULE3_W<'_>`[src]

Bits 12:13 - secure control rule3. it can be set when check_reg's write_lock is '0'

`pub fn rule4(&mut self) -> RULE4_W<'_>`[src]

Bits 16:17 - secure control rule4. it can be set when check_reg's write_lock is '0'

`pub fn rule5(&mut self) -> RULE5_W<'_>`[src]

Bits 20:21 - secure control rule5. it can be set when check_reg's write_lock is '0'

`pub fn rule6(&mut self) -> RULE6_W<'_>`[src]

Bits 24:25 - secure control rule6. it can be set when check_reg's write_lock is '0'

`pub fn rule7(&mut self) -> RULE7_W<'_>`[src]

Bits 28:29 - secure control rule7. it can be set when check_reg's write_lock is '0'

`impl W<u32, Reg<u32, _SEC_CTRL_RAM3_MEM_RULE1>>`[src]

`pub fn rule0(&mut self) -> RULE0_W<'_>`[src]

Bits 0:1 - secure control rule0. it can be set when check_reg's write_lock is '0'

`pub fn rule1(&mut self) -> RULE1_W<'_>`[src]

Bits 4:5 - secure control rule1. it can be set when check_reg's write_lock is '0'

`pub fn rule2(&mut self) -> RULE2_W<'_>`[src]

Bits 8:9 - secure control rule2. it can be set when check_reg's write_lock is '0'

`pub fn rule3(&mut self) -> RULE3_W<'_>`[src]

Bits 12:13 - secure control rule3. it can be set when check_reg's write_lock is '0'

`pub fn rule4(&mut self) -> RULE4_W<'_>`[src]

Bits 16:17 - secure control rule4. it can be set when check_reg's write_lock is '0'

`pub fn rule5(&mut self) -> RULE5_W<'_>`[src]

Bits 20:21 - secure control rule5. it can be set when check_reg's write_lock is '0'

`pub fn rule6(&mut self) -> RULE6_W<'_>`[src]

Bits 24:25 - secure control rule6. it can be set when check_reg's write_lock is '0'

`pub fn rule7(&mut self) -> RULE7_W<'_>`[src]

Bits 28:29 - secure control rule7. it can be set when check_reg's write_lock is '0'

`impl W<u32, Reg<u32, _SEC_CTRL_RAM4_SLAVE_RULE>>`[src]

`pub fn ram4_rule(&mut self) -> RAM4_RULE_W<'_>`[src]

Bits 0:1 - Security access rules for the whole RAM4 : 0x2004_0000 - 0x2004_3FFF

`impl W<u32, Reg<u32, _SEC_CTRL_RAM4_MEM_RULE0>>`[src]

`pub fn rule0(&mut self) -> RULE0_W<'_>`[src]

Bits 0:1 - secure control rule0. it can be set when check_reg's write_lock is '0'

`pub fn rule1(&mut self) -> RULE1_W<'_>`[src]

Bits 4:5 - secure control rule1. it can be set when check_reg's write_lock is '0'

`pub fn rule2(&mut self) -> RULE2_W<'_>`[src]

Bits 8:9 - secure control rule2. it can be set when check_reg's write_lock is '0'

`pub fn rule3(&mut self) -> RULE3_W<'_>`[src]

Bits 12:13 - secure control rule3. it can be set when check_reg's write_lock is '0'

`impl W<u32, Reg<u32, _SEC_CTRL_APB_BRIDGE_SLAVE_RULE>>`[src]

`pub fn apbbridge0_rule(&mut self) -> APBBRIDGE0_RULE_W<'_>`[src]

Bits 0:1 - Security access rules for the whole APB Bridge 0

`pub fn apbbridge1_rule(&mut self) -> APBBRIDGE1_RULE_W<'_>`[src]

Bits 4:5 - Security access rules for the whole APB Bridge 1

`impl W<u32, Reg<u32, _SEC_CTRL_APB_BRIDGE0_MEM_CTRL0>>`[src]

`pub fn syscon_rule(&mut self) -> SYSCON_RULE_W<'_>`[src]

Bits 0:1 - System Configuration

`pub fn iocon_rule(&mut self) -> IOCON_RULE_W<'_>`[src]

Bits 4:5 - I/O Configuration

`pub fn gint0_rule(&mut self) -> GINT0_RULE_W<'_>`[src]

Bits 8:9 - GPIO input Interrupt 0

`pub fn gint1_rule(&mut self) -> GINT1_RULE_W<'_>`[src]

Bits 12:13 - GPIO input Interrupt 1

`pub fn pint_rule(&mut self) -> PINT_RULE_W<'_>`[src]

Bits 16:17 - Pin Interrupt and Pattern match

`pub fn sec_pint_rule(&mut self) -> SEC_PINT_RULE_W<'_>`[src]

Bits 20:21 - Secure Pin Interrupt and Pattern match

`pub fn inputmux_rule(&mut self) -> INPUTMUX_RULE_W<'_>`[src]

Bits 24:25 - Peripheral input multiplexing

`impl W<u32, Reg<u32, _SEC_CTRL_APB_BRIDGE0_MEM_CTRL1>>`[src]

`pub fn ctimer0_rule(&mut self) -> CTIMER0_RULE_W<'_>`[src]

Bits 0:1 - Standard counter/Timer 0

`pub fn ctimer1_rule(&mut self) -> CTIMER1_RULE_W<'_>`[src]

Bits 4:5 - Standard counter/Timer 1

`pub fn wwdt_rule(&mut self) -> WWDT_RULE_W<'_>`[src]

Bits 16:17 - Windiwed wtachdog Timer

`pub fn mrt_rule(&mut self) -> MRT_RULE_W<'_>`[src]

Bits 20:21 - Multi-rate Timer

`pub fn utick_rule(&mut self) -> UTICK_RULE_W<'_>`[src]

Bits 24:25 - Micro-Timer

`impl W<u32, Reg<u32, _SEC_CTRL_APB_BRIDGE0_MEM_CTRL2>>`[src]

`pub fn anactrl_rule(&mut self) -> ANACTRL_RULE_W<'_>`[src]

Bits 12:13 - Analog Modules controller

`impl W<u32, Reg<u32, _SEC_CTRL_APB_BRIDGE1_MEM_CTRL0>>`[src]

`pub fn pmc_rule(&mut self) -> PMC_RULE_W<'_>`[src]

Bits 0:1 - Power Management Controller

`pub fn sysctrl_rule(&mut self) -> SYSCTRL_RULE_W<'_>`[src]

Bits 12:13 - System Controller

`impl W<u32, Reg<u32, _SEC_CTRL_APB_BRIDGE1_MEM_CTRL1>>`[src]

`pub fn ctimer2_rule(&mut self) -> CTIMER2_RULE_W<'_>`[src]

Bits 0:1 - Standard counter/Timer 2

`pub fn ctimer3_rule(&mut self) -> CTIMER3_RULE_W<'_>`[src]

Bits 4:5 - Standard counter/Timer 3

`pub fn ctimer4_rule(&mut self) -> CTIMER4_RULE_W<'_>`[src]

Bits 8:9 - Standard counter/Timer 4

`pub fn rtc_rule(&mut self) -> RTC_RULE_W<'_>`[src]

Bits 16:17 - Real Time Counter

`pub fn osevent_rule(&mut self) -> OSEVENT_RULE_W<'_>`[src]

Bits 20:21 - OS Event Timer

`impl W<u32, Reg<u32, _SEC_CTRL_APB_BRIDGE1_MEM_CTRL2>>`[src]

`pub fn flash_ctrl_rule(&mut self) -> FLASH_CTRL_RULE_W<'_>`[src]

Bits 16:17 - Flash Controller

`pub fn prince_rule(&mut self) -> PRINCE_RULE_W<'_>`[src]

Bits 20:21 - Prince

`impl W<u32, Reg<u32, _SEC_CTRL_APB_BRIDGE1_MEM_CTRL3>>`[src]

`pub fn usbhphy_rule(&mut self) -> USBHPHY_RULE_W<'_>`[src]

Bits 0:1 - USB High Speed Phy controller

`pub fn rng_rule(&mut self) -> RNG_RULE_W<'_>`[src]

Bits 8:9 - True Random Number Generator

`pub fn puf_rule(&mut self) -> PUF_RULE_W<'_>`[src]

Bits 12:13 - PUF

`pub fn plu_rule(&mut self) -> PLU_RULE_W<'_>`[src]

Bits 20:21 - Programmable Look-Up logic

`impl W<u32, Reg<u32, _SEC_CTRL_AHB_PORT8_SLAVE0_RULE>>`[src]

`pub fn dma0_rule(&mut self) -> DMA0_RULE_W<'_>`[src]

Bits 8:9 - DMA Controller

`pub fn fs_usb_dev_rule(&mut self) -> FS_USB_DEV_RULE_W<'_>`[src]

Bits 16:17 - USB Full-speed device

`pub fn sct_rule(&mut self) -> SCT_RULE_W<'_>`[src]

Bits 20:21 - SCTimer

`pub fn flexcomm0_rule(&mut self) -> FLEXCOMM0_RULE_W<'_>`[src]

Bits 24:25 - Flexcomm interface 0

`pub fn flexcomm1_rule(&mut self) -> FLEXCOMM1_RULE_W<'_>`[src]

Bits 28:29 - Flexcomm interface 1

`impl W<u32, Reg<u32, _SEC_CTRL_AHB_PORT8_SLAVE1_RULE>>`[src]

`pub fn flexcomm2_rule(&mut self) -> FLEXCOMM2_RULE_W<'_>`[src]

Bits 0:1 - Flexcomm interface 2

`pub fn flexcomm3_rule(&mut self) -> FLEXCOMM3_RULE_W<'_>`[src]

Bits 4:5 - Flexcomm interface 3

`pub fn flexcomm4_rule(&mut self) -> FLEXCOMM4_RULE_W<'_>`[src]

Bits 8:9 - Flexcomm interface 4

`pub fn mailbox_rule(&mut self) -> MAILBOX_RULE_W<'_>`[src]

Bits 12:13 - Inter CPU communication Mailbox

`pub fn gpio0_rule(&mut self) -> GPIO0_RULE_W<'_>`[src]

Bits 16:17 - High Speed GPIO

`impl W<u32, Reg<u32, _SEC_CTRL_AHB_PORT9_SLAVE0_RULE>>`[src]

`pub fn usb_hs_dev_rule(&mut self) -> USB_HS_DEV_RULE_W<'_>`[src]

Bits 16:17 - USB high Speed device registers

`pub fn crc_rule(&mut self) -> CRC_RULE_W<'_>`[src]

Bits 20:21 - CRC engine

`pub fn flexcomm5_rule(&mut self) -> FLEXCOMM5_RULE_W<'_>`[src]

Bits 24:25 - Flexcomm interface 5

`pub fn flexcomm6_rule(&mut self) -> FLEXCOMM6_RULE_W<'_>`[src]

Bits 28:29 - Flexcomm interface 6

`impl W<u32, Reg<u32, _SEC_CTRL_AHB_PORT9_SLAVE1_RULE>>`[src]

`pub fn flexcomm7_rule(&mut self) -> FLEXCOMM7_RULE_W<'_>`[src]

Bits 0:1 - Flexcomm interface 7

`pub fn sdio_rule(&mut self) -> SDIO_RULE_W<'_>`[src]

Bits 12:13 - SDMMC card interface

`pub fn dbg_mailbox_rule(&mut self) -> DBG_MAILBOX_RULE_W<'_>`[src]

Bits 16:17 - Debug mailbox (aka ISP-AP)

`pub fn hs_lspi_rule(&mut self) -> HS_LSPI_RULE_W<'_>`[src]

Bits 28:29 - High Speed SPI

`impl W<u32, Reg<u32, _SEC_CTRL_AHB_PORT10_SLAVE0_RULE>>`[src]

`pub fn adc_rule(&mut self) -> ADC_RULE_W<'_>`[src]

Bits 0:1 - ADC

`pub fn usb_fs_host_rule(&mut self) -> USB_FS_HOST_RULE_W<'_>`[src]

Bits 8:9 - USB Full Speed Host registers.

`pub fn usb_hs_host_rule(&mut self) -> USB_HS_HOST_RULE_W<'_>`[src]

Bits 12:13 - USB High speed host registers

`pub fn hash_rule(&mut self) -> HASH_RULE_W<'_>`[src]

Bits 16:17 - SHA-2 crypto registers

`pub fn casper_rule(&mut self) -> CASPER_RULE_W<'_>`[src]

Bits 20:21 - RSA/ECC crypto accelerator

`pub fn pq_rule(&mut self) -> PQ_RULE_W<'_>`[src]

Bits 24:25 - Power Quad (CPU0 processor hardware accelerator)

`pub fn dma1_rule(&mut self) -> DMA1_RULE_W<'_>`[src]

Bits 28:29 - DMA Controller (Secure)

`impl W<u32, Reg<u32, _SEC_CTRL_AHB_PORT10_SLAVE1_RULE>>`[src]

`pub fn gpio1_rule(&mut self) -> GPIO1_RULE_W<'_>`[src]

Bits 0:1 - Secure High Speed GPIO

`pub fn ahb_sec_ctrl_rule(&mut self) -> AHB_SEC_CTRL_RULE_W<'_>`[src]

Bits 4:5 - AHB Secure Controller

`impl W<u32, Reg<u32, _SEC_CTRL_AHB_SEC_CTRL_MEM_RULE>>`[src]

`pub fn ahb_sec_ctrl_sect_0_rule(&mut self) -> AHB_SEC_CTRL_SECT_0_RULE_W<'_>`[src]

Bits 0:1 - Address space: 0x400A_0000 - 0x400A_CFFF

`pub fn ahb_sec_ctrl_sect_1_rule(&mut self) -> AHB_SEC_CTRL_SECT_1_RULE_W<'_>`[src]

Bits 4:5 - Address space: 0x400A_D000 - 0x400A_DFFF

`pub fn ahb_sec_ctrl_sect_2_rule(&mut self) -> AHB_SEC_CTRL_SECT_2_RULE_W<'_>`[src]

Bits 8:9 - Address space: 0x400A_E000 - 0x400A_EFFF

`pub fn ahb_sec_ctrl_sect_3_rule(&mut self) -> AHB_SEC_CTRL_SECT_3_RULE_W<'_>`[src]

Bits 12:13 - Address space: 0x400A_F000 - 0x400A_FFFF

`impl W<u32, Reg<u32, _SEC_CTRL_USB_HS_SLAVE_RULE>>`[src]

`pub fn ram_usb_hs_rule(&mut self) -> RAM_USB_HS_RULE_W<'_>`[src]

Bits 0:1 - Security access rules for the whole USB High Speed RAM : 0x4010_0000 - 0x4010_3FFF

`impl W<u32, Reg<u32, _SEC_CTRL_USB_HS_MEM_RULE>>`[src]

`pub fn sram_sect_0_rule(&mut self) -> SRAM_SECT_0_RULE_W<'_>`[src]

Bits 0:1 - Address space: 0x4010_0000 - 0x4010_0FFF

`pub fn sram_sect_1_rule(&mut self) -> SRAM_SECT_1_RULE_W<'_>`[src]

Bits 4:5 - Address space: 0x4010_1000 - 0x4010_1FFF

`pub fn sram_sect_2_rule(&mut self) -> SRAM_SECT_2_RULE_W<'_>`[src]

Bits 8:9 - Address space: 0x4010_2000 - 0x4010_2FFF

`pub fn sram_sect_3_rule(&mut self) -> SRAM_SECT_3_RULE_W<'_>`[src]

Bits 12:13 - Address space: 0x4010_3000 - 0x4010_3FFF

`impl W<u32, Reg<u32, _SEC_VIO_INFO_VALID>>`[src]

`pub fn vio_info_valid0(&mut self) -> VIO_INFO_VALID0_W<'_>`[src]

Bit 0 - violation information valid flag for AHB port 0. Write 1 to clear.

`pub fn vio_info_valid1(&mut self) -> VIO_INFO_VALID1_W<'_>`[src]

Bit 1 - violation information valid flag for AHB port 1. Write 1 to clear.

`pub fn vio_info_valid2(&mut self) -> VIO_INFO_VALID2_W<'_>`[src]

Bit 2 - violation information valid flag for AHB port 2. Write 1 to clear.

`pub fn vio_info_valid3(&mut self) -> VIO_INFO_VALID3_W<'_>`[src]

Bit 3 - violation information valid flag for AHB port 3. Write 1 to clear.

`pub fn vio_info_valid4(&mut self) -> VIO_INFO_VALID4_W<'_>`[src]

Bit 4 - violation information valid flag for AHB port 4. Write 1 to clear.

`pub fn vio_info_valid5(&mut self) -> VIO_INFO_VALID5_W<'_>`[src]

Bit 5 - violation information valid flag for AHB port 5. Write 1 to clear.

`pub fn vio_info_valid6(&mut self) -> VIO_INFO_VALID6_W<'_>`[src]

Bit 6 - violation information valid flag for AHB port 6. Write 1 to clear.

`pub fn vio_info_valid7(&mut self) -> VIO_INFO_VALID7_W<'_>`[src]

Bit 7 - violation information valid flag for AHB port 7. Write 1 to clear.

`pub fn vio_info_valid8(&mut self) -> VIO_INFO_VALID8_W<'_>`[src]

Bit 8 - violation information valid flag for AHB port 8. Write 1 to clear.

`pub fn vio_info_valid9(&mut self) -> VIO_INFO_VALID9_W<'_>`[src]

Bit 9 - violation information valid flag for AHB port 9. Write 1 to clear.

`pub fn vio_info_valid10(&mut self) -> VIO_INFO_VALID10_W<'_>`[src]

Bit 10 - violation information valid flag for AHB port 10. Write 1 to clear.

`pub fn vio_info_valid11(&mut self) -> VIO_INFO_VALID11_W<'_>`[src]

Bit 11 - violation information valid flag for AHB port 11. Write 1 to clear.

`impl W<u32, Reg<u32, _SEC_GPIO_MASK0>>`[src]

`pub fn pio0_pin0_sec_mask(&mut self) -> PIO0_PIN0_SEC_MASK_W<'_>`[src]

Bit 0 - Secure mask for pin P0_0

`pub fn pio0_pin1_sec_mask(&mut self) -> PIO0_PIN1_SEC_MASK_W<'_>`[src]

Bit 1 - Secure mask for pin P0_1

`pub fn pio0_pin2_sec_mask(&mut self) -> PIO0_PIN2_SEC_MASK_W<'_>`[src]

Bit 2 - Secure mask for pin P0_2

`pub fn pio0_pin3_sec_mask(&mut self) -> PIO0_PIN3_SEC_MASK_W<'_>`[src]

Bit 3 - Secure mask for pin P0_3

`pub fn pio0_pin4_sec_mask(&mut self) -> PIO0_PIN4_SEC_MASK_W<'_>`[src]

Bit 4 - Secure mask for pin P0_4

`pub fn pio0_pin5_sec_mask(&mut self) -> PIO0_PIN5_SEC_MASK_W<'_>`[src]

Bit 5 - Secure mask for pin P0_5

`pub fn pio0_pin6_sec_mask(&mut self) -> PIO0_PIN6_SEC_MASK_W<'_>`[src]

Bit 6 - Secure mask for pin P0_6

`pub fn pio0_pin7_sec_mask(&mut self) -> PIO0_PIN7_SEC_MASK_W<'_>`[src]

Bit 7 - Secure mask for pin P0_7

`pub fn pio0_pin8_sec_mask(&mut self) -> PIO0_PIN8_SEC_MASK_W<'_>`[src]

Bit 8 - Secure mask for pin P0_8

`pub fn pio0_pin9_sec_mask(&mut self) -> PIO0_PIN9_SEC_MASK_W<'_>`[src]

Bit 9 - Secure mask for pin P0_9

`pub fn pio0_pin10_sec_mask(&mut self) -> PIO0_PIN10_SEC_MASK_W<'_>`[src]

Bit 10 - Secure mask for pin P0_10

`pub fn pio0_pin11_sec_mask(&mut self) -> PIO0_PIN11_SEC_MASK_W<'_>`[src]

Bit 11 - Secure mask for pin P0_11

`pub fn pio0_pin12_sec_mask(&mut self) -> PIO0_PIN12_SEC_MASK_W<'_>`[src]

Bit 12 - Secure mask for pin P0_12

`pub fn pio0_pin13_sec_mask(&mut self) -> PIO0_PIN13_SEC_MASK_W<'_>`[src]

Bit 13 - Secure mask for pin P0_13

`pub fn pio0_pin14_sec_mask(&mut self) -> PIO0_PIN14_SEC_MASK_W<'_>`[src]

Bit 14 - Secure mask for pin P0_14

`pub fn pio0_pin15_sec_mask(&mut self) -> PIO0_PIN15_SEC_MASK_W<'_>`[src]

Bit 15 - Secure mask for pin P0_15

`pub fn pio0_pin16_sec_mask(&mut self) -> PIO0_PIN16_SEC_MASK_W<'_>`[src]

Bit 16 - Secure mask for pin P0_16

`pub fn pio0_pin17_sec_mask(&mut self) -> PIO0_PIN17_SEC_MASK_W<'_>`[src]

Bit 17 - Secure mask for pin P0_17

`pub fn pio0_pin18_sec_mask(&mut self) -> PIO0_PIN18_SEC_MASK_W<'_>`[src]

Bit 18 - Secure mask for pin P0_18

`pub fn pio0_pin19_sec_mask(&mut self) -> PIO0_PIN19_SEC_MASK_W<'_>`[src]

Bit 19 - Secure mask for pin P0_19

`pub fn pio0_pin20_sec_mask(&mut self) -> PIO0_PIN20_SEC_MASK_W<'_>`[src]

Bit 20 - Secure mask for pin P0_20

`pub fn pio0_pin21_sec_mask(&mut self) -> PIO0_PIN21_SEC_MASK_W<'_>`[src]

Bit 21 - Secure mask for pin P0_21

`pub fn pio0_pin22_sec_mask(&mut self) -> PIO0_PIN22_SEC_MASK_W<'_>`[src]

Bit 22 - Secure mask for pin P0_22

`pub fn pio0_pin23_sec_mask(&mut self) -> PIO0_PIN23_SEC_MASK_W<'_>`[src]

Bit 23 - Secure mask for pin P0_23

`pub fn pio0_pin24_sec_mask(&mut self) -> PIO0_PIN24_SEC_MASK_W<'_>`[src]

Bit 24 - Secure mask for pin P0_24

`pub fn pio0_pin25_sec_mask(&mut self) -> PIO0_PIN25_SEC_MASK_W<'_>`[src]

Bit 25 - Secure mask for pin P0_25

`pub fn pio0_pin26_sec_mask(&mut self) -> PIO0_PIN26_SEC_MASK_W<'_>`[src]

Bit 26 - Secure mask for pin P0_26

`pub fn pio0_pin27_sec_mask(&mut self) -> PIO0_PIN27_SEC_MASK_W<'_>`[src]

Bit 27 - Secure mask for pin P0_27

`pub fn pio0_pin28_sec_mask(&mut self) -> PIO0_PIN28_SEC_MASK_W<'_>`[src]

Bit 28 - Secure mask for pin P0_28

`pub fn pio0_pin29_sec_mask(&mut self) -> PIO0_PIN29_SEC_MASK_W<'_>`[src]

Bit 29 - Secure mask for pin P0_29

`pub fn pio0_pin30_sec_mask(&mut self) -> PIO0_PIN30_SEC_MASK_W<'_>`[src]

Bit 30 - Secure mask for pin P0_30

`pub fn pio0_pin31_sec_mask(&mut self) -> PIO0_PIN31_SEC_MASK_W<'_>`[src]

Bit 31 - Secure mask for pin P0_31

`impl W<u32, Reg<u32, _SEC_GPIO_MASK1>>`[src]

`pub fn pio1_pin0_sec_mask(&mut self) -> PIO1_PIN0_SEC_MASK_W<'_>`[src]

Bit 0 - Secure mask for pin P1_0

`pub fn pio1_pin1_sec_mask(&mut self) -> PIO1_PIN1_SEC_MASK_W<'_>`[src]

Bit 1 - Secure mask for pin P1_1

`pub fn pio1_pin2_sec_mask(&mut self) -> PIO1_PIN2_SEC_MASK_W<'_>`[src]

Bit 2 - Secure mask for pin P1_2

`pub fn pio1_pin3_sec_mask(&mut self) -> PIO1_PIN3_SEC_MASK_W<'_>`[src]

Bit 3 - Secure mask for pin P1_3

`pub fn pio1_pin4_sec_mask(&mut self) -> PIO1_PIN4_SEC_MASK_W<'_>`[src]

Bit 4 - Secure mask for pin P1_4

`pub fn pio1_pin5_sec_mask(&mut self) -> PIO1_PIN5_SEC_MASK_W<'_>`[src]

Bit 5 - Secure mask for pin P1_5

`pub fn pio1_pin6_sec_mask(&mut self) -> PIO1_PIN6_SEC_MASK_W<'_>`[src]

Bit 6 - Secure mask for pin P1_6

`pub fn pio1_pin7_sec_mask(&mut self) -> PIO1_PIN7_SEC_MASK_W<'_>`[src]

Bit 7 - Secure mask for pin P1_7

`pub fn pio1_pin8_sec_mask(&mut self) -> PIO1_PIN8_SEC_MASK_W<'_>`[src]

Bit 8 - Secure mask for pin P1_8

`pub fn pio1_pin9_sec_mask(&mut self) -> PIO1_PIN9_SEC_MASK_W<'_>`[src]

Bit 9 - Secure mask for pin P1_9

`pub fn pio1_pin10_sec_mask(&mut self) -> PIO1_PIN10_SEC_MASK_W<'_>`[src]

Bit 10 - Secure mask for pin P1_10

`pub fn pio1_pin11_sec_mask(&mut self) -> PIO1_PIN11_SEC_MASK_W<'_>`[src]

Bit 11 - Secure mask for pin P1_11

`pub fn pio1_pin12_sec_mask(&mut self) -> PIO1_PIN12_SEC_MASK_W<'_>`[src]

Bit 12 - Secure mask for pin P1_12

`pub fn pio1_pin13_sec_mask(&mut self) -> PIO1_PIN13_SEC_MASK_W<'_>`[src]

Bit 13 - Secure mask for pin P1_13

`pub fn pio1_pin14_sec_mask(&mut self) -> PIO1_PIN14_SEC_MASK_W<'_>`[src]

Bit 14 - Secure mask for pin P1_14

`pub fn pio1_pin15_sec_mask(&mut self) -> PIO1_PIN15_SEC_MASK_W<'_>`[src]

Bit 15 - Secure mask for pin P1_15

`pub fn pio1_pin16_sec_mask(&mut self) -> PIO1_PIN16_SEC_MASK_W<'_>`[src]

Bit 16 - Secure mask for pin P1_16

`pub fn pio1_pin17_sec_mask(&mut self) -> PIO1_PIN17_SEC_MASK_W<'_>`[src]

Bit 17 - Secure mask for pin P1_17

`pub fn pio1_pin18_sec_mask(&mut self) -> PIO1_PIN18_SEC_MASK_W<'_>`[src]

Bit 18 - Secure mask for pin P1_18

`pub fn pio1_pin19_sec_mask(&mut self) -> PIO1_PIN19_SEC_MASK_W<'_>`[src]

Bit 19 - Secure mask for pin P1_19

`pub fn pio1_pin20_sec_mask(&mut self) -> PIO1_PIN20_SEC_MASK_W<'_>`[src]

Bit 20 - Secure mask for pin P1_20

`pub fn pio1_pin21_sec_mask(&mut self) -> PIO1_PIN21_SEC_MASK_W<'_>`[src]

Bit 21 - Secure mask for pin P1_21

`pub fn pio1_pin22_sec_mask(&mut self) -> PIO1_PIN22_SEC_MASK_W<'_>`[src]

Bit 22 - Secure mask for pin P1_22

`pub fn pio1_pin23_sec_mask(&mut self) -> PIO1_PIN23_SEC_MASK_W<'_>`[src]

Bit 23 - Secure mask for pin P1_23

`pub fn pio1_pin24_sec_mask(&mut self) -> PIO1_PIN24_SEC_MASK_W<'_>`[src]

Bit 24 - Secure mask for pin P1_24

`pub fn pio1_pin25_sec_mask(&mut self) -> PIO1_PIN25_SEC_MASK_W<'_>`[src]

Bit 25 - Secure mask for pin P1_25

`pub fn pio1_pin26_sec_mask(&mut self) -> PIO1_PIN26_SEC_MASK_W<'_>`[src]

Bit 26 - Secure mask for pin P1_26

`pub fn pio1_pin27_sec_mask(&mut self) -> PIO1_PIN27_SEC_MASK_W<'_>`[src]

Bit 27 - Secure mask for pin P1_27

`pub fn pio1_pin28_sec_mask(&mut self) -> PIO1_PIN28_SEC_MASK_W<'_>`[src]

Bit 28 - Secure mask for pin P1_28

`pub fn pio1_pin29_sec_mask(&mut self) -> PIO1_PIN29_SEC_MASK_W<'_>`[src]

Bit 29 - Secure mask for pin P1_29

`pub fn pio1_pin30_sec_mask(&mut self) -> PIO1_PIN30_SEC_MASK_W<'_>`[src]

Bit 30 - Secure mask for pin P1_30

`pub fn pio1_pin31_sec_mask(&mut self) -> PIO1_PIN31_SEC_MASK_W<'_>`[src]

Bit 31 - Secure mask for pin P1_31

`impl W<u32, Reg<u32, _SEC_CPU_INT_MASK0>>`[src]

`pub fn sys_irq(&mut self) -> SYS_IRQ_W<'_>`[src]

Bit 0 - Watchdog Timer, Brown Out Detectors and Flash Controller interrupts

`pub fn sdma0_irq(&mut self) -> SDMA0_IRQ_W<'_>`[src]

Bit 1 - System DMA 0 (non-secure) interrupt.

`pub fn gpio_globalint0_irq(&mut self) -> GPIO_GLOBALINT0_IRQ_W<'_>`[src]

Bit 2 - GPIO Group 0 interrupt.

`pub fn gpio_globalint1_irq(&mut self) -> GPIO_GLOBALINT1_IRQ_W<'_>`[src]

Bit 3 - GPIO Group 1 interrupt.

`pub fn gpio_int0_irq0(&mut self) -> GPIO_INT0_IRQ0_W<'_>`[src]

Bit 4 - Pin interrupt 0 or pattern match engine slice 0 interrupt.

`pub fn gpio_int0_irq1(&mut self) -> GPIO_INT0_IRQ1_W<'_>`[src]

Bit 5 - Pin interrupt 1 or pattern match engine slice 1 interrupt.

`pub fn gpio_int0_irq2(&mut self) -> GPIO_INT0_IRQ2_W<'_>`[src]

Bit 6 - Pin interrupt 2 or pattern match engine slice 2 interrupt.

`pub fn gpio_int0_irq3(&mut self) -> GPIO_INT0_IRQ3_W<'_>`[src]

Bit 7 - Pin interrupt 3 or pattern match engine slice 3 interrupt.

`pub fn utick_irq(&mut self) -> UTICK_IRQ_W<'_>`[src]

Bit 8 - Micro Tick Timer interrupt.

`pub fn mrt_irq(&mut self) -> MRT_IRQ_W<'_>`[src]

Bit 9 - Multi-Rate Timer interrupt.

`pub fn ctimer0_irq(&mut self) -> CTIMER0_IRQ_W<'_>`[src]

Bit 10 - Standard counter/timer 0 interrupt.

`pub fn ctimer1_irq(&mut self) -> CTIMER1_IRQ_W<'_>`[src]

Bit 11 - Standard counter/timer 1 interrupt.

`pub fn sct_irq(&mut self) -> SCT_IRQ_W<'_>`[src]

Bit 12 - SCTimer/PWM interrupt.

`pub fn ctimer3_irq(&mut self) -> CTIMER3_IRQ_W<'_>`[src]

Bit 13 - Standard counter/timer 3 interrupt.

`pub fn flexcomm0_irq(&mut self) -> FLEXCOMM0_IRQ_W<'_>`[src]

Bit 14 - Flexcomm 0 interrupt (USART, SPI, I2C, I2S).

`pub fn flexcomm1_irq(&mut self) -> FLEXCOMM1_IRQ_W<'_>`[src]

Bit 15 - Flexcomm 1 interrupt (USART, SPI, I2C, I2S).

`pub fn flexcomm2_irq(&mut self) -> FLEXCOMM2_IRQ_W<'_>`[src]

Bit 16 - Flexcomm 2 interrupt (USART, SPI, I2C, I2S).

`pub fn flexcomm3_irq(&mut self) -> FLEXCOMM3_IRQ_W<'_>`[src]

Bit 17 - Flexcomm 3 interrupt (USART, SPI, I2C, I2S).

`pub fn flexcomm4_irq(&mut self) -> FLEXCOMM4_IRQ_W<'_>`[src]

Bit 18 - Flexcomm 4 interrupt (USART, SPI, I2C, I2S).

`pub fn flexcomm5_irq(&mut self) -> FLEXCOMM5_IRQ_W<'_>`[src]

Bit 19 - Flexcomm 5 interrupt (USART, SPI, I2C, I2S).

`pub fn flexcomm6_irq(&mut self) -> FLEXCOMM6_IRQ_W<'_>`[src]

Bit 20 - Flexcomm 6 interrupt (USART, SPI, I2C, I2S).

`pub fn flexcomm7_irq(&mut self) -> FLEXCOMM7_IRQ_W<'_>`[src]

Bit 21 - Flexcomm 7 interrupt (USART, SPI, I2C, I2S).

`pub fn adc_irq(&mut self) -> ADC_IRQ_W<'_>`[src]

Bit 22 - General Purpose ADC interrupt.

`pub fn reserved0(&mut self) -> RESERVED0_W<'_>`[src]

Bit 23 - Reserved. Read value is undefined, only zero should be written.

`pub fn acmp_irq(&mut self) -> ACMP_IRQ_W<'_>`[src]

Bit 24 - Analog Comparator interrupt.

`pub fn reserved1(&mut self) -> RESERVED1_W<'_>`[src]

Bit 25 - Reserved. Read value is undefined, only zero should be written.

`pub fn reserved2(&mut self) -> RESERVED2_W<'_>`[src]

Bit 26 - Reserved. Read value is undefined, only zero should be written.

`pub fn usb0_needclk(&mut self) -> USB0_NEEDCLK_W<'_>`[src]

Bit 27 - USB Full Speed Controller Clock request interrupt.

`pub fn usb0_irq(&mut self) -> USB0_IRQ_W<'_>`[src]

Bit 28 - USB Full Speed Controller interrupt.

`pub fn rtc_irq(&mut self) -> RTC_IRQ_W<'_>`[src]

Bit 29 - RTC_LITE0_ALARM_IRQ, RTC_LITE0_WAKEUP_IRQ

`pub fn reserved3(&mut self) -> RESERVED3_W<'_>`[src]

Bit 30 - Reserved. Read value is undefined, only zero should be written.

`pub fn mailbox_irq(&mut self) -> MAILBOX_IRQ_W<'_>`[src]

Bit 31 - Mailbox interrupt.

`impl W<u32, Reg<u32, _SEC_CPU_INT_MASK1>>`[src]

`pub fn gpio_int0_irq4(&mut self) -> GPIO_INT0_IRQ4_W<'_>`[src]

Bit 0 - Pin interrupt 4 or pattern match engine slice 4 interrupt.

`pub fn gpio_int0_irq5(&mut self) -> GPIO_INT0_IRQ5_W<'_>`[src]

Bit 1 - Pin interrupt 5 or pattern match engine slice 5 interrupt.

`pub fn gpio_int0_irq6(&mut self) -> GPIO_INT0_IRQ6_W<'_>`[src]

Bit 2 - Pin interrupt 6 or pattern match engine slice 6 interrupt.

`pub fn gpio_int0_irq7(&mut self) -> GPIO_INT0_IRQ7_W<'_>`[src]

Bit 3 - Pin interrupt 7 or pattern match engine slice 7 interrupt.

`pub fn ctimer2_irq(&mut self) -> CTIMER2_IRQ_W<'_>`[src]

Bit 4 - Standard counter/timer 2 interrupt.

`pub fn ctimer4_irq(&mut self) -> CTIMER4_IRQ_W<'_>`[src]

Bit 5 - Standard counter/timer 4 interrupt.

`pub fn os_event_timer_irq(&mut self) -> OS_EVENT_TIMER_IRQ_W<'_>`[src]

Bit 6 - OS Event Timer and OS Event Timer Wakeup interrupts

`pub fn reserved0(&mut self) -> RESERVED0_W<'_>`[src]

Bit 7 - Reserved. Read value is undefined, only zero should be written.

`pub fn reserved1(&mut self) -> RESERVED1_W<'_>`[src]

Bit 8 - Reserved. Read value is undefined, only zero should be written.

`pub fn reserved2(&mut self) -> RESERVED2_W<'_>`[src]

Bit 9 - Reserved. Read value is undefined, only zero should be written.

`pub fn sdio_irq(&mut self) -> SDIO_IRQ_W<'_>`[src]

Bit 10 - SDIO Controller interrupt.

`pub fn reserved3(&mut self) -> RESERVED3_W<'_>`[src]

Bit 11 - Reserved. Read value is undefined, only zero should be written.

`pub fn reserved4(&mut self) -> RESERVED4_W<'_>`[src]

Bit 12 - Reserved. Read value is undefined, only zero should be written.

`pub fn reserved5(&mut self) -> RESERVED5_W<'_>`[src]

Bit 13 - Reserved. Read value is undefined, only zero should be written.

`pub fn usb1_phy_irq(&mut self) -> USB1_PHY_IRQ_W<'_>`[src]

Bit 14 - USB High Speed PHY Controller interrupt.

`pub fn usb1_irq(&mut self) -> USB1_IRQ_W<'_>`[src]

Bit 15 - USB High Speed Controller interrupt.

`pub fn usb1_needclk(&mut self) -> USB1_NEEDCLK_W<'_>`[src]

Bit 16 - USB High Speed Controller Clock request interrupt.

`pub fn sec_hypervisor_call_irq(&mut self) -> SEC_HYPERVISOR_CALL_IRQ_W<'_>`[src]

Bit 17 - Secure fault Hyper Visor call interrupt.

`pub fn sec_gpio_int0_irq0(&mut self) -> SEC_GPIO_INT0_IRQ0_W<'_>`[src]

Bit 18 - Secure Pin interrupt 0 or pattern match engine slice 0 interrupt.

`pub fn sec_gpio_int0_irq1(&mut self) -> SEC_GPIO_INT0_IRQ1_W<'_>`[src]

Bit 19 - Secure Pin interrupt 1 or pattern match engine slice 1 interrupt.

`pub fn plu_irq(&mut self) -> PLU_IRQ_W<'_>`[src]

Bit 20 - Programmable Look-Up Controller interrupt.

`pub fn sec_vio_irq(&mut self) -> SEC_VIO_IRQ_W<'_>`[src]

Bit 21 - Security Violation interrupt.

`pub fn sha_irq(&mut self) -> SHA_IRQ_W<'_>`[src]

Bit 22 - HASH-AES interrupt.

`pub fn casper_irq(&mut self) -> CASPER_IRQ_W<'_>`[src]

Bit 23 - CASPER interrupt.

`pub fn pufkey_irq(&mut self) -> PUFKEY_IRQ_W<'_>`[src]

Bit 24 - PUF interrupt.

`pub fn pq_irq(&mut self) -> PQ_IRQ_W<'_>`[src]

Bit 25 - Power Quad interrupt.

`pub fn sdma1_irq(&mut self) -> SDMA1_IRQ_W<'_>`[src]

Bit 26 - System DMA 1 (Secure) interrupt

`pub fn lspi_hs_irq(&mut self) -> LSPI_HS_IRQ_W<'_>`[src]

Bit 27 - High Speed SPI interrupt

`impl W<u32, Reg<u32, _SEC_MASK_LOCK>>`[src]

`pub fn sec_gpio_mask0_lock(&mut self) -> SEC_GPIO_MASK0_LOCK_W<'_>`[src]

Bits 0:1 - SEC_GPIO_MASK0 register write-lock.

`pub fn sec_gpio_mask1_lock(&mut self) -> SEC_GPIO_MASK1_LOCK_W<'_>`[src]

Bits 2:3 - SEC_GPIO_MASK1 register write-lock.

`pub fn sec_cpu1_int_mask0_lock(&mut self) -> SEC_CPU1_INT_MASK0_LOCK_W<'_>`[src]

Bits 8:9 - SEC_CPU_INT_MASK0 register write-lock.

`pub fn sec_cpu1_int_mask1_lock(&mut self) -> SEC_CPU1_INT_MASK1_LOCK_W<'_>`[src]

Bits 10:11 - SEC_CPU_INT_MASK1 register write-lock.

`impl W<u32, Reg<u32, _MASTER_SEC_LEVEL>>`[src]

`pub fn cpu1c(&mut self) -> CPU1C_W<'_>`[src]

Bits 4:5 - Micro-Cortex M33 (CPU1) Code bus.

`pub fn cpu1s(&mut self) -> CPU1S_W<'_>`[src]

Bits 6:7 - Micro-Cortex M33 (CPU1) System bus.

`pub fn usbfsd(&mut self) -> USBFSD_W<'_>`[src]

Bits 8:9 - USB Full Speed Device.

`pub fn sdma0(&mut self) -> SDMA0_W<'_>`[src]

Bits 10:11 - System DMA 0.

`pub fn sdio(&mut self) -> SDIO_W<'_>`[src]

Bits 16:17 - SDIO.

`pub fn pq(&mut self) -> PQ_W<'_>`[src]

Bits 18:19 - Power Quad.

`pub fn hash(&mut self) -> HASH_W<'_>`[src]

Bits 20:21 - Hash.

`pub fn usbfsh(&mut self) -> USBFSH_W<'_>`[src]

Bits 22:23 - USB Full speed Host.

`pub fn sdma1(&mut self) -> SDMA1_W<'_>`[src]

Bits 24:25 - System DMA 1 security level.

`pub fn master_sec_level_lock(&mut self) -> MASTER_SEC_LEVEL_LOCK_W<'_>`[src]

Bits 30:31 - MASTER_SEC_LEVEL write-lock.

`impl W<u32, Reg<u32, _MASTER_SEC_ANTI_POL_REG>>`[src]

`pub fn cpu1c(&mut self) -> CPU1C_W<'_>`[src]

Bits 4:5 - Micro-Cortex M33 (CPU1) Code bus. Must be equal to NOT(MASTER_SEC_LEVEL.CPU1C)

`pub fn cpu1s(&mut self) -> CPU1S_W<'_>`[src]

Bits 6:7 - Micro-Cortex M33 (CPU1) System bus. Must be equal to NOT(MASTER_SEC_LEVEL.CPU1S)

`pub fn usbfsd(&mut self) -> USBFSD_W<'_>`[src]

Bits 8:9 - USB Full Speed Device. Must be equal to NOT(MASTER_SEC_LEVEL.USBFSD)

`pub fn sdma0(&mut self) -> SDMA0_W<'_>`[src]

Bits 10:11 - System DMA 0. Must be equal to NOT(MASTER_SEC_LEVEL.SDMA0)

`pub fn sdio(&mut self) -> SDIO_W<'_>`[src]

Bits 16:17 - SDIO. Must be equal to NOT(MASTER_SEC_LEVEL.SDIO)

`pub fn pq(&mut self) -> PQ_W<'_>`[src]

Bits 18:19 - Power Quad. Must be equal to NOT(MASTER_SEC_LEVEL.PQ)

`pub fn hash(&mut self) -> HASH_W<'_>`[src]

Bits 20:21 - Hash. Must be equal to NOT(MASTER_SEC_LEVEL.HASH)

`pub fn usbfsh(&mut self) -> USBFSH_W<'_>`[src]

Bits 22:23 - USB Full speed Host. Must be equal to NOT(MASTER_SEC_LEVEL.USBFSH)

`pub fn sdma1(&mut self) -> SDMA1_W<'_>`[src]

Bits 24:25 - System DMA 1 security level. Must be equal to NOT(MASTER_SEC_LEVEL.SDMA1)

`pub fn master_sec_level_antipol_lock( &mut self ) -> MASTER_SEC_LEVEL_ANTIPOL_LOCK_W<'_>`[src]

Bits 30:31 - MASTER_SEC_ANTI_POL_REG register write-lock.

`impl W<u32, Reg<u32, _CPU0_LOCK_REG>>`[src]

`pub fn lock_ns_vtor(&mut self) -> LOCK_NS_VTOR_W<'_>`[src]

Bits 0:1 - Cortex M33 (CPU0) VTOR_NS register write-lock.

`pub fn lock_ns_mpu(&mut self) -> LOCK_NS_MPU_W<'_>`[src]

Bits 2:3 - Cortex M33 (CPU0) non-secure MPU register write-lock.

`pub fn lock_s_vtaircr(&mut self) -> LOCK_S_VTAIRCR_W<'_>`[src]

Bits 4:5 - Cortex M33 (CPU0) VTOR_S, AIRCR.PRIS, IRCR.BFHFNMINS registers write-lock.

`pub fn lock_s_mpu(&mut self) -> LOCK_S_MPU_W<'_>`[src]

Bits 6:7 - Cortex M33 (CPU0) Secure MPU registers write-lock.

`pub fn lock_sau(&mut self) -> LOCK_SAU_W<'_>`[src]

Bits 8:9 - Cortex M33 (CPU0) SAU registers write-lock.

`pub fn cpu0_lock_reg_lock(&mut self) -> CPU0_LOCK_REG_LOCK_W<'_>`[src]

Bits 30:31 - CPU0_LOCK_REG write-lock.

`impl W<u32, Reg<u32, _CPU1_LOCK_REG>>`[src]

`pub fn lock_ns_vtor(&mut self) -> LOCK_NS_VTOR_W<'_>`[src]

Bits 0:1 - micro-Cortex M33 (CPU1) VTOR_NS register write-lock.

`pub fn lock_ns_mpu(&mut self) -> LOCK_NS_MPU_W<'_>`[src]

Bits 2:3 - micro-Cortex M33 (CPU1) non-secure MPU register write-lock.

`pub fn cpu1_lock_reg_lock(&mut self) -> CPU1_LOCK_REG_LOCK_W<'_>`[src]

Bits 30:31 - CPU1_LOCK_REG write-lock.

`impl W<u32, Reg<u32, _MISC_CTRL_DP_REG>>`[src]

`pub fn write_lock(&mut self) -> WRITE_LOCK_W<'_>`[src]

Bits 0:1 - Write lock.

`pub fn enable_secure_checking(&mut self) -> ENABLE_SECURE_CHECKING_W<'_>`[src]

Bits 2:3 - Enable secure check for AHB matrix.

`pub fn enable_s_priv_check(&mut self) -> ENABLE_S_PRIV_CHECK_W<'_>`[src]

Bits 4:5 - Enable secure privilege check for AHB matrix.

`pub fn enable_ns_priv_check(&mut self) -> ENABLE_NS_PRIV_CHECK_W<'_>`[src]

Bits 6:7 - Enable non-secure privilege check for AHB matrix.

`pub fn disable_violation_abort(&mut self) -> DISABLE_VIOLATION_ABORT_W<'_>`[src]

Bits 8:9 - Disable secure violation abort.

`pub fn disable_simple_master_strict_mode( &mut self ) -> DISABLE_SIMPLE_MASTER_STRICT_MODE_W<'_>`[src]

Bits 10:11 - Disable simple master strict mode.

`pub fn disable_smart_master_strict_mode( &mut self ) -> DISABLE_SMART_MASTER_STRICT_MODE_W<'_>`[src]

Bits 12:13 - Disable smart master strict mode.

`pub fn idau_all_ns(&mut self) -> IDAU_ALL_NS_W<'_>`[src]

Bits 14:15 - Disable IDAU.

`impl W<u32, Reg<u32, _MISC_CTRL_REG>>`[src]

`pub fn write_lock(&mut self) -> WRITE_LOCK_W<'_>`[src]

Bits 0:1 - Write lock.

`pub fn enable_secure_checking(&mut self) -> ENABLE_SECURE_CHECKING_W<'_>`[src]

Bits 2:3 - Enable secure check for AHB matrix.

`pub fn enable_s_priv_check(&mut self) -> ENABLE_S_PRIV_CHECK_W<'_>`[src]

Bits 4:5 - Enable secure privilege check for AHB matrix.

`pub fn enable_ns_priv_check(&mut self) -> ENABLE_NS_PRIV_CHECK_W<'_>`[src]

Bits 6:7 - Enable non-secure privilege check for AHB matrix.

`pub fn disable_violation_abort(&mut self) -> DISABLE_VIOLATION_ABORT_W<'_>`[src]

Bits 8:9 - Disable secure violation abort.

`pub fn disable_simple_master_strict_mode( &mut self ) -> DISABLE_SIMPLE_MASTER_STRICT_MODE_W<'_>`[src]

Bits 10:11 - Disable simple master strict mode.

`pub fn disable_smart_master_strict_mode( &mut self ) -> DISABLE_SMART_MASTER_STRICT_MODE_W<'_>`[src]

Bits 12:13 - Disable smart master strict mode.

`pub fn idau_all_ns(&mut self) -> IDAU_ALL_NS_W<'_>`[src]

Bits 14:15 - Disable IDAU.

`impl W<u32, Reg<u32, _CPPWR>>`[src]

`pub fn su0(&mut self) -> SU0_W<'_>`[src]

Bit 0 - State UNKNOWN 0.

`pub fn sus0(&mut self) -> SUS0_W<'_>`[src]

Bit 1 - State UNKNOWN Secure only 0.

`pub fn su1(&mut self) -> SU1_W<'_>`[src]

Bit 2 - State UNKNOWN 1.

`pub fn sus1(&mut self) -> SUS1_W<'_>`[src]

Bit 3 - State UNKNOWN Secure only 1.

`pub fn su2(&mut self) -> SU2_W<'_>`[src]

Bit 4 - State UNKNOWN 2.

`pub fn sus2(&mut self) -> SUS2_W<'_>`[src]

Bit 5 - State UNKNOWN Secure only 2.

`pub fn su3(&mut self) -> SU3_W<'_>`[src]

Bit 6 - State UNKNOWN 3.

`pub fn sus3(&mut self) -> SUS3_W<'_>`[src]

Bit 7 - State UNKNOWN Secure only 3.

`pub fn su4(&mut self) -> SU4_W<'_>`[src]

Bit 8 - State UNKNOWN 4.

`pub fn sus4(&mut self) -> SUS4_W<'_>`[src]

Bit 9 - State UNKNOWN Secure only 4.

`pub fn su5(&mut self) -> SU5_W<'_>`[src]

Bit 10 - State UNKNOWN 5.

`pub fn sus5(&mut self) -> SUS5_W<'_>`[src]

Bit 11 - State UNKNOWN Secure only 5.

`pub fn su6(&mut self) -> SU6_W<'_>`[src]

Bit 12 - State UNKNOWN 6.

`pub fn sus6(&mut self) -> SUS6_W<'_>`[src]

Bit 13 - State UNKNOWN Secure only 6.

`pub fn su7(&mut self) -> SU7_W<'_>`[src]

Bit 14 - State UNKNOWN 7.

`pub fn sus7(&mut self) -> SUS7_W<'_>`[src]

Bit 15 - State UNKNOWN Secure only 7.

`pub fn su10(&mut self) -> SU10_W<'_>`[src]

Bit 20 - State UNKNOWN 10.

`pub fn sus10(&mut self) -> SUS10_W<'_>`[src]

Bit 21 - State UNKNOWN Secure only 10.

`pub fn su11(&mut self) -> SU11_W<'_>`[src]

Bit 22 - State UNKNOWN 11.

`pub fn sus11(&mut self) -> SUS11_W<'_>`[src]

Bit 23 - State UNKNOWN Secure only 11.

`impl W<u32, Reg<u32, _CTRL>>`[src]

`pub fn enable(&mut self) -> ENABLE_W<'_>`[src]

Bit 0 - Enable. Enables the SAU. This bit is RAZ/WI when the Security Extension is implemented without an SAU region.

`pub fn allns(&mut self) -> ALLNS_W<'_>`[src]

Bit 1 - All Non-secure.

`impl W<u32, Reg<u32, _TYPE>>`[src]

`pub fn sregion(&mut self) -> SREGION_W<'_>`[src]

Bits 0:7 - SAU regions. The number of implemented SAU regions.

`impl W<u32, Reg<u32, _RNR>>`[src]

`pub fn region(&mut self) -> REGION_W<'_>`[src]

Bits 0:7 - Region number.

`impl W<u32, Reg<u32, _RBAR>>`[src]

`pub fn baddr(&mut self) -> BADDR_W<'_>`[src]

Bits 5:31 - Base address. Holds bits[31:5] of the base address for the selected SAU region. Bits[4:0] of the base address are defined as 0x00.

`impl W<u32, Reg<u32, _RLAR>>`[src]

`pub fn enable(&mut self) -> ENABLE_W<'_>`[src]

Bit 0 - Enable. SAU region enable.

`pub fn nsc(&mut self) -> NSC_W<'_>`[src]

Bit 1 - Non-secure callable. Controls whether Non-secure state is permitted to execute an SG instruction from this region.

`pub fn laddr(&mut self) -> LADDR_W<'_>`[src]

Bits 5:31 - Limit address. Holds bits[31:5] of the limit address for the selected SAU region. Bits[4:0] of the limit address are defined as 0x1F.

`impl W<u32, Reg<u32, _SFSR>>`[src]

`pub fn invep(&mut self) -> INVEP_W<'_>`[src]

Bit 0 - Invalid entry point.

`pub fn invis(&mut self) -> INVIS_W<'_>`[src]

Bit 1 - Invalid integrity signature flag.

`pub fn inver(&mut self) -> INVER_W<'_>`[src]

Bit 2 - Invalid exception return flag.

`pub fn auviol(&mut self) -> AUVIOL_W<'_>`[src]

Bit 3 - Attribution unit violation flag.

`pub fn invtran(&mut self) -> INVTRAN_W<'_>`[src]

Bit 4 - Invalid transition flag.

`pub fn lsperr(&mut self) -> LSPERR_W<'_>`[src]

Bit 5 - Lazy state preservation error flag.

`pub fn sfarvalid(&mut self) -> SFARVALID_W<'_>`[src]

Bit 6 - Secure fault address valid.

`pub fn lserr(&mut self) -> LSERR_W<'_>`[src]

Bit 7 - Lazy state error flag.

`impl W<u32, Reg<u32, _SFAR>>`[src]

`pub fn address(&mut self) -> ADDRESS_W<'_>`[src]

Bits 0:31 - When the SFARVALID bit of the SFSR is set to 1, this field holds the address of an access that caused an SAU violation.

Auto Trait Implementations

`impl<U, REG> Send for W<U, REG> where REG: Send, U: Send,`

`impl<U, REG> Sync for W<U, REG> where REG: Sync, U: Sync,`

`impl<U, REG> Unpin for W<U, REG> where REG: Unpin, U: Unpin,`

Blanket Implementations

`impl<T> Any for T where T: 'static + ?Sized,` [src]

`fn type_id(&self) -> TypeId`[src]

`impl<T> Borrow<T> for T where T: ?Sized,` [src]

`fn borrow(&self) -> &T`[src]

`impl<T> BorrowMut<T> for T where T: ?Sized,` [src]

`fn borrow_mut(&mut self) -> &mut T`[src]

`impl<T> From<T> for T`[src]

`fn from(t: T) -> T`[src]

`impl<T, U> Into for T where U: From<T>,` [src]

`fn into(self) -> U`[src]

`impl<T> Same<T> for T`[src]

`type Output = T`

Should always be Self

`impl<T, U> TryFrom for T where U: Into<T>,` [src]

`type Error = Infallible`

The type returned in the event of a conversion error.

`fn try_from(value: U) -> Result<T, <T as TryFrom>::Error>`[src]

`impl<T, U> TryInto for T where U: TryFrom<T>,` [src]

`type Error = >::Error`

The type returned in the event of a conversion error.

[−][src]Struct lpc55_pac::generic::W

Implementations

impl<U, REG> W<U, REG>[src]

pub unsafe fn bits(&mut self, bits: U) -> &mut Self[src]

impl W<u32, Reg<u32, _HEADER>>[src]

pub fn field(&mut self) -> FIELD_W<'_>[src]

impl W<u32, Reg<u32, _VERSION>>[src]

pub fn field(&mut self) -> FIELD_W<'_>[src]

impl W<u32, Reg<u32, _S_FW_VERSION>>[src]

pub fn field(&mut self) -> FIELD_W<'_>[src]

impl W<u32, Reg<u32, _NS_FW_VERSION>>[src]

pub fn field(&mut self) -> FIELD_W<'_>[src]

impl W<u32, Reg<u32, _IMAGE_KEY_REVOKE>>[src]

pub fn field(&mut self) -> FIELD_W<'_>[src]

impl W<u32, Reg<u32, _ROTKH_REVOKE>>[src]

pub fn ro_tk0_en(&mut self) -> ROTK0_EN_W<'_>[src]

pub fn ro_tk1_en(&mut self) -> ROTK1_EN_W<'_>[src]

pub fn ro_tk2_en(&mut self) -> ROTK2_EN_W<'_>[src]

impl W<u32, Reg<u32, _VENDOR_USAGE>>[src]

pub fn dbg_vendor_usage(&mut self) -> DBG_VENDOR_USAGE_W<'_>[src]

pub fn inverse_value(&mut self) -> INVERSE_VALUE_W<'_>[src]

impl W<u32, Reg<u32, _DCFG_CC_SOCU_PIN>>[src]

pub fn niden(&mut self) -> NIDEN_W<'_>[src]

pub fn dbgen(&mut self) -> DBGEN_W<'_>[src]

pub fn spniden(&mut self) -> SPNIDEN_W<'_>[src]

pub fn spiden(&mut self) -> SPIDEN_W<'_>[src]

pub fn tapen(&mut self) -> TAPEN_W<'_>[src]

pub fn cpu1_dbgen(&mut self) -> CPU1_DBGEN_W<'_>[src]

pub fn isp_cmd_en(&mut self) -> ISP_CMD_EN_W<'_>[src]

pub fn fa_cmd_en(&mut self) -> FA_CMD_EN_W<'_>[src]

pub fn me_cmd_en(&mut self) -> ME_CMD_EN_W<'_>[src]

pub fn cpu1_niden(&mut self) -> CPU1_NIDEN_W<'_>[src]

pub fn uuid_check(&mut self) -> UUID_CHECK_W<'_>[src]

pub fn inverse_value(&mut self) -> INVERSE_VALUE_W<'_>[src]

impl W<u32, Reg<u32, _DCFG_CC_SOCU_DFLT>>[src]

pub fn niden(&mut self) -> NIDEN_W<'_>[src]

pub fn dbgen(&mut self) -> DBGEN_W<'_>[src]

pub fn spniden(&mut self) -> SPNIDEN_W<'_>[src]

pub fn spiden(&mut self) -> SPIDEN_W<'_>[src]

pub fn tapen(&mut self) -> TAPEN_W<'_>[src]

pub fn cpu1_dbgen(&mut self) -> CPU1_DBGEN_W<'_>[src]

pub fn isp_cmd_en(&mut self) -> ISP_CMD_EN_W<'_>[src]

pub fn fa_cmd_en(&mut self) -> FA_CMD_EN_W<'_>[src]

pub fn me_cmd_en(&mut self) -> ME_CMD_EN_W<'_>[src]

pub fn cpu1_niden(&mut self) -> CPU1_NIDEN_W<'_>[src]

pub fn inverse_value(&mut self) -> INVERSE_VALUE_W<'_>[src]

impl W<u32, Reg<u32, _ENABLE_FA_MODE>>[src]

pub fn field(&mut self) -> FIELD_W<'_>[src]

impl W<u32, Reg<u32, _CMPA_PROG_IN_PROGRESS>>[src]

pub fn field(&mut self) -> FIELD_W<'_>[src]

impl W<u32, Reg<u32, _PRINCE_REGION0_IV_CODE0>>[src]

pub fn field(&mut self) -> FIELD_W<'_>[src]

impl W<u32, Reg<u32, _PRINCE_REGION0_IV_HEADER0>>[src]

pub fn field(&mut self) -> FIELD_W<'_>[src]

impl W<u32, Reg<u32, _PRINCE_REGION0_IV_CODE1>>[src]

pub fn field(&mut self) -> FIELD_W<'_>[src]

impl W<u32, Reg<u32, _PRINCE_REGION0_IV_HEADER1>>[src]

pub fn type_(&mut self) -> TYPE_W<'_>[src]

pub fn index(&mut self) -> INDEX_W<'_>[src]

pub fn size(&mut self) -> SIZE_W<'_>[src]

impl W<u32, Reg<u32, _PRINCE_REGION0_IV_BODY0>>[src]

pub fn field(&mut self) -> FIELD_W<'_>[src]

impl W<u32, Reg<u32, _PRINCE_REGION0_IV_CODE2>>[src]

pub fn field(&mut self) -> FIELD_W<'_>[src]

impl W<u32, Reg<u32, _PRINCE_REGION0_IV_BODY1>>[src]

pub fn field(&mut self) -> FIELD_W<'_>[src]

impl W<u32, Reg<u32, _PRINCE_REGION0_IV_CODE3>>[src]

pub fn field(&mut self) -> FIELD_W<'_>[src]

impl W<u32, Reg<u32, _PRINCE_REGION0_IV_BODY2>>[src]

pub fn field(&mut self) -> FIELD_W<'_>[src]

impl W<u32, Reg<u32, _PRINCE_REGION0_IV_CODE4>>[src]

pub fn field(&mut self) -> FIELD_W<'_>[src]

impl W<u32, Reg<u32, _PRINCE_REGION0_IV_BODY3>>[src]

pub fn field(&mut self) -> FIELD_W<'_>[src]

impl W<u32, Reg<u32, _PRINCE_REGION0_IV_CODE5>>[src]

pub fn field(&mut self) -> FIELD_W<'_>[src]

impl W<u32, Reg<u32, _PRINCE_REGION0_IV_BODY4>>[src]

pub fn field(&mut self) -> FIELD_W<'_>[src]

impl W<u32, Reg<u32, _PRINCE_REGION0_IV_CODE6>>[src]

pub fn field(&mut self) -> FIELD_W<'_>[src]

`impl<U, REG> W<U, REG>`[src]

`pub unsafe fn bits(&mut self, bits: U) -> &mut Self`[src]

`impl W<u32, Reg<u32, _HEADER>>`[src]

`pub fn field(&mut self) -> FIELD_W<'_>`[src]

`impl W<u32, Reg<u32, _VERSION>>`[src]

`pub fn field(&mut self) -> FIELD_W<'_>`[src]

`impl W<u32, Reg<u32, _S_FW_VERSION>>`[src]

`pub fn field(&mut self) -> FIELD_W<'_>`[src]

`impl W<u32, Reg<u32, _NS_FW_VERSION>>`[src]

`pub fn field(&mut self) -> FIELD_W<'_>`[src]

`impl W<u32, Reg<u32, _IMAGE_KEY_REVOKE>>`[src]

`pub fn field(&mut self) -> FIELD_W<'_>`[src]

`impl W<u32, Reg<u32, _ROTKH_REVOKE>>`[src]

`pub fn ro_tk0_en(&mut self) -> ROTK0_EN_W<'_>`[src]

`pub fn ro_tk1_en(&mut self) -> ROTK1_EN_W<'_>`[src]

`pub fn ro_tk2_en(&mut self) -> ROTK2_EN_W<'_>`[src]

`impl W<u32, Reg<u32, _VENDOR_USAGE>>`[src]

`pub fn dbg_vendor_usage(&mut self) -> DBG_VENDOR_USAGE_W<'_>`[src]

`pub fn inverse_value(&mut self) -> INVERSE_VALUE_W<'_>`[src]

`impl W<u32, Reg<u32, _DCFG_CC_SOCU_PIN>>`[src]

`pub fn niden(&mut self) -> NIDEN_W<'_>`[src]

`pub fn dbgen(&mut self) -> DBGEN_W<'_>`[src]

`pub fn spniden(&mut self) -> SPNIDEN_W<'_>`[src]

`pub fn spiden(&mut self) -> SPIDEN_W<'_>`[src]

`pub fn tapen(&mut self) -> TAPEN_W<'_>`[src]

`pub fn cpu1_dbgen(&mut self) -> CPU1_DBGEN_W<'_>`[src]

`pub fn isp_cmd_en(&mut self) -> ISP_CMD_EN_W<'_>`[src]

`pub fn fa_cmd_en(&mut self) -> FA_CMD_EN_W<'_>`[src]

`pub fn me_cmd_en(&mut self) -> ME_CMD_EN_W<'_>`[src]

`pub fn cpu1_niden(&mut self) -> CPU1_NIDEN_W<'_>`[src]

`pub fn uuid_check(&mut self) -> UUID_CHECK_W<'_>`[src]

`pub fn inverse_value(&mut self) -> INVERSE_VALUE_W<'_>`[src]

`impl W<u32, Reg<u32, _DCFG_CC_SOCU_DFLT>>`[src]

`pub fn niden(&mut self) -> NIDEN_W<'_>`[src]

`pub fn dbgen(&mut self) -> DBGEN_W<'_>`[src]

`pub fn spniden(&mut self) -> SPNIDEN_W<'_>`[src]

`pub fn spiden(&mut self) -> SPIDEN_W<'_>`[src]

`pub fn tapen(&mut self) -> TAPEN_W<'_>`[src]

`pub fn cpu1_dbgen(&mut self) -> CPU1_DBGEN_W<'_>`[src]

`pub fn isp_cmd_en(&mut self) -> ISP_CMD_EN_W<'_>`[src]

`pub fn fa_cmd_en(&mut self) -> FA_CMD_EN_W<'_>`[src]

`pub fn me_cmd_en(&mut self) -> ME_CMD_EN_W<'_>`[src]

`pub fn cpu1_niden(&mut self) -> CPU1_NIDEN_W<'_>`[src]

`pub fn inverse_value(&mut self) -> INVERSE_VALUE_W<'_>`[src]

`impl W<u32, Reg<u32, _ENABLE_FA_MODE>>`[src]

`pub fn field(&mut self) -> FIELD_W<'_>`[src]

`impl W<u32, Reg<u32, _CMPA_PROG_IN_PROGRESS>>`[src]

`pub fn field(&mut self) -> FIELD_W<'_>`[src]

`impl W<u32, Reg<u32, _PRINCE_REGION0_IV_CODE0>>`[src]

`pub fn field(&mut self) -> FIELD_W<'_>`[src]

`impl W<u32, Reg<u32, _PRINCE_REGION0_IV_HEADER0>>`[src]

`pub fn field(&mut self) -> FIELD_W<'_>`[src]

`impl W<u32, Reg<u32, _PRINCE_REGION0_IV_CODE1>>`[src]

`pub fn field(&mut self) -> FIELD_W<'_>`[src]

`impl W<u32, Reg<u32, _PRINCE_REGION0_IV_HEADER1>>`[src]

`pub fn type_(&mut self) -> TYPE_W<'_>`[src]

`pub fn index(&mut self) -> INDEX_W<'_>`[src]

`pub fn size(&mut self) -> SIZE_W<'_>`[src]

`impl W<u32, Reg<u32, _PRINCE_REGION0_IV_BODY0>>`[src]

`pub fn field(&mut self) -> FIELD_W<'_>`[src]

`impl W<u32, Reg<u32, _PRINCE_REGION0_IV_CODE2>>`[src]

`pub fn field(&mut self) -> FIELD_W<'_>`[src]

`impl W<u32, Reg<u32, _PRINCE_REGION0_IV_BODY1>>`[src]

`pub fn field(&mut self) -> FIELD_W<'_>`[src]

`impl W<u32, Reg<u32, _PRINCE_REGION0_IV_CODE3>>`[src]

`pub fn field(&mut self) -> FIELD_W<'_>`[src]

`impl W<u32, Reg<u32, _PRINCE_REGION0_IV_BODY2>>`[src]

`pub fn field(&mut self) -> FIELD_W<'_>`[src]

`impl W<u32, Reg<u32, _PRINCE_REGION0_IV_CODE4>>`[src]

`pub fn field(&mut self) -> FIELD_W<'_>`[src]

`impl W<u32, Reg<u32, _PRINCE_REGION0_IV_BODY3>>`[src]

`pub fn field(&mut self) -> FIELD_W<'_>`[src]

`impl W<u32, Reg<u32, _PRINCE_REGION0_IV_CODE5>>`[src]

`pub fn field(&mut self) -> FIELD_W<'_>`[src]

`impl W<u32, Reg<u32, _PRINCE_REGION0_IV_BODY4>>`[src]

`pub fn field(&mut self) -> FIELD_W<'_>`[src]

`impl W<u32, Reg<u32, _PRINCE_REGION0_IV_CODE6>>`[src]

`pub fn field(&mut self) -> FIELD_W<'_>`[src]

`impl W<u32, Reg<u32, _PRINCE_REGION0_IV_BODY5>>`[src]

`pub fn field(&mut self) -> FIELD_W<'_>`[src]