Struct lpc55_pac::rtc::ctrl::RTC_SUBSEC_ENA_W

[+] Show declaration

pub struct RTC_SUBSEC_ENA_W<'a> { /* fields omitted */ }

[−] Expand description

Write proxy for field RTC_SUBSEC_ENA

Implementations

impl<'a> RTC_SUBSEC_ENA_W<'a>[−]

pub fn variant(self, variant: RTC_SUBSEC_ENA_A) -> &'a mut W[−]

Writes variant to the field

pub fn power_up(self) -> &'a mut W[−]

The sub-second counter (if implemented) is disabled. This bit is cleared by a system-level POR or BOD reset as well as a by the RTC_ENA bit (bit 7 in this register). On modules not equipped with a sub-second counter, this bit will always read-back as a '0'.

pub fn powered_down(self) -> &'a mut W[−]

The 32 KHz sub-second counter is enabled (if implemented). Counting commences on the start of the first one-second interval after this bit is set. Note: This bit can only be set after the RTC_ENA bit (bit 7) is set by a previous write operation. Note: The RTC sub-second counter must be re-enabled whenever the chip exits deep power-down mode.

pub fn set_bit(self) -> &'a mut W[−]

Sets the field bit

pub fn clear_bit(self) -> &'a mut W[−]

Clears the field bit

pub fn bit(self, value: bool) -> &'a mut W[−]

Writes raw bits to the field