Module lpc55_pac::ahb_secure_ctrl::master_sec_anti_pol_reg

[−] Expand description

master secure level anti-pole register

Structs

CPU1C_W	Write proxy for field CPU1C
CPU1S_W	Write proxy for field CPU1S
HASH_W	Write proxy for field HASH
MASTER_SEC_LEVEL_ANTIPOL_LOCK_W	Write proxy for field MASTER_SEC_LEVEL_ANTIPOL_LOCK
PQ_W	Write proxy for field PQ
SDIO_W	Write proxy for field SDIO
SDMA0_W	Write proxy for field SDMA0
SDMA1_W	Write proxy for field SDMA1
USBFSD_W	Write proxy for field USBFSD
USBFSH_W	Write proxy for field USBFSH

Enums

CPU1C_A	Micro-Cortex M33 (CPU1) Code bus. Must be equal to NOT(MASTER_SEC_LEVEL.CPU1C)
CPU1S_A	Micro-Cortex M33 (CPU1) System bus. Must be equal to NOT(MASTER_SEC_LEVEL.CPU1S)
HASH_A	Hash. Must be equal to NOT(MASTER_SEC_LEVEL.HASH)
MASTER_SEC_LEVEL_ANTIPOL_LOCK_A	MASTER_SEC_ANTI_POL_REG register write-lock.
PQ_A	Power Quad. Must be equal to NOT(MASTER_SEC_LEVEL.PQ)
SDIO_A	SDIO. Must be equal to NOT(MASTER_SEC_LEVEL.SDIO)
SDMA0_A	System DMA 0. Must be equal to NOT(MASTER_SEC_LEVEL.SDMA0)
SDMA1_A	System DMA 1 security level. Must be equal to NOT(MASTER_SEC_LEVEL.SDMA1)
USBFSD_A	USB Full Speed Device. Must be equal to NOT(MASTER_SEC_LEVEL.USBFSD)
USBFSH_A	USB Full speed Host. Must be equal to NOT(MASTER_SEC_LEVEL.USBFSH)

Type Definitions

CPU1C_R	Reader of field CPU1C
CPU1S_R	Reader of field CPU1S
HASH_R	Reader of field HASH
MASTER_SEC_LEVEL_ANTIPOL_LOCK_R	Reader of field MASTER_SEC_LEVEL_ANTIPOL_LOCK
PQ_R	Reader of field PQ
R	Reader of register MASTER_SEC_ANTI_POL_REG
SDIO_R	Reader of field SDIO
SDMA0_R	Reader of field SDMA0
SDMA1_R	Reader of field SDMA1
USBFSD_R	Reader of field USBFSD
USBFSH_R	Reader of field USBFSH
W	Writer for register MASTER_SEC_ANTI_POL_REG