[−][src]Module lpc55_pac::ahb_secure_ctrl
AHB secure controller
Modules
| cpu0_lock_reg | Miscalleneous control signals for in Cortex M33 (CPU0) |
| cpu1_lock_reg | Miscalleneous control signals for in micro-Cortex M33 (CPU1) |
| master_sec_anti_pol_reg | master secure level anti-pole register |
| master_sec_level | master secure level register |
| misc_ctrl_dp_reg | secure control duplicate register |
| misc_ctrl_reg | secure control register |
| sec_cpu_int_mask0 | Secure Interrupt mask for CPU1 |
| sec_cpu_int_mask1 | Secure Interrupt mask for CPU1 |
| sec_ctrl_ahb_port8_slave0_rule | Security access rules for AHB peripherals. |
| sec_ctrl_ahb_port8_slave1_rule | Security access rules for AHB peripherals. |
| sec_ctrl_ahb_port9_slave0_rule | Security access rules for AHB peripherals. |
| sec_ctrl_ahb_port9_slave1_rule | Security access rules for AHB peripherals. |
| sec_ctrl_ahb_port10_slave0_rule | Security access rules for AHB peripherals. |
| sec_ctrl_ahb_port10_slave1_rule | Security access rules for AHB peripherals. |
| sec_ctrl_ahb_sec_ctrl_mem_rule | Security access rules for AHB_SEC_CTRL_AHB. |
| sec_ctrl_apb_bridge0_mem_ctrl0 | Security access rules for APB Bridge 0 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 0 sectors in total. |
| sec_ctrl_apb_bridge0_mem_ctrl1 | Security access rules for APB Bridge 0 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 0 sectors in total. |
| sec_ctrl_apb_bridge0_mem_ctrl2 | Security access rules for APB Bridge 0 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 0 sectors in total. |
| sec_ctrl_apb_bridge1_mem_ctrl0 | Security access rules for APB Bridge 1 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 1 sectors in total. |
| sec_ctrl_apb_bridge1_mem_ctrl1 | Security access rules for APB Bridge 1 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 1 sectors in total. |
| sec_ctrl_apb_bridge1_mem_ctrl2 | Security access rules for APB Bridge 1 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 1 sectors in total. |
| sec_ctrl_apb_bridge1_mem_ctrl3 | Security access rules for APB Bridge 1 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 1 sectors in total. |
| sec_ctrl_apb_bridge_slave_rule | Security access rules for both APB Bridges slaves. |
| sec_ctrl_flash_mem_rule0 | Security access rules for FLASH sector 0 to sector 20. Each Flash sector is 32 Kbytes. There are 20 FLASH sectors in total. |
| sec_ctrl_flash_mem_rule1 | Security access rules for FLASH sector 0 to sector 20. Each Flash sector is 32 Kbytes. There are 20 FLASH sectors in total. |
| sec_ctrl_flash_mem_rule2 | Security access rules for FLASH sector 0 to sector 20. Each Flash sector is 32 Kbytes. There are 20 FLASH sectors in total. |
| sec_ctrl_flash_rom_slave_rule | Security access rules for Flash and ROM slaves. |
| sec_ctrl_ram0_mem_rule0 | Security access rules for RAM0 slaves. |
| sec_ctrl_ram0_mem_rule1 | Security access rules for RAM0 slaves. |
| sec_ctrl_ram0_slave_rule | Security access rules for RAM0 slaves. |
| sec_ctrl_ram1_mem_rule0 | Security access rules for RAM1 slaves. |
| sec_ctrl_ram1_mem_rule1 | Security access rules for RAM1 slaves. |
| sec_ctrl_ram1_slave_rule | Security access rules for RAM1 slaves. |
| sec_ctrl_ram2_mem_rule0 | Security access rules for RAM2 slaves. |
| sec_ctrl_ram2_mem_rule1 | Security access rules for RAM2 slaves. |
| sec_ctrl_ram2_slave_rule | Security access rules for RAM2 slaves. |
| sec_ctrl_ram3_mem_rule0 | Security access rules for RAM3 slaves. |
| sec_ctrl_ram3_mem_rule1 | Security access rules for RAM3 slaves. |
| sec_ctrl_ram3_slave_rule | Security access rules for RAM3 slaves. |
| sec_ctrl_ram4_mem_rule0 | Security access rules for RAM4 slaves. |
| sec_ctrl_ram4_slave_rule | Security access rules for RAM4 slaves. |
| sec_ctrl_ramx_mem_rule0 | Security access rules for RAMX slaves. |
| sec_ctrl_ramx_slave_rule | Security access rules for RAMX slaves. |
| sec_ctrl_rom_mem_rule0 | Security access rules for ROM sector 0 to sector 31. Each ROM sector is 4 Kbytes. There are 32 ROM sectors in total. |
| sec_ctrl_rom_mem_rule1 | Security access rules for ROM sector 0 to sector 31. Each ROM sector is 4 Kbytes. There are 32 ROM sectors in total. |
| sec_ctrl_rom_mem_rule2 | Security access rules for ROM sector 0 to sector 31. Each ROM sector is 4 Kbytes. There are 32 ROM sectors in total. |
| sec_ctrl_rom_mem_rule3 | Security access rules for ROM sector 0 to sector 31. Each ROM sector is 4 Kbytes. There are 32 ROM sectors in total. |
| sec_ctrl_usb_hs_mem_rule | Security access rules for RAM_USB_HS. |
| sec_ctrl_usb_hs_slave_rule | Security access rules for USB High speed RAM slaves. |
| sec_gpio_mask0 | Secure GPIO mask for port 0 pins. |
| sec_gpio_mask1 | Secure GPIO mask for port 1 pins. |
| sec_mask_lock | Security General Purpose register access control. |
| sec_vio_addr | most recent security violation address for AHB port n |
| sec_vio_info_valid | security violation address/information registers valid flags |
| sec_vio_misc_info | most recent security violation miscellaneous information for AHB port n |
Structs
| RegisterBlock | Register block |
Type Definitions
| CPU0_LOCK_REG | Miscalleneous control signals for in Cortex M33 (CPU0) |
| CPU1_LOCK_REG | Miscalleneous control signals for in micro-Cortex M33 (CPU1) |
| MASTER_SEC_ANTI_POL_REG | master secure level anti-pole register |
| MASTER_SEC_LEVEL | master secure level register |
| MISC_CTRL_DP_REG | secure control duplicate register |
| MISC_CTRL_REG | secure control register |
| SEC_CPU_INT_MASK0 | Secure Interrupt mask for CPU1 |
| SEC_CPU_INT_MASK1 | Secure Interrupt mask for CPU1 |
| SEC_CTRL_AHB_PORT8_SLAVE0_RULE | Security access rules for AHB peripherals. |
| SEC_CTRL_AHB_PORT8_SLAVE1_RULE | Security access rules for AHB peripherals. |
| SEC_CTRL_AHB_PORT9_SLAVE0_RULE | Security access rules for AHB peripherals. |
| SEC_CTRL_AHB_PORT9_SLAVE1_RULE | Security access rules for AHB peripherals. |
| SEC_CTRL_AHB_PORT10_SLAVE0_RULE | Security access rules for AHB peripherals. |
| SEC_CTRL_AHB_PORT10_SLAVE1_RULE | Security access rules for AHB peripherals. |
| SEC_CTRL_AHB_SEC_CTRL_MEM_RULE | Security access rules for AHB_SEC_CTRL_AHB. |
| SEC_CTRL_APB_BRIDGE0_MEM_CTRL0 | Security access rules for APB Bridge 0 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 0 sectors in total. |
| SEC_CTRL_APB_BRIDGE0_MEM_CTRL1 | Security access rules for APB Bridge 0 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 0 sectors in total. |
| SEC_CTRL_APB_BRIDGE0_MEM_CTRL2 | Security access rules for APB Bridge 0 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 0 sectors in total. |
| SEC_CTRL_APB_BRIDGE1_MEM_CTRL0 | Security access rules for APB Bridge 1 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 1 sectors in total. |
| SEC_CTRL_APB_BRIDGE1_MEM_CTRL1 | Security access rules for APB Bridge 1 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 1 sectors in total. |
| SEC_CTRL_APB_BRIDGE1_MEM_CTRL2 | Security access rules for APB Bridge 1 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 1 sectors in total. |
| SEC_CTRL_APB_BRIDGE1_MEM_CTRL3 | Security access rules for APB Bridge 1 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 1 sectors in total. |
| SEC_CTRL_APB_BRIDGE_SLAVE_RULE | Security access rules for both APB Bridges slaves. |
| SEC_CTRL_FLASH_MEM_RULE0 | Security access rules for FLASH sector 0 to sector 20. Each Flash sector is 32 Kbytes. There are 20 FLASH sectors in total. |
| SEC_CTRL_FLASH_MEM_RULE1 | Security access rules for FLASH sector 0 to sector 20. Each Flash sector is 32 Kbytes. There are 20 FLASH sectors in total. |
| SEC_CTRL_FLASH_MEM_RULE2 | Security access rules for FLASH sector 0 to sector 20. Each Flash sector is 32 Kbytes. There are 20 FLASH sectors in total. |
| SEC_CTRL_FLASH_ROM_SLAVE_RULE | Security access rules for Flash and ROM slaves. |
| SEC_CTRL_RAM0_MEM_RULE0 | Security access rules for RAM0 slaves. |
| SEC_CTRL_RAM0_MEM_RULE1 | Security access rules for RAM0 slaves. |
| SEC_CTRL_RAM0_SLAVE_RULE | Security access rules for RAM0 slaves. |
| SEC_CTRL_RAM1_MEM_RULE0 | Security access rules for RAM1 slaves. |
| SEC_CTRL_RAM1_MEM_RULE1 | Security access rules for RAM1 slaves. |
| SEC_CTRL_RAM1_SLAVE_RULE | Security access rules for RAM1 slaves. |
| SEC_CTRL_RAM2_MEM_RULE0 | Security access rules for RAM2 slaves. |
| SEC_CTRL_RAM2_MEM_RULE1 | Security access rules for RAM2 slaves. |
| SEC_CTRL_RAM2_SLAVE_RULE | Security access rules for RAM2 slaves. |
| SEC_CTRL_RAM3_MEM_RULE0 | Security access rules for RAM3 slaves. |
| SEC_CTRL_RAM3_MEM_RULE1 | Security access rules for RAM3 slaves. |
| SEC_CTRL_RAM3_SLAVE_RULE | Security access rules for RAM3 slaves. |
| SEC_CTRL_RAM4_MEM_RULE0 | Security access rules for RAM4 slaves. |
| SEC_CTRL_RAM4_SLAVE_RULE | Security access rules for RAM4 slaves. |
| SEC_CTRL_RAMX_MEM_RULE0 | Security access rules for RAMX slaves. |
| SEC_CTRL_RAMX_SLAVE_RULE | Security access rules for RAMX slaves. |
| SEC_CTRL_ROM_MEM_RULE0 | Security access rules for ROM sector 0 to sector 31. Each ROM sector is 4 Kbytes. There are 32 ROM sectors in total. |
| SEC_CTRL_ROM_MEM_RULE1 | Security access rules for ROM sector 0 to sector 31. Each ROM sector is 4 Kbytes. There are 32 ROM sectors in total. |
| SEC_CTRL_ROM_MEM_RULE2 | Security access rules for ROM sector 0 to sector 31. Each ROM sector is 4 Kbytes. There are 32 ROM sectors in total. |
| SEC_CTRL_ROM_MEM_RULE3 | Security access rules for ROM sector 0 to sector 31. Each ROM sector is 4 Kbytes. There are 32 ROM sectors in total. |
| SEC_CTRL_USB_HS_MEM_RULE | Security access rules for RAM_USB_HS. |
| SEC_CTRL_USB_HS_SLAVE_RULE | Security access rules for USB High speed RAM slaves. |
| SEC_GPIO_MASK0 | Secure GPIO mask for port 0 pins. |
| SEC_GPIO_MASK1 | Secure GPIO mask for port 1 pins. |
| SEC_MASK_LOCK | Security General Purpose register access control. |
| SEC_VIO_ADDR | most recent security violation address for AHB port n |
| SEC_VIO_INFO_VALID | security violation address/information registers valid flags |
| SEC_VIO_MISC_INFO | most recent security violation miscellaneous information for AHB port n |