Type Definition lpc55_pac::usbphy::pll_sic::W

type W = W<u32, PLL_SIC>;

Writer for register PLL_SIC

Implementations

impl W

pub fn pll_en_usb_clks(&mut self) -> PLL_EN_USB_CLKS_W<'_>

Bit 6 - Enables the USB clock from PLL to USB PHY

pub fn pll_power(&mut self) -> PLL_POWER_W<'_>

Bit 12 - Power up the USB PLL

pub fn pll_enable(&mut self) -> PLL_ENABLE_W<'_>

Bit 13 - Enables the clock output from the USB PLL

pub fn refbias_pwd_sel(&mut self) -> REFBIAS_PWD_SEL_W<'_>

Bit 19 - Reference bias power down select.

pub fn refbias_pwd(&mut self) -> REFBIAS_PWD_W<'_>

Bit 20 - Power down the reference bias This bit is only used when REFBIAS_PWD_SEL is set to 1.

pub fn pll_reg_enable(&mut self) -> PLL_REG_ENABLE_W<'_>

Bit 21 - This field controls the USB PLL regulator, set to enable the regulator

pub fn pll_div_sel(&mut self) -> PLL_DIV_SEL_W<'_>

Bits 22:24 - This field controls the USB PLL feedback loop divider

pub fn pll_prediv(&mut self) -> PLL_PREDIV_W<'_>

Bit 30 - This is selection between /1 or /2 to expand the range of ref input clock.