[−][src]Module lpc55_pac::usart0::ctl
USART Control register. USART control settings that are more likely to change during operation.
Structs
| ADDRDET_W | Write proxy for field |
| AUTOBAUD_W | Write proxy for field |
| CC_W | Write proxy for field |
| CLRCCONRX_W | Write proxy for field |
| TXBRKEN_W | Write proxy for field |
| TXDIS_W | Write proxy for field |
Enums
| ADDRDET_A | Enable address detect mode. |
| AUTOBAUD_A | Autobaud enable. |
| CC_A | Continuous Clock generation. By default, SCLK is only output while data is being transmitted in synchronous mode. |
| CLRCCONRX_A | Clear Continuous Clock. |
| TXBRKEN_A | Break Enable. |
| TXDIS_A | Transmit Disable. |
Type Definitions
| ADDRDET_R | Reader of field |
| AUTOBAUD_R | Reader of field |
| CC_R | Reader of field |
| CLRCCONRX_R | Reader of field |
| R | Reader of register CTL |
| TXBRKEN_R | Reader of field |
| TXDIS_R | Reader of field |
| W | Writer for register CTL |