Type Definition lpc55_pac::syscon::PLL0CLKDIV

type PLL0CLKDIV = Reg<u32, _PLL0CLKDIV>;

[−] Expand description

PLL0 clock divider

This register you can read, reset, write, write_with_zero, modify. See API.

For information about available fields see pll0clkdiv module

Trait Implementations

impl Readable for PLL0CLKDIV

read() method returns pll0clkdiv::R reader structure

impl ResetValue for PLL0CLKDIV[+]

Register PLL0CLKDIV reset()'s with value 0x4000_0000

[+] Show hidden undocumented items

type Type = u32

Register size

fn reset_value() -> Self::Type[−]

Reset value of the register

impl Writable for PLL0CLKDIV

write(|w| ..) method takes pll0clkdiv::W writer structure