[−][src]Type Definition lpc55_pac::syscon::pll0clkdiv::R

type R = R<u32, PLL0CLKDIV>;

Reader of register PLL0CLKDIV

Implementations

`impl R`[src]

`pub fn div(&self) -> DIV_R`[src]

Bits 0:7 - Clock divider value.

`pub fn halt(&self) -> HALT_R`[src]

Bit 30 - Halts the divider counter.

`pub fn reqflag(&self) -> REQFLAG_R`[src]

Bit 31 - Divider status flag.