[−][src]Enum lpc55_pac::ctimer0::ctcr::CTMODE_A
pub enum CTMODE_A { TIMER, COUNTER_RISING_EDGE, COUNTER_FALLING_EDGE, COUNTER_DUAL_EDGE, }
Counter/Timer Mode This field selects which rising APB bus clock edges can increment Timer's Prescale Counter (PC), or clear PC and increment Timer Counter (TC). Timer Mode: the TC is incremented when the Prescale Counter matches the Prescale Register.
Value on reset: 0
Variants
0: Timer Mode. Incremented every rising APB bus clock edge.
1: Counter Mode rising edge. TC is incremented on rising edges on the CAP input selected by bits 3:2.
2: Counter Mode falling edge. TC is incremented on falling edges on the CAP input selected by bits 3:2.
3: Counter Mode dual edge. TC is incremented on both edges on the CAP input selected by bits 3:2.
Trait Implementations
impl Clone for CTMODE_A
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impl Copy for CTMODE_A
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impl Debug for CTMODE_A
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impl From<CTMODE_A> for u8
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impl PartialEq<CTMODE_A> for CTMODE_A
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impl StructuralPartialEq for CTMODE_A
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Auto Trait Implementations
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