[−][src]Module lpc55_pac::ctimer0
Standard counter/timers (CTIMER0 to 4)
Modules
| ccr | Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place. |
| cr | Capture Register . CR is loaded with the value of TC when there is an event on the CAPn. input. |
| ctcr | Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting. |
| emr | External Match Register. The EMR controls the match function and the external match pins. |
| ir | Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending. |
| mcr | Match Control Register |
| mr | Match Register . MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC. |
| msr | Match Shadow Register |
| pc | Prescale Counter |
| pr | Prescale Register |
| pwmc | PWM Control Register. This register enables PWM mode for the external match pins. |
| tc | Timer Counter |
| tcr | Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR. |
Structs
| RegisterBlock | Register block |
Type Definitions
| CCR | Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place. |
| CR | Capture Register . CR is loaded with the value of TC when there is an event on the CAPn. input. |
| CTCR | Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting. |
| EMR | External Match Register. The EMR controls the match function and the external match pins. |
| IR | Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending. |
| MCR | Match Control Register |
| MR | Match Register . MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC. |
| MSR | Match Shadow Register |
| PC | Prescale Counter |
| PR | Prescale Register |
| PWMC | PWM Control Register. This register enables PWM mode for the external match pins. |
| TC | Timer Counter |
| TCR | Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR. |