Type Definition lpc55_pac::usbphy::pll_sic_set::R

type R = R<u32, PLL_SIC_SET>;

Reader of register PLL_SIC_SET

Implementations

impl R

pub fn pll_en_usb_clks(&self) -> PLL_EN_USB_CLKS_R

Bit 6 - Enables the USB clock from PLL to USB PHY

pub fn pll_power(&self) -> PLL_POWER_R

Bit 12 - Power up the USB PLL

pub fn pll_enable(&self) -> PLL_ENABLE_R

Bit 13 - Enables the clock output from the USB PLL

pub fn refbias_pwd_sel(&self) -> REFBIAS_PWD_SEL_R

Bit 19 - Reference bias power down select.

pub fn refbias_pwd(&self) -> REFBIAS_PWD_R

Bit 20 - Power down the reference bias This bit is only used when REFBIAS_PWD_SEL is set to 1.

pub fn pll_reg_enable(&self) -> PLL_REG_ENABLE_R

Bit 21 - This field controls the USB PLL regulator, set to enable the regulator

pub fn pll_div_sel(&self) -> PLL_DIV_SEL_R

Bits 22:24 - This field controls the USB PLL feedback loop divider

pub fn pll_prediv(&self) -> PLL_PREDIV_R

Bit 30 - This is selection between /1 or /2 to expand the range of ref input clock.

pub fn pll_lock(&self) -> PLL_LOCK_R

Bit 31 - USB PLL lock status indicator