[−][src]Module lpc55_pac::usbphy::pll_sic_clr

USB PHY PLL Control/Status Register

Structs

PLL_DIV_SEL_W	Write proxy for field `PLL_DIV_SEL`
PLL_ENABLE_W	Write proxy for field `PLL_ENABLE`
PLL_EN_USB_CLKS_W	Write proxy for field `PLL_EN_USB_CLKS`
PLL_POWER_W	Write proxy for field `PLL_POWER`
PLL_PREDIV_W	Write proxy for field `PLL_PREDIV`
PLL_REG_ENABLE_W	Write proxy for field `PLL_REG_ENABLE`
REFBIAS_PWD_SEL_W	Write proxy for field `REFBIAS_PWD_SEL`
REFBIAS_PWD_W	Write proxy for field `REFBIAS_PWD`

PLL_DIV_SEL_A	This field controls the USB PLL feedback loop divider
PLL_LOCK_A	USB PLL lock status indicator
REFBIAS_PWD_SEL_A	Reference bias power down select.

PLL_DIV_SEL_R	Reader of field `PLL_DIV_SEL`
PLL_ENABLE_R	Reader of field `PLL_ENABLE`
PLL_EN_USB_CLKS_R	Reader of field `PLL_EN_USB_CLKS`
PLL_LOCK_R	Reader of field `PLL_LOCK`
PLL_POWER_R	Reader of field `PLL_POWER`
PLL_PREDIV_R	Reader of field `PLL_PREDIV`
PLL_REG_ENABLE_R	Reader of field `PLL_REG_ENABLE`
R	Reader of register PLL_SIC_CLR
REFBIAS_PWD_R	Reader of field `REFBIAS_PWD`
REFBIAS_PWD_SEL_R	Reader of field `REFBIAS_PWD_SEL`
W	Writer for register PLL_SIC_CLR