[−][src]Enum lpc55_pac::usart0::fifotrig::RXLVLENA_A

[−]
pub enum RXLVLENA_A {
    DISABLED,
    ENABLED,
}
[−]

Receive FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET, or a DMA trigger if DMARX in FIFOCFG is set.

Value on reset: 0

Variants

DISABLED
[−]

0: Receive FIFO level does not generate a FIFO level trigger.

ENABLED
[−]

1: An trigger will be generated if the receive FIFO level reaches the value specified by the RXLVL field in this register.

Trait Implementations

impl Clone for RXLVLENA_A[src][+]

impl Copy for RXLVLENA_A[src]

impl Debug for RXLVLENA_A[src][+]

impl From<RXLVLENA_A> for bool[src][+]

impl PartialEq<RXLVLENA_A> for RXLVLENA_A[src][+]

impl StructuralPartialEq for RXLVLENA_A[src]

Auto Trait Implementations

impl Send for RXLVLENA_A

impl Sync for RXLVLENA_A

impl Unpin for RXLVLENA_A

Blanket Implementations

impl<T> Any for T where
    T: 'static + ?Sized, [src][+]

impl<T> Borrow<T> for T where
    T: ?Sized, [src][+]

impl<T> BorrowMut<T> for T where
    T: ?Sized, [src][+]

impl<T> From<T> for T[src][+]

impl<T, U> Into<U> for T where
    U: From<T>, [src][+]

impl<T> Same<T> for T[src]

type Output = T

Should always be Self

impl<T, U> TryFrom<U> for T where
    U: Into<T>, [src][+]

type Error = Infallible

The type returned in the event of a conversion error.

impl<T, U> TryInto<U> for T where
    U: TryFrom<T>, [src][+]

type Error = <U as TryFrom<T>>::Error

The type returned in the event of a conversion error.