Module lpc55_pac::usart0::ctl

USART Control register. USART control settings that are more likely to change during operation.

Structs

ADDRDET_W	Write proxy for field ADDRDET
AUTOBAUD_W	Write proxy for field AUTOBAUD
CC_W	Write proxy for field CC
CLRCCONRX_W	Write proxy for field CLRCCONRX
TXBRKEN_W	Write proxy for field TXBRKEN
TXDIS_W	Write proxy for field TXDIS

Enums

ADDRDET_A	Enable address detect mode.
AUTOBAUD_A	Autobaud enable.
CC_A	Continuous Clock generation. By default, SCLK is only output while data is being transmitted in synchronous mode.
CLRCCONRX_A	Clear Continuous Clock.
TXBRKEN_A	Break Enable.
TXDIS_A	Transmit Disable.

Type Definitions

ADDRDET_R	Reader of field ADDRDET
AUTOBAUD_R	Reader of field AUTOBAUD
CC_R	Reader of field CC
CLRCCONRX_R	Reader of field CLRCCONRX
R	Reader of register CTL
TXBRKEN_R	Reader of field TXBRKEN
TXDIS_R	Reader of field TXDIS
W	Writer for register CTL