Enum lpc55_pac::syscon::sdioclkctrl::CCLK_SAMPLE_PHASE_A

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[+] Expand attributes
#[repr(u8)]pub enum CCLK_SAMPLE_PHASE_A {
    ENUM_0_DEG,
    ENUM_90_DEG,
    ENUM_180_DEG,
    ENUM_270_DEG,
}

[−] Expand description

Programmable delay value by which cclk_in_sample is delayed with regard to cclk_in.

Value on reset: 0

Variants

ENUM_0_DEG

[−] Expand description

0: 0 degree shift.

ENUM_90_DEG

[−] Expand description

1: 90 degree shift.

ENUM_180_DEG

[−] Expand description

2: 180 degree shift.

ENUM_270_DEG

[−] Expand description

3: 270 degree shift.

Trait Implementations

impl Clone for CCLK_SAMPLE_PHASE_A[+]

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fn clone(&self) -> CCLK_SAMPLE_PHASE_A[−]

Returns a copy of the value.

fn clone_from(&mut self, source: &Self)[−]

Performs copy-assignment from source.

impl Copy for CCLK_SAMPLE_PHASE_A

impl Debug for CCLK_SAMPLE_PHASE_A[+]

[+] Show hidden undocumented items

fn fmt(&self, f: &mut Formatter<'_>) -> Result[−]

Formats the value using the given formatter.

impl From<CCLK_SAMPLE_PHASE_A> for u8[+]

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fn from(variant: CCLK_SAMPLE_PHASE_A) -> Self[−]

Performs the conversion.

impl PartialEq<CCLK_SAMPLE_PHASE_A> for CCLK_SAMPLE_PHASE_A[+]

[+] Show hidden undocumented items

fn eq(&self, other: &CCLK_SAMPLE_PHASE_A) -> bool[−]

This method tests for self and other values to be equal, and is used by ==.

[+] Expand attributes

#[must_use]fn ne(&self, other: &Rhs) -> bool[−]

This method tests for !=.

impl StructuralPartialEq for CCLK_SAMPLE_PHASE_A