[−][src]Enum lpc55_pac::syscon::fcclksel1::SEL_A
pub enum SEL_A { ENUM_0X0, ENUM_0X1, ENUM_0X2, ENUM_0X3, ENUM_0X4, ENUM_0X5, ENUM_0X6, ENUM_0X7, }
Flexcomm Interface 1 clock source select for Fractional Rate Divider.
Value on reset: 7
Variants
0: Main clock.
1: system PLL divided clock.
2: FRO 12 MHz clock.
3: FRO 96 MHz clock.
4: FRO 1MHz clock.
5: MCLK clock.
6: Oscillator 32 kHz clock.
7: No clock.
Trait Implementations
impl Clone for SEL_A[src][+]
impl Copy for SEL_A[src]
impl Debug for SEL_A[src][+]
impl From<SEL_A> for u8[src][+]
impl PartialEq<SEL_A> for SEL_A[src][+]
impl StructuralPartialEq for SEL_A[src]
Auto Trait Implementations
Blanket Implementations
impl<T> Any for T where
T: 'static + ?Sized, [src][+]
T: 'static + ?Sized,
impl<T> Borrow<T> for T where
T: ?Sized, [src][+]
T: ?Sized,
impl<T> BorrowMut<T> for T where
T: ?Sized, [src][+]
T: ?Sized,
impl<T> From<T> for T[src][+]
impl<T, U> Into<U> for T where
U: From<T>, [src][+]
U: From<T>,
impl<T> Same<T> for T[src]
type Output = T
Should always be Self
impl<T, U> TryFrom<U> for T where
U: Into<T>, [src][+]
U: Into<T>,
impl<T, U> TryInto<U> for T where
U: TryFrom<T>, [src][+]
U: TryFrom<T>,