[−][src]Enum lpc55_pac::spi0::fifotrig::TXLVLENA_A
pub enum TXLVLENA_A { DISABLED, ENABLED, }
Transmit FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET, or a DMA trigger if DMATX in FIFOCFG is set.
Value on reset: 0
Variants
0: Transmit FIFO level does not generate a FIFO level trigger.
1: An trigger will be generated if the transmit FIFO level reaches the value specified by the TXLVL field in this register.
Trait Implementations
impl Clone for TXLVLENA_A
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impl Copy for TXLVLENA_A
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impl Debug for TXLVLENA_A
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impl From<TXLVLENA_A> for bool
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impl PartialEq<TXLVLENA_A> for TXLVLENA_A
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impl StructuralPartialEq for TXLVLENA_A
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Auto Trait Implementations
Blanket Implementations
impl<T> Any for T where
T: 'static + ?Sized,
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T: 'static + ?Sized,
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T: ?Sized,
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T: ?Sized,
impl<T> BorrowMut<T> for T where
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T: ?Sized,
impl<T> From<T> for T
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impl<T, U> Into<U> for T where
U: From<T>,
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U: From<T>,
impl<T> Same<T> for T
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type Output = T
Should always be Self
impl<T, U> TryFrom<U> for T where
U: Into<T>,
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U: Into<T>,
impl<T, U> TryInto<U> for T where
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