Type Definition lpc55_pac::spi0::div::R

type R = R<u32, DIV>;

Reader of register DIV

Implementations

impl R

pub fn divval(&self) -> DIVVAL_R

Bits 0:15 - Rate divider value. Specifies how the Flexcomm clock (FCLK) is divided to produce the SPI clock rate in master mode. DIVVAL is -1 encoded such that the value 0 results in FCLK/1, the value 1 results in FCLK/2, up to the maximum possible divide value of 0xFFFF, which results in FCLK/65536.