[−][src]Type Definition lpc55_pac::sdif::status::R

type R = R<u32, STATUS>;

Reader of register STATUS

Implementations

`impl R`[src]

`pub fn fifo_rx_watermark(&self) -> FIFO_RX_WATERMARK_R`[src]

Bit 0 - FIFO reached Receive watermark level; not qualified with data transfer.

`pub fn fifo_tx_watermark(&self) -> FIFO_TX_WATERMARK_R`[src]

Bit 1 - FIFO reached Transmit watermark level; not qualified with data transfer.

`pub fn fifo_empty(&self) -> FIFO_EMPTY_R`[src]

Bit 2 - FIFO is empty status.

`pub fn fifo_full(&self) -> FIFO_FULL_R`[src]

Bit 3 - FIFO is full status.

`pub fn cmdfsmstates(&self) -> CMDFSMSTATES_R`[src]

Bits 4:7 - Command FSM states: 0 - Idle 1 - Send init sequence 2 - Tx cmd start bit 3 - Tx cmd tx bit 4 - Tx cmd index + arg 5 - Tx cmd crc7 6 - Tx cmd end bit 7 - Rx resp start bit 8 - Rx resp IRQ response 9 - Rx resp tx bit 10 - Rx resp cmd idx 11 - Rx resp data 12 - Rx resp crc7 13 - Rx resp end bit 14 - Cmd path wait NCC 15 - Wait; CMD-to-response turnaround NOTE: The command FSM state is represented using 19 bits.