[−][src]Module lpc55_pac::rtc::ctrl
RTC control register
Structs
| ALARM1HZ_W | Write proxy for field |
| ALARMDPD_EN_W | Write proxy for field |
| RTC1KHZ_EN_W | Write proxy for field |
| RTC_EN_W | Write proxy for field |
| RTC_OSC_BYPASS_W | Write proxy for field |
| RTC_OSC_PD_W | Write proxy for field |
| RTC_SUBSEC_ENA_W | Write proxy for field |
| SWRESET_W | Write proxy for field |
| WAKE1KHZ_W | Write proxy for field |
| WAKEDPD_EN_W | Write proxy for field |
Enums
| ALARM1HZ_A | RTC 1 Hz timer alarm flag status. |
| ALARMDPD_EN_A | RTC 1 Hz timer alarm enable for Deep power-down. |
| RTC1KHZ_EN_A | RTC 1 kHz clock enable. This bit can be set to 0 to conserve power if the 1 kHz timer is not used. This bit has no effect when the RTC is disabled (bit 7 of this register is 0). |
| RTC_EN_A | RTC enable. |
| RTC_OSC_BYPASS_A | RTC oscillator bypass control. |
| RTC_OSC_PD_A | RTC oscillator power-down control. |
| RTC_SUBSEC_ENA_A | RTC Sub-second counter control. |
| SWRESET_A | Software reset control |
| WAKE1KHZ_A | RTC 1 kHz timer wake-up flag status. |
| WAKEDPD_EN_A | RTC 1 kHz timer wake-up enable for Deep power-down. |
Type Definitions
| ALARM1HZ_R | Reader of field |
| ALARMDPD_EN_R | Reader of field |
| R | Reader of register CTRL |
| RTC1KHZ_EN_R | Reader of field |
| RTC_EN_R | Reader of field |
| RTC_OSC_BYPASS_R | Reader of field |
| RTC_OSC_PD_R | Reader of field |
| RTC_SUBSEC_ENA_R | Reader of field |
| SWRESET_R | Reader of field |
| W | Writer for register CTRL |
| WAKE1KHZ_R | Reader of field |
| WAKEDPD_EN_R | Reader of field |