[−][src]Enum lpc55_pac::i2c0::msttime::MSTSCLHIGH_A
pub enum MSTSCLHIGH_A { CLOCKS_2, CLOCKS_3, CLOCKS_4, CLOCKS_5, CLOCKS_6, CLOCKS_7, CLOCKS_8, CLOCKS_9, }
Master SCL High time. Specifies the minimum high time that will be asserted by this master on SCL. Other masters in a multi-master system could shorten this time. This corresponds to the parameter tHIGH in the I2C bus specification. I2C bus specification parameters tSU;STO and tHD;STA have the same values and are also controlled by MSTSCLHIGH.
Value on reset: 7
Variants
0: 2 clocks. Minimum SCL high time is 2 clock of the I2C clock pre-divider.
1: 3 clocks. Minimum SCL high time is 3 clocks of the I2C clock pre-divider .
2: 4 clocks. Minimum SCL high time is 4 clock of the I2C clock pre-divider.
3: 5 clocks. Minimum SCL high time is 5 clock of the I2C clock pre-divider.
4: 6 clocks. Minimum SCL high time is 6 clock of the I2C clock pre-divider.
5: 7 clocks. Minimum SCL high time is 7 clock of the I2C clock pre-divider.
6: 8 clocks. Minimum SCL high time is 8 clock of the I2C clock pre-divider.
7: 9 clocks. Minimum SCL high time is 9 clocks of the I2C clock pre-divider.
Trait Implementations
impl Clone for MSTSCLHIGH_A
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impl Copy for MSTSCLHIGH_A
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impl Debug for MSTSCLHIGH_A
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impl From<MSTSCLHIGH_A> for u8
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impl PartialEq<MSTSCLHIGH_A> for MSTSCLHIGH_A
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impl StructuralPartialEq for MSTSCLHIGH_A
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Auto Trait Implementations
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Should always be Self
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