[−][src]Module lpc55_pac::dma0::channel::ctlstat
Control and status register for DMA channel .
Enums
| TRIG_A | Trigger flag. Indicates that the trigger for this channel is currently set. This bit is cleared at the end of an entire transfer or upon reload when CLRTRIG = 1. |
| VALIDPENDING_A | Valid pending flag for this channel. This bit is set when a 1 is written to the corresponding bit in the related SETVALID register when CFGVALID = 1 for the same channel. |
Type Definitions
| R | Reader of register CTLSTAT |
| TRIG_R | Reader of field |
| VALIDPENDING_R | Reader of field |